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| author | Jiong Wang <jiong.wang@arm.com> | 2017-08-09 17:52:54 +0100 |
|---|---|---|
| committer | Jiong Wang <jiong.wang@arm.com> | 2017-08-09 17:52:54 +0100 |
| commit | cc4a945a2687184c7cd4a0572e02965829517408 (patch) | |
| tree | 571345ba14e0aa796cdf3ba2cd48a4515edc52f5 /opcodes/ChangeLog | |
| parent | cd3af38d7b3e66117e7964b6fea45e57d47169ff (diff) | |
| download | gdb-cc4a945a2687184c7cd4a0572e02965829517408.zip gdb-cc4a945a2687184c7cd4a0572e02965829517408.tar.gz gdb-cc4a945a2687184c7cd4a0572e02965829517408.tar.bz2 | |
[ARM] Don't warn on REG_SP when used in CRC32 instructions
According to ARMv8-A architecture manual, REG_SP is allowed in CRC32
instructions in Thumb mode. It is REG_PC that will cause unpredictable
behaviours on both ARM and Thumb.
This patch removes the incorrect warning on Thumb mode.
Meanwhile the disassembler is updated to use format "<bitfield>R" instead of
"<bitfield>S". "<bitfield>S" is not used elsewhere. so I have deleted related
code from the disassembler.
gas/
* config/tc-arm.c (do_crc32_1): Remove warning on REG_SP for thumb_mode.
* testsuite/gas/arm/crc32-armv8-a-bad.d: Update exepcted result.
* testsuite/gas/arm/crc32-armv8-r-bad.d: Likewise.
* testsuite/gas/arm/crc32-armv8-a.d: Likewise.
* testsuite/gas/arm/crc32-armv8-r.d: Likewise.
* testsuite/gas/arm/crc32-armv8-ar-bad.s: Update test case.
* testsuite/gas/arm/crc32-armv8-ar.s: Likewise.
* testsuite/gas/arm/crc32-bad.l: Update expected error message.
opcode/
* arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
register operands in CRC instructions.
(print_insn_thumb32): Remove "<bitfield>S" support. Updated the
comments.
Diffstat (limited to 'opcodes/ChangeLog')
| -rw-r--r-- | opcodes/ChangeLog | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 4414037..5cbe7e0 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2017-08-09 Jiong Wang <jiong.wang@arm.com> + + * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for + register operands in CRC instructions. + (print_insn_thumb32): Remove "<bitfield>S" support. Updated the + comments. + 2017-08-07 H.J. Lu <hongjiu.lu@intel.com> * disassemble.c (disassembler): Mark big and mach with |