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2022-01-24Update Bulgarian, French, Romaniam and Ukranian translation for some of the s...Nick Clifton1-0/+5
2022-01-22Change version number to 2.38.50 and regenerate filesNick Clifton1-0/+5
2022-01-22Add markers for 2.38 branchNick Clifton1-0/+4
2022-01-17Update the config.guess and config.sub files from the master repository and r...Nick Clifton1-0/+5
2022-01-02Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2021-12-02Allow the --visualize-jumps feature to work with the AVR disassembler.Marcus Nilsson1-0/+5
2021-11-26opcodes/riscv: add disassembler options support to libopcodesAndrew Burgess1-0/+9
2021-11-25Fix building the AArch64 assembler and disassembler when assertions are disab...Nick Clifton1-0/+7
2021-11-25Updated French translation for the opcodes directory.Nick Clifton1-0/+4
2021-10-27opcodes: Fix RPATH not being set for dynamic libbfd dependencyMaciej W. Rozycki1-0/+8
2021-09-27configure: regenerate in all projects that use libtool.m4Nick Alcock1-0/+4
2021-09-25PowerPC: Enable mfppr mfppr32, mtppr and mtppr32 extended mnemonics on POWER5Peter Bergner1-0/+5
2021-09-20riscv: print .2byte or .4byte before an unknown instruction encodingAndrew Burgess1-0/+6
2021-09-02Fix the V850 assembler's generation of relocations for the st.b instruction.Nick Clifton1-0/+6
2021-08-17opcodes: Fix the auxiliary register numbers for ARC HSShahab Vahedi1-0/+4
2021-08-10Updated Serbian and Russian translations for various sub-directoriesNick Clifton1-0/+4
2021-07-27Correct gs264e bfd_mach in mips_arch_choices.Chenghua Xu1-0/+4
2021-07-07Add changelog entries for last commitAndreas Krebbel1-0/+4
2021-07-03Update version number and regenerate filesNick Clifton1-0/+5
2021-07-03Add markers for 2.37 branchNick Clifton1-0/+4
2021-07-02Re: Fix minor NDS32 renaming snafuAlan Modra1-0/+9
2021-07-01cgen: split GUILE setting outMike Frysinger1-0/+6
2021-07-01opcodes: constify & local meps macrosMike Frysinger1-0/+7
2021-07-01opcodes: cleanup nds32 variablesMike Frysinger1-0/+17
2021-07-01opcodes: constify & localize z80 opcodesMike Frysinger1-0/+5
2021-07-01opcodes: constify & scope microblaze opcodesMike Frysinger1-0/+12
2021-07-01opcodes: constify aarch64_opcode_tablesMike Frysinger1-1/+6
2021-06-22opcodes: make use of __builtin_popcount when availableAndrew Burgess1-0/+5
2021-06-22picojava assembler and disassembler fixesAlan Modra1-0/+5
2021-06-19ubsan: vax: pointer overflowAlan Modra1-0/+4
2021-06-19Fix another strncpy warningAlan Modra1-0/+5
2021-06-17powerpc: move cell "or rx,rx,rx" hintsAlan Modra1-0/+5
2021-06-03PR1202, mcore disassembler: wrong address looptAlan Modra1-0/+6
2021-06-02arc: Construct disassembler options dynamicallyShahab Vahedi1-0/+8
2021-05-29PowerPC table driven -Mraw disassemblyAlan Modra1-0/+15
2021-05-29MIPS/opcodes: Reorder legacy COP0, COP2, COP3 opcode instructionsMaciej W. Rozycki1-0/+5
2021-05-29MIPS/opcodes: Accurately record coprocessor opcode CPU/ISA membershipMaciej W. Rozycki1-0/+10
2021-05-29MIPS/opcodes: Remove DMFC3 and DMTC3 instructionsMaciej W. Rozycki1-0/+5
2021-05-29MIPS/opcodes: Disassemble the RFE instructionMaciej W. Rozycki1-0/+5
2021-05-29MIPS/opcodes: Add legacy CP1 control register namesMaciej W. Rozycki1-0/+10
2021-05-29MIPS/opcodes: Do not use CP0 register names for control registersMaciej W. Rozycki1-0/+14
2021-05-29MIPS/opcodes: Add TX39 CP0 register namesMaciej W. Rozycki1-0/+6
2021-05-29MIPS/opcodes: Free up redundant `g' operand codeMaciej W. Rozycki1-0/+6
2021-05-29microMIPS/opcodes: Refer FPRs rather than FCRs with DMTC1Maciej W. Rozycki1-0/+5
2021-05-27PowerPC: Add new xxmr and xxlnot extended mnemonicsPeter Bergner1-0/+4
2021-05-25Regen cris filesAlan Modra1-0/+7
2021-05-24opcodes: cris: move desc & opc files from sim/Mike Frysinger1-0/+11
2021-05-18RISC-V: PR27814, Objdump crashes when disassembling a non-ELF RISC-V binary.Job Noorman1-0/+6
2021-05-17arm: Fix bugs with MVE vmov from two GPRs to vector lanesAlex Coplan1-0/+9
2021-05-11Fix an illegal memory access when attempting to disassemble a corrupt TIC30 b...Nick Clifton1-0/+6
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