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| author | Andrew Burgess <andrew.burgess@embecosm.com> | 2021-09-18 10:42:41 +0100 |
|---|---|---|
| committer | Andrew Burgess <andrew.burgess@embecosm.com> | 2021-09-20 09:45:34 +0100 |
| commit | 6a7f57668afcd841e8fc6b507a27bb20e9209fa9 (patch) | |
| tree | dcf2fb8b5648e7ee4b608dd7be16cf37e4b4eb71 /opcodes/ChangeLog | |
| parent | d467335403fda3c4774e27d9725b3528e1799398 (diff) | |
| download | gdb-6a7f57668afcd841e8fc6b507a27bb20e9209fa9.zip gdb-6a7f57668afcd841e8fc6b507a27bb20e9209fa9.tar.gz gdb-6a7f57668afcd841e8fc6b507a27bb20e9209fa9.tar.bz2 | |
riscv: print .2byte or .4byte before an unknown instruction encoding
When the RISC-V disassembler encounters an unknown instruction, it
currently just prints the value of the bytes, like this:
Dump of assembler code for function custom_insn:
0x00010132 <+0>: addi sp,sp,-16
0x00010134 <+2>: sw s0,12(sp)
0x00010136 <+4>: addi s0,sp,16
0x00010138 <+6>: 0x52018b
0x0001013c <+10>: 0x9c45
My proposal, in this patch, is to change the behaviour to this:
Dump of assembler code for function custom_insn:
0x00010132 <+0>: addi sp,sp,-16
0x00010134 <+2>: sw s0,12(sp)
0x00010136 <+4>: addi s0,sp,16
0x00010138 <+6>: .4byte 0x52018b
0x0001013c <+10>: .2byte 0x9c45
Adding the .4byte and .2byte opcodes. The benefit that I see here is
that in the patched version of the tools, the disassembler output can
be fed back into the assembler and it should assemble to the same
binary format. Before the patch, the disassembler output is invalid
assembly.
I've started a RISC-V specific test file under binutils so that I can
add a test for this change.
binutils/ChangeLog:
* testsuite/binutils-all/riscv/riscv.exp: New file.
* testsuite/binutils-all/riscv/unknown.d: New file.
* testsuite/binutils-all/riscv/unknown.s: New file.
opcodes/ChangeLog:
* riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
before an unknown instruction, '%d' is replaced with the
instruction length.
Diffstat (limited to 'opcodes/ChangeLog')
| -rw-r--r-- | opcodes/ChangeLog | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index ca3206d..a32af60 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2021-09-20 Andrew Burgess <andrew.burgess@embecosm.com> + + * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode + before an unknown instruction, '%d' is replaced with the + instruction length. + 2021-09-02 Nick Clifton <nickc@redhat.com> PR 28292 |