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authorMaciej W. Rozycki <macro@orcam.me.uk>2021-05-29 03:26:33 +0200
committerMaciej W. Rozycki <macro@orcam.me.uk>2021-05-29 03:26:33 +0200
commit49149d595cfdfa32611b2abba564b9b5d7542c91 (patch)
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parent28b7d4f1c98fe62fb1d8f51c18dddca174820962 (diff)
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MIPS/opcodes: Reorder legacy COP0, COP2, COP3 opcode instructions
Group legacy instructions using the COP0, COP2, COP3 opcodes together and by their coprocessor number, and move them towards the end of the opcode table. No functional change. With the addition of explicit ISA exclusions this is maybe not strictly necessary anymore as the individual legacy instructions are not supposed to match ISA levels or CPU implementations that have discarded them or replaced with a new instruction each, but let's not have them scattered randomly across blocks of unrelated instruction sets where someone chose to put them previously. Perhaps they could be put back in alphabetical order in the main instruction block, but let's leave it for another occasion. opcodes/ * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2, COP3 opcode instructions.
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2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
+ * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
+ COP3 opcode instructions.
+
+2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
+
* mips-opc.c (mips_builtin_opcodes): Update exclusion list for
"ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
"swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",