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AgeCommit message (Expand)AuthorFilesLines
2019-10-28Fix potentially illegal shift and assign operation in CSKY disassembler.Nick Clifton1-0/+5
2019-10-28Fix buffer overrun in TIC30 disassembler.Nick Clifton1-0/+10
2019-10-28Stop potential illegal memory access in the NS32K disassembler.Nick Clifton1-0/+8
2019-10-28Prevent an illegal memory access in the xgate disassembler.Nick Clifton1-0/+5
2019-10-25Fix potential undefined behaviour in the RX disassembler.Nick Clifton1-0/+5
2019-10-23Fix typo in RX disassembler error messages.Nick Clifton1-0/+9
2019-10-22Prevent more potential illegal memory accesses in the RX disassembler.Nick Clifton1-0/+7
2019-10-16Fix potential illegal memory access when disassembling corrupt RX binaries.Nick Clifton1-0/+10
2019-10-09Fix the disassembly of the LDS and STS instructions of the AVR architecture.Nick Clifton1-0/+6
2019-10-07x86/Intel: correct MOVSD and CMPSD handlingJan Beulich1-0/+6
2019-09-23m68k bfd.h tidyAlan Modra1-0/+4
2019-09-23mips bfd.h tidyAlan Modra1-0/+5
2019-09-20x86-64: fix handling of PUSH/POP of segment registerJan Beulich1-0/+7
2019-09-19bfd_section_* macrosAlan Modra1-0/+4
2019-09-18Re-generate many configure and Makefile.in filesSimon Marchi1-0/+5
2019-09-17RISC-V: Gate opcode tables by enum rather than string.Jim Wilson1-0/+6
2019-09-16Update version to 2.33.50 and regenerate configure scripts.Phil Blundell1-0/+4
2019-09-10Use the correct alias for the M68K tdiv instruction.Miod Vallat1-0/+5
2019-09-09Add markers for 2.33 branch to NEWS and ChangeLog files.Phil Blundell1-0/+4
2019-09-03Fix buffer underrun bug in the TI C30 disassembler.Nick Clifton1-0/+6
2019-09-03Fix a potential buffer overrun in the MMIX disassembler when processing a cor...Nick Clifton1-0/+10
2019-08-27Add support for the MVE VMOV instruction to the ARM assembler. This instruct...Srinath Parvathaneni1-0/+6
2019-08-22[AArch64][gas] Update MTE system register encodingsKyrylo Tkachov1-0/+6
2019-08-12Modify the ARM encoding and decoding of SQRSHRL and UQRSHLL MVE instructions.Srinath Parvathaneni1-0/+7
2019-08-07Prevent objdump from aborting when asked to disassemble an unknown type of AR...Phillipe Antoine1-0/+8
2019-08-07x86: drop stray FloatMFJan Beulich1-0/+7
2019-08-05Removes support in the ARM assembler for the unsigned variants of the VQ(R)DM...Barnaby Wilks1-0/+5
2019-07-30RISC-V: Fix minor issues with FP csr instructions.Jim Wilson1-0/+8
2019-07-24[ARC] Update disassembler opcode selectionClaudiu Zissulescu1-0/+7
2019-07-24[ARC] Update ARC opcode tableClaudiu Zissulescu1-0/+8
2019-07-23[AArch64] Add support for GMID_EL1 register for +memtagKyrylo Tkachov1-0/+5
2019-07-23Add Changelog entry missing from previous delta.Nick Clifton1-0/+5
2019-07-19cpu,opcodes,gas: use %r0 and %r6 instead of %a and %ctf in eBPF disassemblerJose E. Marchesi1-0/+4
2019-07-17x86: drop stale Mem enumeratorJan Beulich1-0/+8
2019-07-16x86: make RegMem an opcode modifierJan Beulich1-0/+23
2019-07-16x86: fold SReg{2,3}Jan Beulich1-0/+13
2019-07-15cpu,opcodes,gas: fix explicit arguments to eBPF ldabs instructionsJose E. Marchesi1-0/+6
2019-07-14cpu,opcodes,gas: fix arguments to ldabs and ldind eBPF instructionsJose E. Marchesi1-0/+5
2019-07-10arm-dis.c (print_insn_coprocessor): Rename index to index_operand.Hans-Peter Nilsson1-0/+5
2019-07-05Kito's 5-part patch set to improve .insn support.Jim Wilson1-0/+9
2019-07-02[AArch64] Allow MOVPRFX to be used with FMOVRichard Sandiford1-0/+5
2019-07-02[AArch64] Add missing C_MAX_ELEM flags for SVE conversionsRichard Sandiford1-0/+5
2019-07-02[AArch64] Fix bogus MOVPRFX warning for GPR form of CPYRichard Sandiford1-0/+5
2019-07-01[gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AESMatthew Malcomson1-0/+15
2019-07-01x86: drop Vec_Imm4Jan Beulich1-0/+10
2019-07-01x86: limit ImmExt abuseJan Beulich1-0/+10
2019-07-01x86: optimize AND/OR with twice the same registerJan Beulich1-0/+6
2019-07-01x86-64: optimize certain commutative VEX-encoded insnsJan Beulich1-0/+32
2019-07-01x86: optimize EVEX packed integer logical instructionsJan Beulich1-0/+6
2019-07-01x86: add missing pseudo ops for VPCLMULQDQ ISA extensionJan Beulich1-0/+7
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