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| author | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2019-08-27 12:08:21 +0100 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2019-08-27 12:08:21 +0100 |
| commit | c4a23bf878f2e9a64034006c91596401faf6db3e (patch) | |
| tree | e2dbc28c785dec21ae1fa252059f22f5af2f6b46 /opcodes/ChangeLog | |
| parent | e8fffdff93dc455842a08b12cd4c05bd69aef518 (diff) | |
| download | gdb-c4a23bf878f2e9a64034006c91596401faf6db3e.zip gdb-c4a23bf878f2e9a64034006c91596401faf6db3e.tar.gz gdb-c4a23bf878f2e9a64034006c91596401faf6db3e.tar.bz2 | |
Add support for the MVE VMOV instruction to the ARM assembler. This instruction copies the value of one vector register to another vector register. The patch also modifies the decoding of VORR instruction which is effecting decoding of VMOV instruction.
gas * config/tc-arm.c (parse_neon_mov): Add check to accept vector
register to both the arguments in VMOV instruction.
* testsuite/gas/arm/mve-vmov-1.d: Modify.
* testsuite/gas/arm/mve-vmov-1.s: Likewise.
* testsuite/gas/arm/mve-vorr.d: Likewise.
opcodes * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
(is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
(print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
Diffstat (limited to 'opcodes/ChangeLog')
| -rw-r--r-- | opcodes/ChangeLog | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 0017bd4..bec2b59 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com> + + * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC. + (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC. + (print_insn_mve): Add condition to check Qm==Qn of VORR instruction. + 2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1, |