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| author | Kito Cheng <kito.cheng@sifive.com> | 2025-01-17 09:53:01 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2025-01-17 12:34:50 +0800 |
| commit | 1c618df71307a9b1403c55ade463bf23e1d7e770 (patch) | |
| tree | e6f0dbacc5db332466af0f5fbf2996e04667a9fb /opcodes | |
| parent | b4681c2e8a46af1559990398bbc8f010d26312ca (diff) | |
| download | gdb-1c618df71307a9b1403c55ade463bf23e1d7e770.zip gdb-1c618df71307a9b1403c55ade463bf23e1d7e770.tar.gz gdb-1c618df71307a9b1403c55ade463bf23e1d7e770.tar.bz2 | |
RISC-V: Use t2 for tail if Zicfilp enabled
This change is to make tail conform with software guarded jump of Zicfilp. The
reason to not choose t1 as the label register is that t1 is also as .got.plt
offset of _dl_runtime_resolve in PLT.
See more: https://github.com/riscv-non-isa/riscv-asm-manual/pull/93
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/riscv-opc.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index ed37eb7..ceb94a5 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -465,6 +465,7 @@ const struct riscv_opcode riscv_opcodes[] = {"jal", 0, INSN_CLASS_I, "d,a", MATCH_JAL, MASK_JAL, match_opcode, INSN_JSR }, {"call", 0, INSN_CLASS_I, "d,c", (X_T1 << OP_SH_RS1), (int) M_CALL, NULL, INSN_MACRO }, {"call", 0, INSN_CLASS_I, "c", (X_RA << OP_SH_RS1)|(X_RA << OP_SH_RD), (int) M_CALL, NULL, INSN_MACRO }, +{"tail", 0, INSN_CLASS_ZICFILP, "c", (X_T2 << OP_SH_RS1), (int) M_CALL, NULL, INSN_MACRO }, {"tail", 0, INSN_CLASS_I, "c", (X_T1 << OP_SH_RS1), (int) M_CALL, NULL, INSN_MACRO }, {"jump", 0, INSN_CLASS_I, "c,s", 0, (int) M_CALL, match_rs1_nonzero, INSN_MACRO }, {"nop", 0, INSN_CLASS_C, "", MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS }, |