| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2019-01-01 | Update year range in copyright notice of binutils files | Alan Modra | 1 | -0/+4 |
| 2019-01-01 | ChangeLog rotation | Alan Modra | 1 | -878/+2 |
| 2018-12-28 | PR24028, PPC_INT_FMT | Alan Modra | 1 | -0/+5 |
| 2018-12-14 | elf: Add PT_GNU_PROPERTY segment type | H.J. Lu | 1 | -0/+6 |
| 2018-12-11 | Fix a failure in the libiberty testsuite by increasing the recursion limit to... | Nick Clifton | 1 | -0/+5 |
| 2018-12-07 | elf: Report property change when merging properties | H.J. Lu | 1 | -0/+4 |
| 2018-12-07 | Synchronize libiberty with gcc and add --no-recruse-limit option to tools tha... | Nick Clifton | 1 | -0/+5 |
| 2018-12-06 | PowerPC @l, @h and @ha warnings, plus VLE e_li | Alan Modra | 1 | -0/+4 |
| 2018-12-06 | opcodes/riscv: Hide '.L0 ' fake symbols | Andrew Burgess | 1 | -0/+6 |
| 2018-12-03 | RISC-V: Accept version, supervisor ext and more than one NSE for -march. | Jim Wilson | 1 | -0/+5 |
| 2018-11-27 | RISC-V: Add .insn CA support. | Jim Wilson | 1 | -0/+5 |
| 2018-11-13 | [ARM] Improve indentation of ARM architecture declarations | Thomas Preud'homme | 1 | -0/+59 |
| 2018-11-12 | [BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging Extension | Sudakshina Das | 1 | -0/+5 |
| 2018-11-12 | [BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Exten... | Sudakshina Das | 1 | -0/+6 |
| 2018-11-12 | [BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Ex... | Sudakshina Das | 1 | -0/+5 |
| 2018-11-12 | [BINUTILS, AARCH64, 1/8] Add support for Memory Tagging Extension for ARMv8.5-A | Sudakshina Das | 1 | -0/+4 |
| 2018-11-07 | Add support for new load commands added by Apple to the MACH-O file format. | Roman Bolshakov | 1 | -0/+10 |
| 2018-11-06 | Add support for a couple of new Mach-O commands. | Nick Clifton | 1 | -0/+5 |
| 2018-11-06 | [BINUTILS, ARM] Add Armv8.5-A to select_arm_features and update macros. | Sudakshina Das | 1 | -0/+6 |
| 2018-10-26 | Support AT_HWCAP2 on FreeBSD. | John Baldwin | 1 | -0/+4 |
| 2018-10-09 | [PATCH, BINUTULS, AARCH64, 9/9] Add SSBS to MSR/MRS | Sudakshina Das | 1 | -0/+5 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and ID_PFR2_EL1 system registers | Sudakshina Das | 1 | -0/+6 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 7/9] Add BTI instruction | Sudakshina Das | 1 | -0/+9 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 6/9] Add Random number instructions | Sudakshina Das | 1 | -0/+4 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 5/9] Add DC CVADP instruction | Sudakshina Das | 1 | -0/+4 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructions | Sudakshina Das | 1 | -0/+7 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 3/9] Add instruction SB for ARMv8.5-A | Sudakshina Das | 1 | -0/+5 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 2/9] Add Data procoessing instructions for ARMv8.5-A | Sudakshina Das | 1 | -0/+6 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 1/9] Add -march=armv8.5-a and related internal fea... | Sudakshina Das | 1 | -0/+5 |
| 2018-10-08 | Separate header PT_LOAD for -z separate-code | Alan Modra | 1 | -0/+4 |
| 2018-10-05 | [Arm, 3/3] Add Execution and Data Prediction instructions for AArch32 | Sudakshina Das | 1 | -0/+5 |
| 2018-10-05 | [Arm, 2/3] Add instruction SB for AArch32 | Sudakshina Das | 1 | -0/+5 |
| 2018-10-05 | [Arm, 1/3] Add -march=armv8.5-a and related internal feature macros to AArch32 | Sudakshina Das | 1 | -0/+5 |
| 2018-10-05 | or1k: Add the l.adrp insn and supporting relocations | Stafford Horne | 1 | -0/+8 |
| 2018-10-05 | or1k: Add relocations for high-signed and low-stores | Richard Henderson | 1 | -0/+6 |
| 2018-10-03 | AArch64: Add SVE constraints verifier. | Tamar Christina | 1 | -0/+8 |
| 2018-10-03 | AArch64: Refactor verifiers to make more general. | Tamar Christina | 1 | -0/+5 |
| 2018-10-03 | AArch64: Refactor err_type. | Tamar Christina | 1 | -0/+5 |
| 2018-10-03 | AArch64: Wire through instr_sequence | Tamar Christina | 1 | -0/+5 |
| 2018-10-03 | AArch64: Mark sve instructions that require MOVPRFX constraints | Tamar Christina | 1 | -0/+6 |
| 2018-10-03 | Make print_insn_s12z public. | John Darrington | 1 | -0/+4 |
| 2018-10-02 | RISC-V: Add fence.tso instruction | Palmer Dabbelt | 1 | -0/+5 |
| 2018-10-02 | [ARC] Entries to Changelog for previous commits. | Cupertino Miranda | 1 | -0/+4 |
| 2018-09-21 | ELF: Don't include zero size sections at start of PT_NOTE segment | H.J. Lu | 1 | -0/+6 |
| 2018-09-20 | Andes Technology has good news for you, we plan to update the nds32 port of b... | Nick Clifton | 1 | -0/+13 |
| 2018-09-20 | Handle missing Solaris auxv entries | Rainer Orth | 1 | -0/+8 |
| 2018-09-05 | Disable -Wformat-nonliteral in parts of printcmd.c | Simon Marchi | 1 | -0/+4 |
| 2018-08-31 | PowerPC64 higher REL16 relocations | Alan Modra | 1 | -0/+7 |
| 2018-08-30 | RISC-V: Allow instruction require more than one extension | Jim Wilson | 1 | -0/+6 |
| 2018-08-29 | [MIPS] Add Loongson 2K1000 proccessor support. | Chenghua Xu | 1 | -0/+4 |
