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authorPalmer Dabbelt <palmer@sifive.com>2018-10-02 08:26:32 -0700
committerPalmer Dabbelt <palmer@sifive.com>2018-10-02 08:26:32 -0700
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RISC-V: Add fence.tso instruction
The RISC-V memory model has been ratified, and it includes an additional fence: "fence.tso". This pseudo instruction extends one of the previously reserved full fence patterns to be less restrictive, and therefor will execute correctly on all existing microarchitectures. Thus there is no reason to allow this instruction to be disabled (or unconverted to a full fence), so it's just unconditionally allowed. I've added a test case for GAS to check that "fence.tso" correctly assembles on rv32i-based targets. I checked to see that "fence.tso" appears in "gas.log", but that's the only testing I've done. gas/ChangeLog 2018-10-02 Palmer Dabbelt <palmer@sifive.com> * testsuite/gas/riscv/fence-tso.d: New file. * testsuite/gas/riscv/fence-tso.s: Likewise. include/ChangeLog 2018-10-02 Palmer Dabbelt <palmer@sifive.com> * opcode/riscv-opc.h (MATCH_FENCE_TSO): New define. (MASK_FENCE_TSO): Likewise. opcodes/ChangeLog 2018-10-02 Palmer Dabbelt <palmer@sifive.com> * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
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+2018-10-02 Palmer Dabbelt <palmer@sifive.com>
+
+ * opcode/riscv-opc.h (MATCH_FENCE_TSO): New define.
+ (MASK_FENCE_TSO): Likewise.
+
2018-10-01 Cupertino Miranda <cmiranda@synopsys.com>
* arc-reloc.def (ARC_TLS_LE_32): Updated reloc formula.