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2016-12-05Fix fault in assembler when passed a bogus input file.Nick Clifton2-0/+16
PR gas/20902 * read.c (next_char_of_string): Do end advance past the end of the buffer.
2016-12-05Fix ICE in assembler when passed a bogus input file.Nick Clifton3-2/+11
PR gas/20904 * as.h (SKIP_ALL_WHITESPACE): New macro. * expr.c (operand): Use it.
2016-12-05[ARM] Add ARMv8.3 VCMLA and VCADD instructionsSzabolcs Nagy7-0/+281
Add support for VCMLA and VCADD advanced SIMD complex number instructions. The command line option is -march=armv8.3-a+fp16+simd for enabling all instructions. In arm-dis.c the formatting syntax was abused a bit to select between 0 vs 90 or 180 vs 270 or 90 vs 270 based on a bit value instead of duplicating entries in the opcode table. gas/ * config/tc-arm.c (do_vcmla, do_vcadd): Define. (neon_scalar_for_vcmla): Define. (enum operand_parse_code): Add OP_IROT1 and OP_IROT2. (NEON_ENC_TAB): Add DDSI and QQSI variants. (insns): Add vcmla and vcadd. * testsuite/gas/arm/armv8_3-a-simd.d: New. * testsuite/gas/arm/armv8_3-a-simd.s: New. * testsuite/gas/arm/armv8_3-a-simd-bad.d: New. * testsuite/gas/arm/armv8_3-a-simd-bad.l: New. * testsuite/gas/arm/armv8_3-a-simd-bad.s: New. opcodes/ * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd. (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
2016-12-05[ARC] Don't check extAuxRegister second argument for sign.Claudiu Zissulescu6-11/+47
gas/ 2016-12-05 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/textauxregister-1.d: New file. * testsuite/gas/arc/textauxregister-1.s: Likewise. * testsuite/gas/arc/textcondcode-err.s: Likewise. * testsuite/gas/arc/textcoreregister-err.s: Likewise. * config/tc-arc.c (tokenize_extregister): Return bfd_boolean, don't check second argument of extension auxiliary register for signess. (arc_extcorereg): Consider the return of tokenize_extregister function call.
2016-12-05[ARM] Add ARMv8.3 VJCVT instructionSzabolcs Nagy7-0/+68
Add support for VJCVT javascript conversion instruction. gas/ * config/tc-arm.c (arm_ext_v8_3, do_vjcvt): Define. (insns): Add vjcvt. * testsuite/gas/aarch64/armv8_3-a-fp.s: New. * testsuite/gas/aarch64/armv8_3-a-fp.d: New. * testsuite/gas/aarch64/armv8_3-a-fp-bad.s: New. * testsuite/gas/aarch64/armv8_3-a-fp-bad.d: New. * testsuite/gas/aarch64/armv8_3-a-fp-bad.l: New. opcodes/ * arm-dis.c (coprocessor_opcodes): Add vjcvt.
2016-12-05[ARM] Add ARMv8.3 command line option and feature flagSzabolcs Nagy3-0/+7
ARMv8.3 is an architectural extension of ARMv8. Add the feature macro and -march=armv8.3-a gas command line option for the ARM target. https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions gas/ * config/tc-arm.c (arm_archs): Add "armv8.3-a". * doc/c-arm.texi (-march): Add "armv8.3-a". include/ * opcode/arm.h (ARM_EXT2_V8_3A, ARM_AEXT2_V8_3A): New. (ARM_ARCH_V8_3A): New.
2016-12-02[ARC] Sync cpu names with the ones accepted by GCC.Claudiu Zissulescu9-22/+237
gas/ 2016-12-02 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/cpu-em-err.s: New file. * testsuite/gas/arc/cpu-em4-err.s: Likewise. * testsuite/gas/arc/cpu-fpuda-err.s: Likewise. * testsuite/gas/arc/cpu-hs-err.s: Likewise. * testsuite/gas/arc/cpu-quarkse-err.s: Likewise. * testsuite/gas/arc/noargs_a7.s: Add .cpu. * config/tc-arc.c (ARC_CPU_TYPE_A6xx): Define. (ARC_CPU_TYPE_A7xx): Likewise. (ARC_CPU_TYPE_AV2EM): Likewise. (ARC_CPU_TYPE_AV2HS): Likewise. (cpu_types): Update list of known CPU names. (arc_show_cpu_list): New function. (md_show_usage): Print accepted CPU names. (cl_features): New variable. (arc_select_cpu): Use cl_features. (arc_option): Allow various .cpu names. (md_parse_option): Set cl_features. * doc/c-arc.texi: Update -mcpu and .cpu documentation.
2016-12-02Add support for Fushia OS.Josh Conner2-0/+7
* configure.ac: Add fuchsia to targets that use ELF. * configure: Regenerated. bfd * configure.tgt: Add support for fuchsia (OS). gas * configure.tgt: Add support for fuchsia (OS). ld * Makefile.am: Add dependency information for earmelf_fuchsia.c. * Makefile.in: Regenerate. * configure.tgt: Add support for aarch64-*-fuchsia, arm*-*-fuchsia*, and x86_64-*-fuchsia* targets. * emulparams/armelf_fuchsia.sh: New file. * emulparams/armelfb_fuchsia.sh: New file.
2016-12-01Fix seg fault attempting to unget an EOF character.Nick Clifton2-1/+4
PR gas/20898 * app.c (do_scrub_chars): Do not attempt to unget EOF.
2016-12-01Fix seg-fault printing assembler statistics when the output file was not ↵Nick Clifton2-0/+8
created. PR gas/20897 * subsegs.c (subsegs_print_statistics): Do nothing if no output file was created.
2016-12-01Fix ICE in assembler when passed a corrupt input file.Nick Clifton2-1/+16
PR gas/20895 * symbols.c (resolve_symbol_value): Gracefully handle erroneous symbolic expressions.
2016-11-29[ARC] Add checking for LP_COUNT reg usage, improve error reporting.Claudiu Zissulescu4-16/+39
gas/ 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (find_opcode_match): New function argument errmsg. (assemble_tokens): Collect and report the eventual error message found during opcode matching process. * testsuite/gas/arc/lpcount-err.s: New file. * testsuite/gas/arc/add_s-err.s: Update error message. opcode/ 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (insert_ra_chk): New function. (insert_rb_chk): Likewise. (insert_rad): Update text error message. (insert_rcd): Likewise. (insert_rhv2): Likewise. (insert_r0): Likewise. (insert_r1): Likewise. (insert_r2): Likewise. (insert_r3): Likewise. (insert_sp): Likewise. (insert_gp): Likewise. (insert_pcl): Likewise. (insert_blink): Likewise. (insert_ilink1): Likewise. (insert_ilink2): Likewise. (insert_ras): Likewise. (insert_rbs): Likewise. (insert_rcs): Likewise. (insert_simm3s): Likewise. (insert_rrange): Likewise. (insert_fpel): Likewise. (insert_blinkel): Likewise. (insert_pcel): Likewise. (insert_nps_3bit_dst): Likewise. (insert_nps_3bit_dst_short): Likewise. (insert_nps_3bit_src2_short): Likewise. (insert_nps_bitop_size_2b): Likewise. (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise. (RA_CHK): Define. (RB): Adjust. (RB_CHK): Define. (RC): Adjust. * arc-dis.c (print_insn_arc): Add LOAD and STORE class. * arc-tbl.h (div, divu): All instructions are DIVREM class. Change first insn argument to check for LP_COUNT usage. (rem): Likewise. (ld, ldd): All instructions are LOAD class. Change first insn argument to check for LP_COUNT usage. (st, std): All instructions are STORE class. (mac, mpy, dmac, mul, dmpy): All instructions are MPY class. Change first insn argument to check for LP_COUNT usage. (mov): All instructions are MOVE class. Change first insn argument to check for LP_COUNT usage. include/ 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (insn_class_t): Add DIVREM, LOAD, MOVE, MPY, STORE instruction classes.
2016-11-28X86: Ignore REX_B bit for 32-bit XOP instructionsAmit Pawar4-0/+37
While decoding 32-bit XOP instructions, 64 bit registers names are printed. This patch fixes this by ignoring REX_B bit in 32-bit mode. opcodes/ PR binutils/20637 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP instructions. gas/ PR binutils/20637 * testsuite/gas/i386/xop32reg.d: New file. * testsuite/gas/i386/xop32reg.s: New file. * testsuite/gas/i386/i386.exp: Run new test.
2016-11-27Fix spelling in comments in .y files (binutils)Ambrogino Modigliani1-0/+4
* arparse.y: Fix spelling in comments.
2016-11-27Fix spelling in comments in .l files (gas)Ambrogino Modigliani2-1/+5
* config/bfin-lex.l: Fix spelling in comments.
2016-11-27Fix spelling in comments in Expect scripts (gas)Ambrogino Modigliani8-11/+21
* testsuite/gas/all/gas.exp: Fix spelling in comments. * testsuite/gas/cris/cris.exp: Fix spelling in comments. * testsuite/gas/hppa/basic/basic.exp: Fix spelling in comments. * testsuite/gas/hppa/parse/parse.exp: Fix spelling in comments. * testsuite/gas/hppa/reloc/reloc.exp: Fix spelling in comments. * testsuite/gas/sh/arch/arch.exp: Fix spelling in comments. * testsuite/gas/tic4x/tic4x.exp: Fix spelling in comments.
2016-11-27Fix spelling in comments in Assembler files (gas)Ambrogino Modigliani13-13/+28
* testsuite/gas/arm/local_function.d: Fix spelling in comments. * testsuite/gas/arm/req.s: Fix spelling in comments. * testsuite/gas/arm/vfp1.s: Fix spelling in comments. * testsuite/gas/arm/vfp1_t2.s: Fix spelling in comments. * testsuite/gas/arm/vfp1xD.s: Fix spelling in comments. * testsuite/gas/arm/vfp1xD_t2.s: Fix spelling in comments. * testsuite/gas/mcore/allinsn.s: Fix spelling in comments. * testsuite/gas/mips/24k-triple-stores-5.s: Fix spelling in comments. * testsuite/gas/mips/delay.d: Fix spelling in comments. * testsuite/gas/mips/nodelay.d: Fix spelling in comments. * testsuite/gas/mips/r5900-full.s: Fix spelling in comments. * testsuite/gas/mips/r5900.s: Fix spelling in comments.
2016-11-27Fix spelling in comments in C source files (gas)Ambrogino Modigliani45-87/+135
* as.h: Fix spelling in comments. * config/obj-ecoff.c: Fix spelling in comments. * config/obj-macho.c: Fix spelling in comments. * config/tc-aarch64.c: Fix spelling in comments. * config/tc-arc.c: Fix spelling in comments. * config/tc-arm.c: Fix spelling in comments. * config/tc-avr.c: Fix spelling in comments. * config/tc-cr16.c: Fix spelling in comments. * config/tc-epiphany.c: Fix spelling in comments. * config/tc-frv.c: Fix spelling in comments. * config/tc-hppa.c: Fix spelling in comments. * config/tc-hppa.h: Fix spelling in comments. * config/tc-i370.c: Fix spelling in comments. * config/tc-m68hc11.c: Fix spelling in comments. * config/tc-m68k.c: Fix spelling in comments. * config/tc-mcore.c: Fix spelling in comments. * config/tc-mep.c: Fix spelling in comments. * config/tc-metag.c: Fix spelling in comments. * config/tc-mips.c: Fix spelling in comments. * config/tc-mn10200.c: Fix spelling in comments. * config/tc-mn10300.c: Fix spelling in comments. * config/tc-nds32.c: Fix spelling in comments. * config/tc-nios2.c: Fix spelling in comments. * config/tc-ns32k.c: Fix spelling in comments. * config/tc-pdp11.c: Fix spelling in comments. * config/tc-ppc.c: Fix spelling in comments. * config/tc-riscv.c: Fix spelling in comments. * config/tc-rx.c: Fix spelling in comments. * config/tc-score.c: Fix spelling in comments. * config/tc-score7.c: Fix spelling in comments. * config/tc-sparc.c: Fix spelling in comments. * config/tc-tic54x.c: Fix spelling in comments. * config/tc-vax.c: Fix spelling in comments. * config/tc-xgate.h: Fix spelling in comments. * config/tc-xtensa.c: Fix spelling in comments. * config/tc-z80.c: Fix spelling in comments. * dwarf2dbg.c: Fix spelling in comments. * input-file.h: Fix spelling in comments. * itbl-ops.c: Fix spelling in comments. * read.c: Fix spelling in comments. * stabs.c: Fix spelling in comments. * symbols.c: Fix spelling in comments. * write.c: Fix spelling in comments. * testsuite/gas/all/itbl-test.c: Fix spelling in comments. * testsuite/gas/tic4x/opclasses.h: Fix spelling in comments.
2016-11-25gas: fix CBCOND diagnostics for invalid immediate operands.Jose E. Marchesi5-2/+20
This patch fixes two problems in the SPARC assembler: - The diagnostic message Error: Illegal operands: Immediate value in cbcond is out of range. is incorrectly issued for non-CBCOND instructions that feature a simm5 immediate field, such as MPMUL, MONTMUL, etc. - When an invalid immediate operand is used in a CBCOND instruction, two redundant error messages are issued to the user, the second due to a stale fixup (this happens since commit 85024cd8bcb93f4112470ecdbd6c10fc2aea724f). Some diagnostic tests for the CBCOND instructions are also included in the patch. Tested in both sparc64-linux-gnu and sparcv9-linux-gnu targets. gas/ChangeLog: 2016-11-25 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-sparc.c (sparc_ip): Avoid emitting a cbcond error messages for non-cbcond instructions. * testsuite/gas/sparc/cbcond-diag.s: New file. * testsuite/gas/sparc/cbcond-diag.l: Likewise. * testsuite/gas/sparc/sparc.exp (gas_64_check): Run cbcond-diag tests.
2016-11-23gas: run the hwcaps-bump tests with 64-bit sparc objects only.Jose E. Marchesi2-1/+6
gas/ChangeLog: 2016-11-23 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/sparc/sparc.exp (gas_64_check): Make sure the hwcaps-bump test is run with 64-bit objects.
2016-11-23RISCV/GAS Add missing break in md_apply_fix.Kuan-Lin Chen2-0/+5
gdb/ChangeLog: * config/tc-riscv.c: Add missing break.
2016-11-23Regen POTFILES.inAlan Modra2-0/+6
bfd/ * po/BLD-POTFILES.in: Regenerate. * po/SRC-POTFILES.in: Regenerate. gas/ * po/POTFILES.in: Regenerate.
2016-11-22Fix spelling mistakes in comments in configure scriptsAmbrogino Modigliani2-1/+5
All changes are limited to comments, and no run-time behavior is affected. bfd/ChangeLog: 2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com> * warning.m4: Fix spelling in comments. * configure.ac: Fix spelling in comments. * configure: Regenerate. binutils/ChangeLog: 2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com> * configure: Regenerate. gdb/ChangeLog: 2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com> * configure.ac: Fix spelling in comments. * configure: Regenerate. gas/ChangeLog: 2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com> * configure: Regenerate. gold/ChangeLog: 2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com> * configure: Regenerate. gprof/ChangeLog: 2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com> * configure: Regenerate. ld/ChangeLog: 2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com> * configure: Regenerate. opcodes/ChangeLog: 2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com> * configure: Regenerate.
2016-11-22gas,opcodes: fix hardware capabilities bumping in the sparc assembler.Jose E. Marchesi5-58/+80
When the assembler finds an instruction which is part of a higher opcode architecture it bumps the current opcode architecture. For example: $ echo "mwait" | as -bump {standard input}: Assembler messages: {standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait" However, when two instructions pertaining to the same opcode architecture but associated to different SPARC hardware capabilities are found in the input stream, and no GAS architecture is specified in the command line, the assembler bangs: $ echo "mwait; wr %g0,%g1,%mcdper" | as -bump {standard input}: Assembler messages: {standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait" {standard input}:1: Error: Hardware capability "sparc5" not enabled for "wr". ... and it should'nt, as WRMCDPER pertains to the same architecture level than MWAIT. This patch fixes this by extending the definition of sparc opcode architectures to contain a set of hardware capabilities and making the assembler to take these capabilities into account when updating the set of allowed hwcaps when an architecture bump is triggered by some instruction. This way, hwcaps associated to architecture levels are maintained in opcodes, while the assembler keeps the flexibiity of defining GAS architectures including additional hwcaps (like -Asparcfmaf or the v8plus* variants). A test covering this failure case is included. gas/ChangeLog: 2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-sparc.c: Move HWS_* and HWS2_* definitions to opcodes/sparc-opc.c. (sparc_arch): Clarify the new role of the hwcap_allowed and hwcap2_allowed fields. (sparc_arch_table): Remove HWS_* and HWS2_* instances from hwcap_allowed and hwcap2_allowed respectively. (md_parse_option): Include the opcode arch hwcaps when processing -A. (sparc_ip): Use the current opcode arch hwcaps to update hwcap_allowed, as well of the hwcaps of the instruction triggering the bump. * testsuite/gas/sparc/hwcaps-bump.s: New file. * testsuite/gas/sparc/hwcaps-bump.l: Likewise. * testsuite/gas/sparc/sparc.exp (gas_64_check): Run tests in hwcaps-bump. include/ChangeLog: 2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/sparc.h (sparc_opcode_arch): New fields hwcaps and hwcaps2. opcodes/ChangeLog: 2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com> * sparc-opc.c (HWS_V8): Definition moved from gas/config/tc-sparc.c. (HWS_V9): Likewise. (HWS_VA): Likewise. (HWS_VB): Likewise. (HWS_VC): Likewise. (HWS_VD): Likewise. (HWS_VE): Likewise. (HWS_VV): Likewise. (HWS_VM): Likewise. (HWS2_VM): Likewise. (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of existing entries.
2016-11-22[ARC] Fix printing 'b' mnemonics.Claudiu Zissulescu2-2/+6
gas/ 2016-11-22 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/b.d: Update test result. opcode/ 2016-11-22 Claudiu Zissulescu <claziss@synopsys.com> * arc-tbl.h: Reorder conditional flags with delay flags for 'b' instructions.
2016-11-22PR20744, Incorrect PowerPC VLE relocsAlan Modra3-91/+82
VLE 16A and 16D relocs were functionally swapped. PR 20744 include/ * opcode/ppc.h: Define VLE insns using 16A and 16D relocs. bfd/ * elf32-ppc.h (struct ppc_elf_params): Add vle_reloc_fixup field. * elf32-ppc.c: Include opcode/ppc.h. (ppc_elf_howto_raw): Correct dst_mask for R_PPC_VLE_LO16A, R_PPC_VLE_LO16D, R_PPC_VLE_HI16A, R_PPC_VLE_HI16D, R_PPC_VLE_HA16A, R_PPC_VLE_HA16D, R_PPC_VLE_SDAREL_LO16A, R_PPC_VLE_SDAREL_LO16D, R_PPC_VLE_SDAREL_HI16A, R_PPC_VLE_SDAREL_HI16D, R_PPC_VLE_SDAREL_HA16A, and R_PPC_VLE_SDAREL_HA16D relocs. (ppc_elf_link_hash_table_create): Update default_params init. (ppc_elf_vle_split16): Correct shift and mask. Add params. Report or fix insn/reloc mismatches. (ppc_elf_relocate_section): Pass input_section, offset and fixup to ppc_elf_vle_split16. binutils/ * NEWS: Mention PowerPC VLE relocation error. gas/ * config/tc-ppc.c: Delete VLE insn defines. (md_assemble): Swap use_a_reloc and use_d_reloc. * testsuite/gas/ppc/vle-reloc.d: Update. ld/ * emultempl/ppc32elf.em (params): Update initializer. Handle --vle-reloc-fixup command line arg.
2016-11-21[GAS][ARM][PR20827]Fix gas error for two register form instruction (pre-UAL ↵Renlin Li4-2/+29
syntax). gas/ 2016-11-21 Renlin Li <renlin.li@arm.com> PR gas/20827 * config/tc-arm.c (encode_arm_shift): Don't assert for operands not presented. * testsuite/gas/arm/add-shift-two.d: New. * testsuite/gas/arm/add-shift-two.s: New.
2016-11-21Use ACX_PROG_CMP_IGNORE_INITIAL in gasAlan Modra6-26/+56
* configure.ac: Invoke ACX_PROG_CMP_IGNORE_INITIAL. * Makefile.am (comparison): Rewrite using do_compare. * configure: Regenerate. * Makefile.in: Regenerate. * doc/Makefile.in: Regenerate.
2016-11-18[ARC] Fix and extend features of .cpu directive.Claudiu Zissulescu8-18/+119
gas/ 2016-11-18 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/cl-warn.s: New file. * testsuite/gas/arc/cpu-pseudop-1.d: Likewise. * testsuite/gas/arc/cpu-pseudop-1.s: Likewise. * testsuite/gas/arc/cpu-pseudop-2.d: Likewise. * testsuite/gas/arc/cpu-pseudop-2.s: Likewise. * testsuite/gas/arc/cpu-warn2.s: Likewise. * config/tc-arc.c (selected_cpu): Initialize. (feature_type): New struct. (feature_list): New variable. (arc_check_feature): New function. (arc_select_cpu): Check for .cpu duplicates. Don't overwrite the current cpu features. Check if a feature is available for a given cpu. (md_parse_option): Test if features are available for a given cpu.
2016-11-18[AArch64] Add ARMv8.3 FCMLA and FCADD instructionsSzabolcs Nagy7-0/+125
Add support for FCMLA and FCADD complex arithmetic SIMD instructions. FCMLA has an indexed element variant where the index range has to be treated specially because a complex number takes two elements and the indexed vector size depends on the other operands. These complex number SIMD instructions are part of ARMv8.3 https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions include/ 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_IMM_ROT1, AARCH64_OPND_IMM_ROT2, AARCH64_OPND_IMM_ROT3. (enum aarch64_op): Add OP_FCMLA_ELEM. opcodes/ 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define. (aarch64_feature_simd_v8_3, SIMD_V8_3): Define. (aarch64_opcode_table): Add fcmla and fcadd. (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}. * aarch64-asm.h (aarch64_ins_imm_rotate): Declare. * aarch64-asm.c (aarch64_ins_imm_rotate): Define. * aarch64-dis.h (aarch64_ext_imm_rotate): Declare. * aarch64-dis.c (aarch64_ext_imm_rotate): Define. * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}. * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}. (operand_general_constraint_met_p): Rotate and index range check. (aarch64_print_operand): Handle rotate operand. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. gas/ 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> * config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_IMM_ROT*. * testsuite/gas/aarch64/advsimd-armv8_3.d: New. * testsuite/gas/aarch64/advsimd-armv8_3.s: New. * testsuite/gas/aarch64/illegal-fcmla.s: New. * testsuite/gas/aarch64/illegal-fcmla.l: New. * testsuite/gas/aarch64/illegal-fcmla.d: New.
2016-11-18[AArch64] Add ARMv8.3 weaker release consistency load instructionsSzabolcs Nagy6-0/+93
Add support for ARMv8.3 LDAPRB, LDAPRH and LDAPR weak release consistency load instructions. (They are equivalent to LDARB, LDARH and LDAR instructions other than the weaker memory ordering requirement.) For more details about weak release consistency see https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions opcodes/ 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. gas/ 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> * testsuite/gas/aarch64/ldst-exclusive-armv8_3.s: Add ldaprb, ldaprh, ldapr tests. * testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Likewise. * testsuite/gas/aarch64/illegal-ldapr.s: Likewise. * testsuite/gas/aarch64/illegal-ldapr.d: Likewise. * testsuite/gas/aarch64/illegal-ldapr.l: Likewise.
2016-11-18[AArch64] Add ARMv8.3 javascript floating-point conversion instructionSzabolcs Nagy9-0/+61
Add support for ARMv8.3 FJCVTZS floating-point conversion instruction. For details about javascript floating-point conversion see https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions opcodes/ 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs. (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. gas/ 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> * testsuite/gas/aarch64/fp-armv8_3.s: Add fjcvtzs test. * testsuite/gas/aarch64/fp-armv8_3.d: Likewise. * testsuite/gas/aarch64/illegal-fjcvtzs.s: Likewise. * testsuite/gas/aarch64/illegal-fjcvtzs.d: Likewise. * testsuite/gas/aarch64/illegal-fjcvtzs.l: Likewise. * testsuite/gas/aarch64/illegal-nofp-armv8_3.s: Likewise. * testsuite/gas/aarch64/illegal-nofp-armv8_3.d: Likewise. * testsuite/gas/aarch64/illegal-nofp-armv8_3.l: Likewise.
2016-11-18[AArch64] Add ARMv8.3 combined pointer authentication load instructionsSzabolcs Nagy7-0/+158
Add support for ARMv8.3 LDRAA and LDRAB combined pointer authentication and load instructions. These instructions authenticate the base register and load 8 byte from it plus a scaled 10-bit offset with optional writeback to update the base register. A new instruction class (ldst_imm10) and operand type (AARCH64_OPND_ADDR_SIMM10) were introduced to handle the special addressing form. include/ 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM10. (enum aarch64_insn_class): Add ldst_imm10. opcodes/ 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> * aarch64-tbl.h (QL_X1NIL): New. (arch64_opcode_table): Add ldraa, ldrab. (AARCH64_OPERANDS): Add "ADDR_SIMM10". * aarch64-asm.h (aarch64_ins_addr_simm10): Declare. * aarch64-asm.c (aarch64_ins_addr_simm10): Define. * aarch64-dis.h (aarch64_ext_addr_simm10): Declare. * aarch64-dis.c (aarch64_ext_addr_simm10): Define. * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10. * aarch64-opc.c (fields): Add data for FLD_S_simm10. (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10. (aarch64_print_operand): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. gas/ 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> * config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_ADDR_SIMM10. (fix_insn): Likewise. (warn_unpredictable_ldst): Handle ldst_imm10. * testsuite/gas/aarch64/pac.s: Add ldraa and ldrab tests. * testsuite/gas/aarch64/pac.d: Likewise. * testsuite/gas/aarch64/illegal-ldraa.s: New. * testsuite/gas/aarch64/illegal-ldraa.l: New. * testsuite/gas/aarch64/illegal-ldraa.d: New.
2016-11-15Fix SPARC relocations generated for the .eh_frame section.Nick Clifton2-1/+10
PR gas/20803 * config/tc-sparc.c (cons_fix_new_sparc): Use unaligned relocs in the .eh_frame section.
2016-11-13add missing ChangeLog entryAnthony Green1-0/+4
2016-11-13Assemble 'bad' moxie instructionAnthony Green1-0/+7
2016-11-11Accept L and LL suffixes to integer constants.Nick Clifton5-0/+35
PR gas/20732 * expr.c (integer_constant): If tc_allow_L_suffix is defined and non-zero then accept a L or LL suffix. * testsuite/gas/sparc/pr20732.d: New test source file. * testsuite/gas/sparc/pr20732.d: New test output file. * testsuite/gas/sparc/sparc.exp: Run new test.
2016-11-11[AArch64] Add ARMv8.3 combined pointer authentication branch instructionsSzabolcs Nagy3-0/+40
Add support for ARMv8.3 pointer authentication instructions that are encoded as unconditional branch instructions. opcodes/ 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com> * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz, brabz, blraaz, blrabz, retaa, retab, eretaa, eretab. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. gas/ 2016-11-08 Szabolcs Nagy <szabolcs.nagy@arm.com> * testsuite/gas/aarch64/pac.s: Add ARMv8.3 branch instruction tests. * testsuite/gas/aarch64/pac.d: Likewise.
2016-11-11[AArch64] Add ARMv8.3 PACGA instructionSzabolcs Nagy4-0/+14
Add support for the ARMv8.3 PACGA instruction. include/ 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com> * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rm_SP. opcodes/ 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com> * aarch64-tbl.h (arch64_opcode_table): Add pacga. (AARCH64_OPERANDS): Add Rm_SP. * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. gas/ 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com> * config/tc-aarch64.c (process_omitted_operand): Handle AARCH64_OPND_Rm_SP. (parse_operands): Likewise. * testsuite/gas/aarch64/pac.s: Add pacga. * testsuite/gas/aarch64/pac.d: Add pacga.
2016-11-11[AArch64] Add ARMv8.3 single source PAC instructionsSzabolcs Nagy3-0/+73
Add support for ARMv8.3 pointer authentication instructions that are encoded as single source data processing instructions. opcodes/ 2016-11-08 Szabolcs Nagy <szabolcs.nagy@arm.com> * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia, autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza, autdzb, xpaci, xpacd. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. gas/testsuite/ 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com> * testsuite/gas/aarch64/pac.s: New. * testsuite/gas/aarch64/pac.d: New.
2016-11-11[AArch64] Add ARMv8.3 pointer authentication key registersSzabolcs Nagy5-0/+80
Add support for system registers introduced in ARMv8.3 for pointer authentication. opcodes/ 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com> * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1, apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1, apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1. (aarch64_sys_reg_supported_p): Add feature test for new registers. gas/ 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com> * testsuite/gas/aarch64/sysreg-3.s: New. * testsuite/gas/aarch64/sysreg-3.d: New. * testsuite/gas/aarch64/illegal-sysreg-3.l: New. * testsuite/gas/aarch64/illegal-sysreg-3.d: New.
2016-11-11[AArch64] Add ARMv8.3 instructions which are in the NOP spaceSzabolcs Nagy4-13/+94
This patch adds support for a subset of the ARMv8.3 pointer authentication instructions: XPACLRI, PACIA1716, PACIB1716, AUTIA1716, AUTIA1716, PACIAZ, PACIASP, PACIBZ, PACISP, AUTIAZ, AUTIASP, AUTIBZ, AUTIBSP. These are aliases to HINT #0x7, HINT #0x8, HINT #0xa, HINT #0xc, HINT #0xe, HINT #0x18, HINT #0x19, ..., HINT #0x1f respectively. For more details about pointer authentication in ARMv8.3 see https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions opcodes/ 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com> * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New. (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716, autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz, autibsp. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. gas/ 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com> * testsuite/gas/aarch64/system-3.s: New. * testsuite/gas/aarch64/system-3.d: New. * testsuite/gas/aarch64/system.d: Update expected output.
2016-11-11[AArch64] Add ARMv8.3 command line option and feature flagSzabolcs Nagy3-1/+7
ARMv8.3 can be selected with -march=armv8.3-a command line option. An overview of the ARMv8.3 architecture extension is at https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions gas/ 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com> * config/tc-aarch64.c (aarch64_archs): Add "armv8.3-a". * doc/c-aarch64.texi (-march): Likewise. include/ 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_V8_3): Define. (AARCH64_ARCH_V8_3): Define. (AARCH64_ARCH_V8_1, AARCH64_ARCH_V8_2): Simplify.
2016-11-11[AArch64] Fix feature dependencies for +simd and +cryptoSzabolcs Nagy7-2/+48
According to the gas manual, +simd implies +fp and +crypto implies +simd. Make sure +nofp turns +simd, +crypto and +fp16 off. gas/ 2016-11-07 Szabolcs Nagy <szabolcs.nagy@arm.com> * config/tc-aarch64.c (aarch64_features): Fix "simd" and "crypto". * testsuite/gas/aarch64/illegal-crypto-nofp.d: New. * testsuite/gas/aarch64/illegal-crypto-nofp.l: New. * testsuite/gas/aarch64/illegal-fp16-nofp.d: New. * testsuite/gas/aarch64/illegal-fp16-nofp.l: New. * testsuite/gas/aarch64/illegal-fp16-nofp.s: New.
2016-11-09X86: Remove the .s suffix from EVEX vpextrwH.J. Lu8-72/+17
The .s suffix indicates that the instruction is encoded by swapping 2 register operands. Since vpextrw takes an XMM register and an integer register, the .s suffix should be ignored for EVEX vpextrw. gas/ PR binutils/20799 * testsuite/gas/i386/opcode.s: Add a test for EVEX vpextrw. * testsuite/gas/i386/opcode-intel.d: Updated. * testsuite/gas/i386/opcode-suffix.d: Likewise. * testsuite/gas/i386/opcode.d: Likewise. * testsuite/gas/i386/x86-64-avx512bw-opts.s: Remove vpextrw tests. * testsuite/gas/i386/x86-64-avx512bw-opts-intel.d: Updated. * testsuite/gas/i386/x86-64-avx512bw-opts.d: Likewise. opcodes/ PR binutils/20799 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw. * i386-dis.c (EdqwS): Removed. (dqw_swap_mode): Likewise. (intel_operand_size): Don't check dqw_swap_mode. (OP_E_register): Likewise. (OP_E_memory): Likewise. (OP_G): Likewise. (OP_EX): Likewise. * i386-opc.tbl: Remove "S" from EVEX vpextrw. * i386-tbl.h: Regerated.
2016-11-09X86: Update opcode-suffix.dH.J. Lu2-0/+13
PR binutils/20754 * testsuite/gas/i386/opcode-suffix.d: Updated.
2016-11-07X86: Properly handle bad FPU opcodeH.J. Lu4-0/+23
Since Bad_Opcode and FGRPd9_2 were the same in i386-dis.c, all Bad_Opcode entries in float_reg were displaced as FGRPd9_2. This patch adds an entry for Bad_Opcode in fgrps to avoid treating it as FGRPd9_2. gas/ PR binutils/20775 * testsuite/gas/i386/i386.exp: Run fpu-bad. * testsuite/gas/i386/fpu-bad.d: New file. * testsuite/gas/i386/fpu-bad.s: Likewise. opcodes/ PR binutils/20775 * i386-dis.c (FGRPd9_2): Replace 0 with 1. (FGRPd9_4): Replace 1 with 2. (FGRPd9_5): Replace 2 with 3. (FGRPd9_6): Replace 3 with 4. (FGRPd9_7): Replace 4 with 5. (FGRPda_5): Replace 5 with 6. (FGRPdb_4): Replace 6 with 7. (FGRPde_3): Replace 7 with 8. (FGRPdf_4): Replace 8 with 9. (fgrps): Add an entry for Bad_Opcode.
2016-11-04Fix gas crash with unreasonably long linesNathan Sidwell2-43/+59
gas/ * input-scrub.c (partial_size): Make size_t. (buffer_length): Likewise. Adjust meaning. (struct input_save): Adjust partial_size type. (input_scrub_reinit): New. (input_scrub_push, input_scrub_begin): Use it. (input_scrub_next_buffer): Fix buffer extension logic. Only scan newly read buffer for newline.
2016-11-04arc/nps400: Validate address type operands correctlyAndrew Burgess4-3/+69
When we match against an address type operand within an instruction it is important that we match exactly the right address type operand early on, during the opcode selection phase. If we wait until the operand insertion phase to check that we have the correct address operand, then it is too late to select an alternative opcode. This becomes important only when we have multiple opcodes with the same mnemonic, and operand lists that differ only in the type of the address operands. This commit fixes this issue, and adds some example instructions that require this issue to be fixed (the instructions are identical except for the address type operand). gas/ChangeLog: * config/tc-arc.c (find_opcode_match): Use insert function to validate matching address type operands. * testsuite/gas/arc/nps400-10.d: New file. * testsuite/gas/arc/nps400-10.s: New file. opcodes/ChangeLog: * arc-opc.c (arc_flag_operands): Add F_DI14. (arc_flag_classes): Add C_DI14. * arc-nps400-tbl.h: Add new exc instructions.
2016-11-04S/390: Fix 16 bit pc relative relocs.Andreas Krebbel3-7/+33
Since the bpp instruction has been added the 16 bit wide pc relative relocs might occur at offset 2 as well at offset 4 in an instruction. With this patch the different adjustment is passed from md_gather_operand to md_apply_fix via fx_pcrel_adjust field in the fix data structure. No regressions on s390x. gas/ChangeLog: 2016-11-04 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/tc-s390.c (md_gather_operands): Set fx_pcrel_adjust. (md_apply_fix): Use/Set fx_pcrel_adjust. * testsuite/gas/s390/zarch-zEC12.d: Add bpp reloc test pattern. * testsuite/gas/s390/zarch-zEC12.s: Add bpp reloc test.
generated by cgit v1.1 at 2024-12-23 13:09:59 +0000