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2023-03-30aarch64: Add new SVE dot-product instructionsRichard Sandiford9-12/+186
2023-03-30aarch64: Add the SVE BFMLSL instructionsRichard Sandiford7-0/+143
2023-03-30aarch64: Add the SME2 UZP and ZIP instructionsRichard Sandiford7-0/+352
2023-03-30aarch64: Add the SME2 UNPK instructionsRichard Sandiford7-0/+188
2023-03-30aarch64: Add the SME2 shift instructionsRichard Sandiford15-3/+384
2023-03-30aarch64: Add the SME2 saturating conversion instructionsRichard Sandiford14-0/+328
2023-03-30aarch64: Add the SME2 FP<->FP conversion instructionsRichard Sandiford7-0/+102
2023-03-30aarch64: Add the SME2 FP<->int conversion instructionsRichard Sandiford7-0/+245
2023-03-30aarch64: Add the SME2 CLAMP instructionsRichard Sandiford7-0/+407
2023-03-30aarch64: Add the SME2 MOPA and MOPS instructionsRichard Sandiford7-0/+177
2023-03-30aarch64: Add the SME2 vertical dot-product instructionsRichard Sandiford28-0/+556
2023-03-30aarch64: Add the SME2 dot-product instructionsRichard Sandiford28-0/+2355
2023-03-30aarch64: Add the SME2 MLALL and MLSLL instructionsRichard Sandiford22-0/+2317
2023-03-30aarch64: Add the SME2 MLAL and MLSL instructionsRichard Sandiford8-0/+2084
2023-03-30aarch64: Add the SME2 FMLA and FMLS instructionsRichard Sandiford15-0/+1129
2023-03-30aarch64: Add the SME2 maximum/minimum instructionsRichard Sandiford8-6/+2218
2023-03-30aarch64: Add the SME2 ADD and SUB instructionsRichard Sandiford22-1/+1424
2023-03-30aarch64: Add the SME2 ZT0 instructionsRichard Sandiford11-12/+746
2023-03-30aarch64: Add the SME2 predicate-related instructionsRichard Sandiford26-24/+2680
2023-03-30aarch64: Add the SME2 multivector LD1 and ST1 instructionsRichard Sandiford29-0/+6804
2023-03-30aarch64: Add the SME2 MOVA instructionsRichard Sandiford10-2/+1598
2023-03-30aarch64: Add support for predicate-as-counter registersRichard Sandiford15-3/+331
2023-03-30aarch64; Add support for vector offset rangesRichard Sandiford11-0/+84
2023-03-30aarch64: Add support for vgx2 and vgx4Richard Sandiford13-1/+119
2023-03-30aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_arrayRichard Sandiford1-1/+1
2023-03-30aarch64: Add +sme2Richard Sandiford3-0/+6
2023-03-30aarch64: Prefer register ranges & support wrappingRichard Sandiford11-982/+1038
2023-03-30aarch64: Add support for strided register listsRichard Sandiford4-27/+53
2023-03-30aarch64: Rename some of GAS's REG_TYPE_* macrosRichard Sandiford1-71/+71
2023-03-30aarch64: Add a aarch64_cpu_supports_inst_p helperRichard Sandiford1-2/+1
2023-03-30aarch64: Tweak priorities of parsing-related errorsRichard Sandiford2-11/+51
2023-03-30aarch64: Try to report invalid variants against the closest matchRichard Sandiford4-93/+101
2023-03-30aarch64: Tweak register list errorsRichard Sandiford4-20/+18
2023-03-30aarch64: Make AARCH64_OPDE_REG_LIST take a bitfieldRichard Sandiford1-20/+34
2023-03-30aarch64: Add an operand class for SVE register listsRichard Sandiford1-13/+13
2023-03-30aarch64: Add an error code for out-of-range registersRichard Sandiford1-0/+8
2023-03-30aarch64: Deprioritise AARCH64_OPDE_REG_LISTRichard Sandiford1-3/+3
2023-03-30aarch64: Update operand_mismatch_kind_namesRichard Sandiford1-0/+2
2023-03-30aarch64: Rework reporting of failed register checksRichard Sandiford23-972/+1202
2023-03-30aarch64: Try to avoid inappropriate default errorsRichard Sandiford6-5/+26
2023-03-30aarch64: Improve errors for malformed register listsRichard Sandiford6-21/+41
2023-03-30aarch64: Tweak parsing of integer & FP registersRichard Sandiford1-29/+42
2023-03-30aarch64: Tweak errors for base & offset registersRichard Sandiford9-293/+308
2023-03-30aarch64: Tweak error for missing immediate offsetRichard Sandiford5-18/+18
2023-03-30aarch64: Move w12-w15 range check to libopcodesRichard Sandiford7-26/+31
2023-03-30aarch64: Commonise index parsingRichard Sandiford1-21/+21
2023-03-30aarch64: Consolidate ZA slice parsingRichard Sandiford5-72/+55
2023-03-30aarch64: Move ZA range checks to aarch64-opc.cRichard Sandiford8-140/+77
2023-03-30aarch64: Pass aarch64_indexed_za to parsersRichard Sandiford1-152/+78
2023-03-30aarch64: Rename za_tile_vector to za_indexRichard Sandiford1-9/+9