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2023-04-28x86/Intel: reduce ELF/PE conditional scope in x86_cons()Jan Beulich1-6/+4
2023-04-28gas: move shift count checkJan Beulich1-14/+14
2023-04-28x86: rework AMX multiplication insn disassemblyJan Beulich1-1/+1
2023-04-27gas: bpf: fix tests for pseudo-c syntaxJose E. Marchesi36-392/+489
2023-04-26 RISC-V: Support XVentanaCondOps extensionPhilipp Tomsich3-0/+22
2023-04-26gas: documentation for the BPF pseudo-c asm syntaxJose E. Marchesi2-6/+201
2023-04-26gas: BPF pseudo-c syntax testsGuillermo E. Martinez31-5/+880
2023-04-26gas: support for the BPF pseudo-c assembly syntaxGuillermo E. Martinez3-4/+1551
2023-04-26Avoid another -Werror=dangling-pointerAlan Modra1-2/+3
2023-04-25RISC-V: adjust logic to avoid register name symbolsJan Beulich2-27/+98
2023-04-25RISC-V: test for expected / no unexpected symbolsJan Beulich3-0/+22
2023-04-25RISC-V: don't recognize bogus relocationsJan Beulich1-2/+1
2023-04-25RISC-V: avoid redundant and misleading/wrong error messagesJan Beulich2-1/+9
2023-04-25RISC-V: drop "percent_op" parameter from my_getOpcodeExpression()Jan Beulich1-4/+4
2023-04-25RISC-V: minor effort reduction in relocation specifier parsingJan Beulich1-16/+16
2023-04-23MIPS: fix loongson3 llsc workaroundYunQiang Su1-7/+3
2023-04-23MIPS: default output r6 obj if the triple is r6YunQiang Su2-0/+18
2023-04-23MIPS: support mips*64 as CPU and gnuabi64 as ABIYunQiang Su2-2/+8
2023-04-23LoongArch: Fix loongarch32 test failsmengqinggang1-7/+7
2023-04-20x86: adjust an ILP32 testcase using .insnJan Beulich1-1/+1
2023-04-19gas: sframe: fix commentIndu Bhagat1-1/+1
2023-04-19gas: sframe: use ATTRIBUTE_UNUSED consistentlyIndu Bhagat1-3/+3
2023-04-19gas: document that get_symbol_name() can clobber the input bufferJan Beulich1-5/+10
2023-04-19x86: parse_register() must not alter the parsed stringJan Beulich1-13/+9
2023-04-19x86: parse_real_register() does not alter the parsed stringJan Beulich1-4/+4
2023-04-18Symbols with GOT relocatios do not fix adjustbalemengqinggang4-69/+91
2023-04-18Assembler Internal Docs: Describe handling of opcodes for relaxation a bit be...Thomas Koenig2-3/+10
2023-04-13arc: Update ARC's CFI tests.Claudiu Zissulescu3-11/+16
2023-04-13arc: Update GAS testClaudiu Zissulescu3-8/+5
2023-04-12Fail of x86_64 AMX-COMPLEX insns (Intel disassembly)Alan Modra1-0/+1
2023-04-12Comment typo fixAlan Modra1-1/+1
2023-04-10x86: Add inval tests for AMX instructionsHaochen Jiang7-8/+60
2023-04-07Support Intel AMX-COMPLEXHaochen Jiang11-1/+104
2023-04-06gas/write.c use better typesAlan Modra1-3/+3
2023-04-03opcodes/arm: adjust whitespace in cpsie instructionAndrew Burgess2-4/+4
2023-04-03ubsan: aarch64 parse_vector_reg_listAlan Modra1-4/+4
2023-03-31RISC-V: Allocate "various" operand typeTsukasa OI1-17/+47
2023-03-31x86: convert testcases to use .insnJan Beulich39-523/+346
2023-03-31x86: document .insnJan Beulich2-0/+133
2023-03-31x86: handle immediate operands for .insnJan Beulich6-4/+182
2023-03-31x86: allow for multiple immediates in output_disp()Jan Beulich1-5/+5
2023-03-31x86: handle EVEX Disp8 for .insnJan Beulich5-1/+149
2023-03-31x86: process instruction operands for .insnJan Beulich6-21/+432
2023-03-31x86: parse special opcode modifiers for .insnJan Beulich1-1/+38
2023-03-31x86: parse VEX and alike specifiers for .insnJan Beulich5-6/+250
2023-03-31x86: introduce .insn directiveJan Beulich6-10/+213
2023-03-30aarch64: Add the RPRFM instructionRichard Sandiford7-1/+186
2023-03-30aarch64: Add the SVE FCLAMP instructionRichard Sandiford8-1/+102
2023-03-30aarch64: Add new SVE shift instructionsRichard Sandiford7-0/+97
2023-03-30aarch64: Add new SVE saturating conversion instructionsRichard Sandiford7-0/+93
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