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2018-02-13gas: xtensa: fix trampoline placementMax Filippov2-0/+11
For jumps requiring multiple trampolines trampoline placement code may place multiple sequential trampolines into the same frag. Don't do that. gas/ 2018-02-13 Max Filippov <jcmvbkbc@gmail.com> * config/tc-xtensa.c (xg_find_best_trampoline): Skip trampoline frag that contains source address.
2018-02-13Fix ARm assembler so that it rejects invalid immediate values for the Thumb ↵Nick Clifton5-3/+28
ORR instruction. PR 22773 * config/tc-arm.c (md_apply_fix): Test Rn field of Thumb ORR instruction before assuming that it is a MOV instruction. * testsuite/gas/arm/pr22773.s: New test. * testsuite/gas/arm/pr22773.d: New test driver. * testsuite/gas/arm/pr22773.l: New expected output.
2018-02-13x86-64: Generate branch with PLT32 relocationH.J. Lu10-23/+85
Since there is no need to prepare for PLT branch on x86-64, generate R_X86_64_PLT32, instead of R_X86_64_PC32, if possible, which can be used as a marker for 32-bit PC-relative branches. To compile Linux kernel, this patch: From: "H.J. Lu" <hjl.tools@gmail.com> Subject: [PATCH] x86: Treat R_X86_64_PLT32 as R_X86_64_PC32 On i386, there are 2 types of PLTs, PIC and non-PIC. PIE and shared objects must use PIC PLT. To use PIC PLT, you need to load _GLOBAL_OFFSET_TABLE_ into EBX first. There is no need for that on x86-64 since x86-64 uses PC-relative PLT. On x86-64, for 32-bit PC-relative branches, we can generate PLT32 relocation, instead of PC32 relocation, which can also be used as a marker for 32-bit PC-relative branches. Linker can always reduce PLT32 relocation to PC32 if function is defined locally. Local functions should use PC32 relocation. As far as Linux kernel is concerned, R_X86_64_PLT32 can be treated the same as R_X86_64_PC32 since Linux kernel doesn't use PLT. is needed. It is available on hjl/plt32/master branch at https://github.com/hjl-tools/linux bfd/ PR gas/22791 * elf64-x86-64.c (is_32bit_relative_branch): Removed. (elf_x86_64_relocate_section): Check PIC relocations in PIE. Remove is_32bit_relative_branch usage. Disallow PC32 reloc against protected function in shared object. gas/ PR gas/22791 * config/tc-i386.c (need_plt32_p): New function. (output_jump): Generate BFD_RELOC_X86_64_PLT32 if possible. (md_estimate_size_before_relax): Likewise. * testsuite/gas/i386/reloc64.d: Updated. * testsuite/gas/i386/x86-64-jump.d: Likewise. * testsuite/gas/i386/x86-64-mpx-branch-1.d: Likewise. * testsuite/gas/i386/x86-64-mpx-branch-2.d: Likewise. * testsuite/gas/i386/x86-64-relax-2.d: Likewise. * testsuite/gas/i386/x86-64-relax-3.d: Likewise. * testsuite/gas/i386/ilp32/reloc64.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise. ld/ PR gas/22791 * testsuite/ld-x86-64/mpx1c.rd: Updated. * testsuite/ld-x86-64/pr22791-1.err: New file. * testsuite/ld-x86-64/pr22791-1a.c: Likewise. * testsuite/ld-x86-64/pr22791-1b.s: Likewise. * testsuite/ld-x86-64/pr22791-2.rd: Likewise. * testsuite/ld-x86-64/pr22791-2a.s: Likewise. * testsuite/ld-x86-64/pr22791-2b.c: Likewise. * testsuite/ld-x86-64/pr22791-2c.s: Likewise. * testsuite/ld-x86-64/x86-64.exp: Run PR ld/22791 tests.
2018-02-13Fix compile time warning messages from gcc version 8 about cast between ↵Nick Clifton9-16/+75
incompatible function types. PR 22823 bfd Fix compile time warnings generated by gcc version 8. * libbfd-in.h: Remove extraneous text from prototypes. Add prototypes for bfd_false_any, bfd_true_any, bfd_nullvoidptr_any, bfd_0_any, bfd_0u_any, bfd_0l_any, bfd_n1_any, bfd_void_any. (_bfd_generic_bfd_copy_private_bfd_data): Use vararg based dummy function. (_bfd_generic_bfd_merge_private_bfd_data): Likewise. (_bfd_generic_bfd_set_private_flags): Likewise. (_bfd_generic_bfd_copy_private_section_data): Likewise. (_bfd_generic_bfd_copy_private_symbol_data): Likewise. (_bfd_generic_bfd_copy_private_header_data): Likewise. (_bfd_generic_bfd_print_private_bfd_data): Likewise. (_bfd_noarchive_construct_extended_name_table): Likewise. (_bfd_noarchive_truncate_arname): Likewise. (_bfd_noarchive_write_ar_hdr): Likewise. (_bfd_noarchive_get_elt_at_index): Likewise. (_bfd_nosymbols_canonicalize_symtab): Likewise. (_bfd_nosymbols_print_symbol): Likewise. (_bfd_nosymbols_get_symbol_info): Likewise. (_bfd_nosymbols_get_symbol_version_string): Likewise. (_bfd_nosymbols_bfd_is_local_label_name): Likewise. (_bfd_nosymbols_bfd_is_target_special_symbol): Likewise. (_bfd_nosymbols_get_lineno): Likewise. (_bfd_nosymbols_find_nearest_line): Likewise. (_bfd_nosymbols_find_line): Likewise. (_bfd_nosymbols_find_inliner_info): Likewise. (_bfd_nosymbols_bfd_make_debug_symbol): Likewise. (_bfd_nosymbols_read_minisymbols): Likewise. (_bfd_nosymbols_minisymbol_to_symbol): Likewise. (_bfd_norelocs_bfd_reloc_type_lookup): Likewise. (_bfd_norelocs_bfd_reloc_name_lookup): Likewise. (_bfd_nowrite_set_arch_mach): Likewise. (_bfd_nowrite_set_section_contents): Likewise. (_bfd_nolink_sizeof_headers): Likewise. (_bfd_nolink_bfd_get_relocated_section_contents): Likewise. (_bfd_nolink_bfd_relax_section): Likewise. (_bfd_nolink_bfd_gc_sections): Likewise. (_bfd_nolink_bfd_lookup_section_flags): Likewise. (_bfd_nolink_bfd_merge_sections): Likewise. (_bfd_nolink_bfd_is_group_section): Likewise. (_bfd_nolink_bfd_discard_group): Likewise. (_bfd_nolink_bfd_link_hash_table_create): Likewise. (_bfd_nolink_bfd_link_add_symbols): Likewise. (_bfd_nolink_bfd_link_just_syms): Likewise. (_bfd_nolink_bfd_copy_link_hash_symbol_type): Likewise. (_bfd_nolink_bfd_final_link): Likewise. (_bfd_nolink_bfd_link_split_section): Likewise. (_bfd_nolink_section_already_linked): Likewise. (_bfd_nolink_bfd_define_common_symbol): Likewise. (_bfd_nolink_bfd_define_start_stop): Likewise. (_bfd_nodynamic_canonicalize_dynamic_symtab): Likewise. (_bfd_nodynamic_get_synthetic_symtab): Likewise. (_bfd_nodynamic_get_dynamic_reloc_upper_bound _bfd_): Likewise. (_bfd_nodynamic_canonicalize_dynamic_reloc): Likewise. * libbfd.c (bfd_false_any): New function. Like bfd_false but accepts one or more arguments. (bfd_true_any): Likewise. (bfd_nullvoidptr_any): Likewise. (bfd_0_any): Likewise. (bfd_0u_any): Likewise. (bfd_0l_any): Likewise. (_bfd_n1_any): Likewise. (bfd_void_any): Likewise. * libbfd.h (extern): Regenerate * aout-target.h (MY_bfd_is_target_special_symbol): Use vararg based dummy function. * aout-tic30.c (tic30_aout_set_arch_mach): Likewise. * binary.c (binary_get_symbol_info): Likewise. * coff-alpha.c (alpha_ecoff_backend_data): Likewise. * coff-mips.c (mips_ecoff_backend_data): Likewise. * coffcode.h (coff_set_alignment_hook): Likewise. (symname_in_debug_hook): Likewise. (bfd_coff_backend_data bigobj_swap_table): Likewise. * elf-m10300.c (elf_backend_omit_section_dynsym): Likewise. * elf32-cr16.c (elf_backend_omit_section_dynsym): Likewise. * elf32-lm32.c (elf_backend_omit_section_dynsym): Likewise. * elf32-m32r.c (elf_backend_omit_section_dynsym): Likewise. * elf32-metag.c (elf_backend_omit_section_dynsym): Likewise. * elf32-score.c (elf_backend_omit_section_dynsym): Likewise. * elf32-score7.c (elf_backend_omit_section_dynsym): Likewise. * elf32-xstormy16.c (elf_backend_omit_section_dynsym): Likewise. * elf32-xtensa.c (elf_backend_omit_section_dynsym): Likewise. * elf64-alpha.c (elf_backend_omit_section_dynsym): Likewise. * elf64-hppa.c (elf_backend_omit_section_dynsym): Likewise. * elf64-ia64-vms.c (elf_backend_omit_section_dynsym): Likewise. * elf64-mmix.c (elf_backend_omit_section_dynsym): Likewise. * elf64-sh64.c (elf_backend_omit_section_dynsym): Likewise. * elfnn-ia64.c (elf_backend_omit_section_dynsym): Likewise. * elfxx-target.h (bfd_elfNN_bfd_debug_info_accumulate): Likewise. (bfd_elfNN_bfd_make_debug_symbol): Likewise. (bfd_elfNN_bfd_merge_private_bfd_data): Likewise. (bfd_elfNN_bfd_set_private_flags): Likewise. (bfd_elfNN_bfd_is_target_special_symbol): Likewise. (elf_backend_init_index_section): Likewise. (elf_backend_allow_non_load_phdr): Likewise. * elfxx-x86.h (elf_backend_omit_section_dynsym): Likewise. * i386msdos.c (msdos_bfd_is_target_special_symbol): Likewise. * ieee.c (ieee_construct_extended_name_table): Likewise. (ieee_write_armap): Likewise. (ieee_write_ar_hdr): Likewise. (ieee_bfd_is_target_special_symbol): Likewise. * ihex.c (ihex_canonicalize_symtab): Likewise. (ihex_bfd_is_target_special_symbol): Likewise. * libaout.h (aout_32_bfd_is_target_special_symbol): Likewise. * libecoff.h (_bfd_ecoff_bfd_is_target_special_symbol): Likewise. (_bfd_ecoff_set_alignment_hook): Likewise. * mach-o-target.c (bfd_mach_o_bfd_is_target_special_symbol): Likewise. * mmo.c (mmo_bfd_is_target_special_symbol): Likewise. * nlm-target.h (nlm_bfd_is_target_special_symbol): Likewise. * oasys.c (oasys_construct_extended_name_table): Likewise. (oasys_write_armap): Likewise. (oasys_write_ar_hdr): Likewise. (oasys_bfd_is_target_special_symbol): Likewise. * pef.c (bfd_pef_bfd_is_target_special_symbol): Likewise. * plugin.c (bfd_plugin_bfd_is_target_special_symbol): Likewise. * ppcboot.c (ppcboot_bfd_is_target_special_symbol): Likewise. * som.c (som_bfd_is_target_special_symbol): Likewise. * srec.c (srec_bfd_is_target_special_symbol): Likewise. * tekhex.c (tekhex_bfd_is_target_special_symbol): Likewise. * verilog.c (verilog_bfd_is_target_special_symbol): Likewise. * versados.c (versados_bfd_is_target_special_symbol): Likewise. (versados_bfd_reloc_name_lookup): Likewise. * vms-alpha.c (vms_bfd_is_target_special_symbol): Likewise. (vms_bfd_define_start_stop): Likewise. (alpha_vms_bfd_is_target_special_symbol): Likewise. * wasm-module.c (wasm_bfd_is_target_special_symbol): Likewise. * xsym.c (bfd_sym_bfd_is_target_special_symbol): Likewise. * elf32-arc.c (get_replace_function): Assign replacement function to func pointer. * elf32-i370.c (i370_noop): Update prototype. gas * config/obj-elf.c (elf_pseudo_table): Remove now redundant casts. (obj_elf_vtable_inherit): Rename to obj_elf_get_vtable_inherit. (obj_elf_vtable_inherit): New stub function that calls obj_elf_get_vtable_inherit. (obj_elf_vtable_entry): Rename to obj_elf_get_vtable_entry. (obj_elf_vtable_entry): New stub function that calls obj_elf_get_vtable_entry. * config/obj-elf.h (obj_elf_vtable_inherit): Update prototype. (obj_elf_vtable_entry) Likewise. (obj_elf_get_vtable_inherit) Likewise. (obj_elf_get_vtable_entry) Likewise. * config/tc-arm.c (md_pseudo_table): Remove now redundant cast. * config/tc-i386c (md_pseudo_table): Likewise. * config/tc-hppa.c (pa_vtable_entry): Call obj_elf_get_vtable_entry. (pa_vtable_inherit): Call obj_elf_get_vtable_inherit. * config/tc-mips.c (s_mips_file): Replace call to dwarf2_get_file with call to dwarf2_get_filename. * dwarf2dbg.c (dwarf2_directive_file): Rename to dwarf2_directive_filename. (dwarf2_directive_file): New stub function that calls dwarf2_directive_filename. * dwarf2dbg.h: Prototype dwarf2_directive_filename. opcodes * metag-dis.c (print_fmmov): Double buffer size to avoid warning about truncation of printing.
2018-02-13MIPS/GAS/testsuite: Correct duplicate `Loongson-3A tests' test nameMaciej W. Rozycki2-1/+5
Correct a duplicate `Loongson-3A tests' GAS test name introduced with commit 986754024085 ("Add Loongson3A specific instructions"), <https://sourceware.org/ml/binutils/2010-12/msg00447.html>, shared between gas/testsuite/gas/mips/loongson-3a.d and gas/testsuite/gas/mips/loongson-3a-2.d. gas/ * testsuite/gas/mips/loongson-3a-2.d: Rename test.
2018-02-12MIPS/GAS/test: Fix an n32 `.reginfo' size test failureMaciej W. Rozycki2-1/+6
Correct a commit 2d6dda71611b ("MIPS/BFD: Correctly report unsupported `.reginfo' section size") issue and avoid a GAS test failure: regexp_diff match failure regexp "^.*: Incorrect `\.reginfo' section size; expected 24, got 28$" line "../as-new: dump.o: Incorrect `.reginfo' section size; expected 24, got 32" FAIL: MIPS assembled .reginfo section size (n32) on MIPS targets other than bare-metal ones. The reason for this failure is section padding to alignment, done in `size_seg'. For n32 `.reginfo' the section alignment is set to 3, and therefore the section is padded to a multiple of 8, except for bare-metal targets, for which padding is unconditionally disabled in `md_section_align'. Use `--no-pad-sections' then to disable padding for all targets, so that the size of `.reginfo' is always the same, matching the message pattern. gas/ * testsuite/gas/mips/reginfo-2-n32.d: Add `--no-pad-sections' to `as' flags.
2018-02-12MIPS: Fix encoding for MIPSr6 sigrie instruction.Henry Wong4-6/+12
The instruction encoding for the MIPS r6 sigrie instruction seems to be incorrect. It's currently 0x4170xxxx (which overlaps with ei, di, evp, and dvp), but should be 0x0417xxxx. See ISA reference[1][2]. References: [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Imagination Technologies, Inc., Document Number: MD00086, Revision 6.06, December 15, 2016, Table A.4 "MIPS32 REGIMM Encoding of rt Field", p. 452 [2] "MIPS Architecture For Programmers Volume II-A: The MIPS64 Instruction Set Reference Manual", Imagination Technologies, Inc., Document Number: MD00087, Revision 6.06, December 15, 2016, Table A.4 "MIPS64 REGIMM Encoding of rt Field", p. 581 opcodes/ * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding. gas/ * testsuite/gas/mips/r6.d: Update for "sigrie" encoding fix. * testsuite/gas/mips/r6-n32.d: Likewise. * testsuite/gas/mips/r6-n64.d: Likewise.
2018-02-12Update Russian translation for the gas/ sub-directory.Nick Clifton2-574/+600
2018-02-08PR22819, powerpc gas "instruction address is not a multiple of 4"Alan Modra8-35/+70
Checks for insn alignment were hopelessly confused when misaligned data starts a new frag. The real-world testcase happened to run out of frag space in the middle of emitting a trace-back table via something like: .byte 0 /* VERSION=0 */ .byte 9 /* LANG=C++ */ .byte 34 /* Bits on: has_tboff, fp_present */ .byte 64 /* Bits on: name_present */ .byte 128 /* Bits on: stores_bc, FP_SAVED=0 */ .byte 0 /* Bits on: GP_SAVED=0 */ .byte 2 /* FIXEDPARMS=2 */ .byte 1 /* FLOATPARMS=0, parmsonstk */ .long 0 .long 768 /* tb_offset: 0x300 */ .hword 45 /* Function name length: 45 */ .long 0x334e5a5f .long 0x31766f70 .long 0x65744932 .long 0x69746172 .long 0x7a5f6e6f .long 0x64504533 .long 0x5f534e50 .long 0x72463431 .long 0x61746361 .long 0x74535f6c .long 0x74637572 .byte 0x45 .byte 0 The trigger being those misaligned .long's output for the function name. A most horrible way to output a string, especially considering endian issues.. PR 22819 * config/tc-ppc.c (md_assemble): Rewrite insn alignment checking. (ppc_frag_check): Likewise. * testsuite/gas/ppc/misalign.d, * testsuite/gas/ppc/misalign.l, * testsuite/gas/ppc/misalign.s: New test. * testsuite/gas/ppc/misalign2.d, * testsuite/gas/ppc/misalign2.s: New test. * testsuite/gas/ppc/ppc.exp: Run them.
2018-02-05RISC-V/GAS: Correct an `expr' global shadowing error for pre-4.8 GCCMaciej W. Rozycki2-3/+8
Correct a commit f0531ed6a429 ("Compress loads/stores with implicit 0 offset.") regression and remove a `-Wshadow' compilation error: cc1: warnings being treated as errors .../gas/config/tc-riscv.c: In function 'riscv_handle_implicit_zero_offset': .../gas/config/tc-riscv.c:1194: error: declaration of 'expr' shadows a global declaration .../gas/expr.h:180: error: shadowed declaration is here make[4]: *** [tc-riscv.o] Error 1 which for versions of GCC before 4.8 prevents GAS for RISC-V targets from being built. See also GCC PR c/53066. gas/ * config/tc-riscv.c (riscv_handle_implicit_zero_offset): Rename `expr' parameter to `ep'.
2018-02-05MIPS/BFD: Correctly report unsupported `.reginfo' section sizeMaciej W. Rozycki6-0/+24
Report an error when an unsupported `.reginfo' section size is found in `_bfd_mips_elf_section_processing', removing an assertion that triggers at elfxx-mips.c:7105 in GAS when assembling input like: .section .reginfo .word 0xdeadbeef and in `objcopy --rename-section' when renaming an incorrectly sized section to `.reginfo'. bfd/ * elfxx-mips.c (_bfd_mips_elf_section_processing): For SHT_MIPS_REGINFO sections don't assert the correct size and report an error instead. binutils/ * testsuite/binutils-all/mips/mips-reginfo.d: New test. * testsuite/binutils-all/mips/mips-reginfo-n32.d: New test. * testsuite/binutils-all/mips/mips-reginfo.s: New test source. * testsuite/binutils-all/mips/mips.exp: Run the new tests. gas/ * testsuite/gas/mips/reginfo-2.d: New test. * testsuite/gas/mips/reginfo-2-n32.d: New test. * testsuite/gas/mips/reginfo-2.l: New test stderr output. * testsuite/gas/mips/reginfo-2.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2018-02-05Updated Brazillian portuguese and Russian translationNick Clifton2-273/+263
2018-01-31PR22714, Assembler preprocessor loses track of \@Alan Modra2-1/+29
The PR22714 testcase is such that the input buffer processed by do_scrub_chars ends on this line 1: bug "Returning to usermode but unexpected PSR bits set?", \@ right at the backslash. (The line is part of a macro definition.) The next input buffer then starts with '@' which starts a comment on ARM, and the check for \@ fails due to to == tostart. Now it would be possible to simply access to[-1] in this particular case, but that's ugly, and to be absolutely safe from people deliberately trying to crash gas we'd need the read.c:read_a_source_file buffer passed to do_scrub_chars to have a single byte pad at the start. PR 22714 * app.c (last_char): New static var. (struct app_save): Add last_char field. (app_push, app_pop): Handle it. (do_scrub_chars): Use last_char in test for "\@". Set last_char.
2018-01-30Fix PR gas/22738 (.dc.a directive has wrong size on SPARC 64-bit).Eric Botcazou3-2/+26
The .dc.a directive has wrong size (32 bits) on SPARC 64-bit because the assembler sets the correct BFD architecture only at the very end of the processing and it's too late for the directive. It's fixed by defining TARGET_MACH and making it return a sensible default value. gas/ * config/tc-sparc.h (sparc_mach): Declare. (TARGET_MACH): Define to above. * config/tc-sparc.c (sparc_mach): New function. (sparc_md_end): Minor tweak. ld/ * testsuite/ld-elf/pr22450.d: Remove reference to SPARC64.
2018-01-29Update Russian translation for the gas sub-directoryNick Clifton2-4734/+9701
2018-01-26MIPS/GAS: Correct `mips-*-windiss' target emulation configurationMaciej W. Rozycki2-0/+6
Fix a commit 0a44bf6950b3 ("mips-vxworks support"), <https://sourceware.org/ml/binutils/2006-03/msg00179.html>, regression and override the choice of the `vxworks' target environment introduced with commit ea3eed15006f ("Add generic vxworks GAS target."), <https://sourceware.org/ml/binutils/2005-01/msg00052.html>, for `mips-*-windiss' targets as they have not been converted to the VxWorks target format introduced with the former commit, removing a GAS target format selection failure: Assembler messages: Fatal error: selected target format 'elf32-bigmips-vxworks' unknown on any assembly attempt with `mips-windiss' and equivalent target configurations. gas/ * configure.tgt: Use generic emulation for `mips-*-windiss', overriding the blanket choice made for `*-*-windiss'.
2018-01-26MIPS/GAS: Correct `mips-*-sysv4*' target emulation configurationMaciej W. Rozycki2-1/+6
Use `mips-*-sysv4*' rather than `mips-*-sysv4*MP*' to match the system type for System V Release 4 MIPS targets, removing a GAS target selection failure: Assembler messages: Fatal error: selected target format 'elf32-bigmips' unknown on any assembly attempt with `mips-sysv4' and equivalent target configurations. These would typically be called `mips-sni-sysv4' (Sinix) vs `mips-dde-sysv4.2MP' (Supermax). This corrects commit 8614eeee67f9 ("Traditional MIPS patches"), <https://sourceware.org/ml/binutils/2000-07/msg00018.html>, making GAS target selection match commit dd745cfae548 ("Traditional MIPS patches"), <https://sourceware.org/ml/binutils/2000-07/msg00018.html>, and commit 3548145dcbf6 ("Traditional MIPS patches"), <https://sourceware.org/ml/binutils/2000-07/msg00018.html>, which added support for these targets to BFD and LD respectively. gas/ * configure.tgt: Use `mips-*-sysv4*' rather than `mips-*-sysv4*MP*'.
2018-01-24[GAS][AARCH64]Add group relocations to create PC-relative offset.Renlin Li16-0/+263
This is a patch to add the gas support for group relocations to create a 16, 32, 48, or 64 bit PC-relative offset inline. The following relocations are added along with the test cases: BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC, BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC, BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC, BFD_RELOC_AARCH64_MOVW_PREL_G3. bfd/ 2018-01-24 Renlin Li <renlin.li@arm.com> * reloc.c: Add BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC, BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC, BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC, BFD_RELOC_AARCH64_MOVW_PREL_G3. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elfnn-aarch64.c (elfNN_aarch64_howto_table): Add entries for BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC, BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC, BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC, BFD_RELOC_AARCH64_MOVW_PREL_G3. gas/ 2018-01-24 Renlin Li <renlin.li@arm.com> * config/tc-aarch64.c (reloc_table): add entries for BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC, BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC, BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC, BFD_RELOC_AARCH64_MOVW_PREL_G3. (process_movw_reloc_info): Supports newly added MOVW_PREL relocations. (md_apply_fix): Likewise * testsuite/gas/aarch64/prel_g0.s: New. * testsuite/gas/aarch64/prel_g0.d: New. * testsuite/gas/aarch64/prel_g0_nc.s: New. * testsuite/gas/aarch64/prel_g0_nc.d: New. * testsuite/gas/aarch64/prel_g1.s: New. * testsuite/gas/aarch64/prel_g1.d: New. * testsuite/gas/aarch64/prel_g1_nc.s: New. * testsuite/gas/aarch64/prel_g1_nc.d: New. * testsuite/gas/aarch64/prel_g2.s: New. * testsuite/gas/aarch64/prel_g2.d: New. * testsuite/gas/aarch64/prel_g2_nc.s: New. * testsuite/gas/aarch64/prel_g2_nc.d: New. * testsuite/gas/aarch64/prel_g3.s: New. * testsuite/gas/aarch64/prel_g3.d: New.
2018-01-23MIPS/GAS: Correct default ABI selection for `mips64*-ps2-elf*'Maciej W. Rozycki3-2/+10
Correct an issue with the `mips64*-ps2-elf*' target introduced with commit e407c74b5b60 ("Support for MIPS R5900 (Sony Playstation 2)"), <https://sourceware.org/ml/binutils/2012-12/msg00240.html> and make the n32 ABI the default for GAS, consistently with how BFD and LD are configured for this target. gas/ * configure.ac: Also set `mips_default_abi' to N32_ABI for `mips64*-ps2-elf*'. * configure: Regenerate.
2018-01-23MIPS/GAS: Remove a stale OPTION_COMPAT_ARCH_BASE option markerMaciej W. Rozycki2-1/+5
Complement commit 23fce1e31156 ("MIPS16 intermix test failure"), <https://sourceware.org/ml/binutils/2009-01/msg00335.html>, and remove a stale option marker entry. gas/ * config/tc-mips.c (options): Remove OPTION_COMPAT_ARCH_BASE enum value.
2018-01-23Enable Intel PCONFIG instruction.Igor Tsimbalist10-1/+74
Intel has disclosed a set of new instructions for Icelake processor. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf This patch enables Intel PCONFIG instruction. gas/ * config/tc-i386.c (cpu_arch): Add .pconfig. * doc/c-i386.texi: Document .pconfig. * testsuite/gas/i386/i386.exp: Add PCONFIG tests. * testsuite/gas/i386/pconfig-intel.d: New test. * testsuite/gas/i386/pconfig.d: Likewise. * testsuite/gas/i386/pconfig.s: Likewise. * testsuite/gas/i386/x86-64-pconfig-intel.d: Likewise. * testsuite/gas/i386/x86-64-pconfig.d: Likewise. * testsuite/gas/i386/x86-64-pconfig.s: Likewise. opcodes/ * i386-dis.c (enum): Add pconfig. * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS. (cpu_flags): Add CpuPCONFIG. * i386-opc.h (enum): Add CpuPCONFIG. (i386_cpu_flags): Add cpupconfig. * i386-opc.tbl: Add PCONFIG instruction. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2018-01-23Enable Intel WBNOINVD instruction.Igor Tsimbalist10-0/+74
Intel has disclosed a set of new instructions for Icelake processor. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf This patch enables Intel WBNOINVD instruction. gas/ * config/tc-i386.c (cpu_arch): Add .wbnoinvd. * doc/c-i386.texi: Document .wbnoinvd. * testsuite/gas/i386/i386.exp: Add WBNOINVD tests. * testsuite/gas/i386/wbnoinvd-intel.d: New test. * testsuite/gas/i386/wbnoinvd.d: Likewise. * testsuite/gas/i386/wbnoinvd.s: Likewise. * testsuite/gas/i386/x86-64-wbnoinvd-intel.d: Likewise. * testsuite/gas/i386/x86-64-wbnoinvd.d: Likewise. * testsuite/gas/i386/x86-64-wbnoinvd.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_0F09. * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS. (cpu_flags): Add CpuWBNOINVD. * i386-opc.h (enum): Add CpuWBNOINVD. (i386_cpu_flags): Add cpuwbnoinvd. * i386-opc.tbl: Add WBNOINVD instruction. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2018-01-23MIPS/GAS: Correct `as --help' always reporting `o32' as the default ABIMaciej W. Rozycki2-3/+13
Remove an issue with `as --help' always reporting `o32' as the default ABI regardless of what the default actually is, originally caused by commit cac012d6d394 ("check mips abi x linker emulation compatibility"), <https://sourceware.org/ml/binutils/2003-05/msg00187.html> missing an update here. gas/ * config/tc-mips.c (md_show_usage): Correctly indicate the configuration-specific default ABI.
2018-01-23MIPS/GAS: Add missing `-mmips16e2'/`-mno-mips16e2' help textMaciej W. Rozycki2-0/+8
Correct a commit 25499ac7ee92 ("MIPS16e2: Add MIPS16e2 ASE support") GAS bug and add missing help text for the `-mmips16e2' and `-mno-mips16e2' options added with said commit. gas/ * config/tc-mips.c (md_show_usage): Report `-mmips16e2' and `-mno-mips16e2' options.
2018-01-22GAS/doc: Correct `.set nomips16e2' directive description syntaxMaciej W. Rozycki2-2/+7
gas/ * doc/c-mips.texi (MIPS ASE Instruction Generation Overrides): Correct syntax of the `.set nomips16e2' directive description.
2018-01-22Fix the RX assembler so that it can handle escaped double quote characters, ↵Oleg Endo5-2/+30
ie: \" PR 22737 * config/tc-rx.c (rx_start_line): Handle escaped double-quote character. * testsuite/gas/rx/pr22737.s: New test. * testsuite/gas/rx/pr22737.d: Likewise. * testsuite/gas/rx/rx.exp: Run the new test.
2018-01-19[gas/ARM] Remove spurious commentsThomas Preud'homme2-2/+5
Remove spurious comments after the definition of ToC and ToU. 2018-01-19 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (ToC macro): Remove spurious comment. (ToU macro): Likewise.
2018-01-17RISC-V: Fix bug in prior addi/c.nop patch.Jim Wilson2-0/+15
gas/ * config/tc-riscv.c (validate_riscv_insn) <'z'>: New. (riscv_ip) <'z'>: New. opcodes/ * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2018-01-17Replace CET bit with IBT and SHSTK bits.Igor Tsimbalist12-6/+69
The latest specification for Intel CET technology defined two new bits instead of previously used CET bit. These are IBT and SHSTK bits. The patch replaces CET bit with IBT and SHSTK bits. gas/ * config/tc-i386.c (cpu_arch): Delete .cet. Add .ibt, .shstk. (cpu_noarch): Add noibt, noshstk. (parse_insn): Change cpucet to cpuibt. * doc/c-i386.texi: Delete .cet. Add .ibt, .shstk. * testsuite/gas/i386/cet-ibt-inval.l: New test. * testsuite/gas/i386/cet-ibt-inval.s: Likewise. * testsuite/gas/i386/cet-shstk-inval.l: Likewise. * testsuite/gas/i386/cet-shstk-inval.s: Likewise. * testsuite/gas/i386/x86-64-cet-ibt-inval.l: Likewise. * testsuite/gas/i386/x86-64-cet-ibt-inval.s: Likewise. * testsuite/gas/i386/x86-64-cet-shstk-inval.l: Likewise. * testsuite/gas/i386/x86-64-cet-shstk-inval.s: Likewise. opcodes/ * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET. Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS, CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK. (cpu_flags): Add CpuIBT, CpuSHSTK. * i386-opc.h (enum): Add CpuIBT, CpuSHSTK. (i386_cpu_flags): Add cpuibt, cpushstk. * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2018-01-16Update translations for various binutils components.Nick Clifton2-2448/+2647
ld * po/pt_BR.po: Updated Brazilian Portugese translation. opcodes * po/pt_BR.po: Updated Brazilian Portugese translation. * po/de.po: Updated German translation. gas * po/fr.po: Updated French translation. binutils* po/fr.po: Updated French translation.
2018-01-15RISC-V: Add support for addi that compresses to c.nop.Jim Wilson3-2/+9
gas/ * testsuite/gas/riscv/c-zero-imm.s: Test addi that compresses to c.nop. * testsuite/gas/riscv/c-zero-imm.d: Likewise. opcodes/ * riscv-opc.c (match_c_nop): New. (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2018-01-15[ARM] Add new macro for Thumb-only opcodesThomas Preud'homme2-9/+27
Armv8-M Security Extensions introduced some Thumb-only opcodes (eg. sg). These are defined using the TUE and TCE macros, setting the Arm execution state related fields to 0/NULL. This patch adds 2 new macros to avoid filling this field and clearly identify Thumb-only instructions. 2018-01-15 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (ToC): Define macro. (ToU): Likewise. (insns): Make use of above macros for new instructions introduced in Armv8-M.
2018-01-15[ARM] Enable conditional Armv8-M instructionsThomas Preud'homme3-11/+27
Newly introduced instructions common to ARMv8-M Baseline and Mainline are currently all marked as unconditional. However, all instructions but sg (ie. blxns, bxns, tt, ttt, tta, ttat, vlldm and vlstm) do actually support conditional execution. This patch fixes the definition of these instructions accordingly. 2018-01-15 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (insns): Make blxns, bxns, tt, ttt, tta, ttat, vlldm and vlstm conditionally executable and reindent parameters. * testsuite/gas/arm/archv8m-cmse-main.s: Add conditional version of aforementionned instructions.
2018-01-15[ARM] No IT usage deprecation for ARMv8-MThomas Preud'homme7-54/+70
Deprecations related to the use of the IT instruction introduced in Armv8-A do not apply to Armv8-M Baseline and mainline. However the warning logic do not distinguish between the various profiles and warn whenever the architecture version is 8. This patch adds a check to exclude M profile architectures from this warning. This works as expected when -march is specified on the command-line or a .arch/.cpu directive exist. However, in autodetection mode the CPU/architecture targeted is only known once the instructions have been all processed but this code is run when IT instruction is processed. It is therefore not possible to distinguish between Armv8-M and Armv8-A in that mode. The approach chosen here is not to warn in autodetection mode. The udf.d testcase that relied on that behavior to test deprecation warning for Armv8-A is therefore updated to explicitely pass -march=armv8-a. 2018-01-15 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (it_fsm_post_encode): Do not warn if targeting M profile architecture or if in autodetection mode. Clarify that deprecation is for performance reason and concerns Armv8-A and Armv8-R. * testsuite/gas/arm/armv8-ar-bad.l: Adapt to new IT deprecation warning message. * testsuite/gas/arm/armv8-ar-it-bad.l: Likewise. * testsuite/gas/arm/sp-pc-validations-bad-t-v8a.l: Likewise. * testsuite/gas/arm/udf.l: Likewise. * testsuite/gas/arm/udf.d: Assemble for Armv8-A explicitely.
2018-01-15Update Ukranian translations for bfd, binutils, gas, gold, ld and opcodesNick Clifton2-2446/+2678
2018-01-13Update pot filesNick Clifton2-2430/+2597
2018-01-13Bump version number to 2.30.51Nick Clifton2-10/+14
bfd/ * version.m4: Bump version to 2.30.51 * configure: Regenerate. binutils/ * configure: Regenerate. gas/ * configure: Regenerate. gprof/ * configure: Regenerate. ld/ * configure: Regenerate. opcodes/ * configure: Regenerate.
2018-01-13Add note about 2.30 branch creation to changelogsNick Clifton1-0/+1
2018-01-13Add 2.30 markers to NEWS files.Nick Clifton2-0/+6
binutils/ * NEWS: Add marker for 2.30. gas/ * NEWS: Add marker for 2.30. ld/ * NEWS: Add marker for 2.30.
2018-01-12Fix compile time warning building aout targeted architectures.Gunther Nikl2-3/+10
Occasionally I build an out-of-tree a.out target (m68k-amigaos). After a system upgrade which included a newer compiler (clang 4) the build produces warnings like this: warning: macro expansion producing 'defined' has undefined behavior [-Wexpansion-to-defined] This is caused by the macro gas/config/aout_gnu.h:USE_EXTENDED_RELOC. Since it is in a header file, the warning triggers for several files. I am unsure what solution is preferable, thus I am suggesting two patches: a) keep the offending macro but define it explicitly to 0 and 1 b) replace the macro usage with its value where it is used. Either patch removes the warning for clang. I did not check with a recent GCC. * gas/config/aout_gnu.h (USE_EXTENDED_RELOC): Explicitly define to 0 and 1. Remove a dangling reference to "AMD 29000" in a comment.
2018-01-11Remove VL variants for 4FMAPS and 4VNNIW insns.Igor Tsimbalist20-1030/+36
AVX512_4FMAPS and AVX512_4VNNIW insns are marked as having AVX512VL variants. That is wrong as SDM doesn't define such instructions. The patch removes these VL variants. gas/ * testsuite/gas/i386/avx512_4fmaps-warn.l: Change xmm to zmm. * testsuite/gas/i386/avx512_4fmaps-warn.s: Likewise. * testsuite/gas/i386/avx512_4fmaps_vl-intel.d: Delete. * testsuite/gas/i386/avx512_4fmaps_vl-warn.l: Likewise. * testsuite/gas/i386/avx512_4fmaps_vl-warn.s: Likewise. * testsuite/gas/i386/avx512_4fmaps_vl.d: Likewise. * testsuite/gas/i386/avx512_4fmaps_vl.s: Likewise. * testsuite/gas/i386/avx512_4vnniw_vl-intel.d: Likewise. * testsuite/gas/i386/avx512_4vnniw_vl.d: Likewise. * testsuite/gas/i386/avx512_4vnniw_vl.s: Likewise. * testsuite/gas/i386/i386.exp: Delete _vl tests for 4fmaps an 4vnniw tests. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl-intel.d: Delete. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.l: Likewise. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.s: Likewise. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl.s: Likewise. * testsuite/gas/i386/x86-64-avx512_4vnniw_vl-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512_4vnniw_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512_4vnniw_vl.s: Likewise. opcodes/ * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns. * i386-tbl.h: Regenerate.
2018-01-11gas tc-arm.c warning fixAlan Modra2-1/+6
* config/tc-arm.c (aeabi_set_public_attributes): Avoid false positive "‘profile’ may be used uninitialized".
2018-01-10x86: fix Disp8 handling for scalar AVX512_4FMAPS insnsJan Beulich13-381/+402
Just like their packed counterparts the memory operand is always 16 bytes wide, and the Disp8 scaling is the same for all of them. (As a side note: I'm also surprised by there being AVX512VL variants of these as well as the AVX512_4VNNIW ones - the SDM doesn't define any such.) Adjust the test cases also for the packed forms to actually live up to their promise of testing correct Disp8 encoding.
2018-01-10x86: fix Disp8 handling for AVX512VL VPCMP*{B,W} variantsJan Beulich7-0/+46
In commit 2645e1d079 ("x86: add support for AVX-512 VPCMP*{B,W} pseudo-ops") I screwed up the Disp8MemShift values of the AVX512VL variants.
2018-01-09RISC-V: Disassemble x0 based addresses as 0.Jim Wilson3-0/+21
gas/ * testsuite/gas/riscv/auipc-x0.d: New. * testsuite/gas/riscv/auipc-x0.s: New. opcodes/ * riscv-dis.c (maybe_print_address): If base_reg is zero, then the hi_addr value is zero.
2018-01-09[Arm] Add CSDB instructionJames Greenhalgh6-0/+44
CSDB is a new instruction which Arm has defined. As it shares the encoding space with NOP instructions, it is available from Armv3 in Arm mode, and Armv6T2 in Thumb mode. OK? If so, please commit on my behalf as I don't have commit rights over here. Thanks, James --- opcodes/ 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com> * arm-dis.c (arm_opcodes): Add csdb. (thumb32_opcodes): Add csdb. gas/ 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com> * config/tc-arm.c (insns): Add csdb, enable for Armv3 and above in Arm execution state, and Armv6T2 and above in Thumb execution state. * testsuite/gas/arm/csdb.s: New. * testsuite/gas/arm/csdb.d: New. * testsuite/gas/arm/thumb2_it_bad.l: Add csdb. * testsuite/gas/arm/thumb2_it_bad.s: Add csdb.
2018-01-09Add support for the AArch64's CSDB instruction.James Greenhalgh2-1/+6
CSDB is a new instruction which Arm has defined. It has the same encoding as HINT #0x14 and is available at all architecture levels. opcodes * aarch64-tbl.h (aarch64_opcode_table): Add "csdb". * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. gas * testsuite/gas/aarch64/system.d: Update expected results to expect CSDB.
2018-01-08x86: Properly encode vmovd with 64-bit memeoryH.J. Lu5-0/+145
For historical reason, we allow movd/vmovd with 64-bit register and memeory operands. But for vmovd, we failed to handle 64-bit memeory operand. This has been gone unnoticed since AT&T syntax always treats memory operand as 32-bit memory. This patch properly encodes vmovd with 64-bit memeory operands. It also removes AVX512 vmovd with 64-bit operands since GCC has case TYPE_SSEMOV: switch (get_attr_mode (insn)) { case MODE_DI: /* Handle broken assemblers that require movd instead of movq. */ if (!HAVE_AS_IX86_INTERUNIT_MOVQ && (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))) return "%vmovd\t{%1, %0|%0, %1}"; return "%vmovq\t{%1, %0|%0, %1}"; and all AVX512 GNU assemblers set HAVE_AS_IX86_INTERUNIT_MOVQ, GCC won't generate AVX512 vmovd with 64-bit operand. gas/ PR gas/22681 * testsuite/gas/i386/i386.exp: Run x86-64-movd and x86-64-movd-intel. * testsuite/gas/i386/x86-64-movd-intel.d: New file. * testsuite/gas/i386/x86-64-movd.d: Likewise. * testsuite/gas/i386/x86-64-movd.s: Likewise. opcodes/ PR gas/22681 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand. Remove AVX512 vmovd with 64-bit operands. * i386-tbl.h: Regenerated.
2018-01-08Add a description of the X86_64 assembler's .largcomm pseudo-op.Nick Clifton2-1/+16
PR 22553 * doc/c-i386.texi (i386-Directives): Document the .largecomm directive.
2018-01-04RISC-V: Add 2 missing privileged registers.Jim Wilson3-24/+33
gas/ * testsuite/gas/riscv/priv-reg.s: Add missing stval and mtval. * testsuite/gas/riscv/priv-reg.d: Likewise. include/ * opcode/riscv-opc.h (CSR_SBADADDR): Rename to CSR_STVAL. Rename DECLARE_CSR entry. Add alias to map sbadaddr to CSR_STVAL. (CSR_MBADADDR): Rename to CSR_MTVAL. Rename DECLARE_CSR entry. Add alias to map mbadaddr to CSR_MTVAL.
generated by cgit v1.1 at 2024-07-13 11:23:01 +0000