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authorJim Wilson <jimw@sifive.com>2018-01-15 14:53:44 -0800
committerJim Wilson <jimw@sifive.com>2018-01-15 14:53:44 -0800
commit2721d702a055fe0f7621386123b103b5c4d84662 (patch)
treebb592824b55f213951d96e600a373f0eaf6be999 /gas
parentdb422fb2120e311318657d9c7dd0e7b0b5a5eac9 (diff)
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RISC-V: Add support for addi that compresses to c.nop.
gas/ * testsuite/gas/riscv/c-zero-imm.s: Test addi that compresses to c.nop. * testsuite/gas/riscv/c-zero-imm.d: Likewise. opcodes/ * riscv-opc.c (match_c_nop): New. (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
Diffstat (limited to 'gas')
-rw-r--r--gas/ChangeLog5
-rw-r--r--gas/testsuite/gas/riscv/c-zero-imm.d5
-rw-r--r--gas/testsuite/gas/riscv/c-zero-imm.s1
3 files changed, 9 insertions, 2 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 63fa139..1c128ee 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2018-01-15 Jim Wilson <jimw@sifive.com>
+
+ * testsuite/gas/riscv/c-zero-imm.s: Test addi that compresses to c.nop.
+ * testsuite/gas/riscv/c-zero-imm.d: Likewise.
+
2018-01-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (ToC): Define macro.
diff --git a/gas/testsuite/gas/riscv/c-zero-imm.d b/gas/testsuite/gas/riscv/c-zero-imm.d
index ac47e80..c138966 100644
--- a/gas/testsuite/gas/riscv/c-zero-imm.d
+++ b/gas/testsuite/gas/riscv/c-zero-imm.d
@@ -11,6 +11,7 @@ Disassembly of section .text:
[ ]+2:[ ]+4581[ ]+li[ ]+a1,0
[ ]+4:[ ]+8a01[ ]+andi[ ]+a2,a2,0
[ ]+6:[ ]+8a81[ ]+andi[ ]+a3,a3,0
-[ ]+8:[ ]+00070713[ ]+mv[ ]+a4,a4
-[ ]+c:[ ]+0781[ ]+addi[ ]+a5,a5,0
+[ ]+8:[ ]+0001[ ]+nop
+[ ]+a:[ ]+00070713[ ]+mv[ ]+a4,a4
+[ ]+e:[ ]+0781[ ]+addi[ ]+a5,a5,0
#...
diff --git a/gas/testsuite/gas/riscv/c-zero-imm.s b/gas/testsuite/gas/riscv/c-zero-imm.s
index 650313d..a07baa4 100644
--- a/gas/testsuite/gas/riscv/c-zero-imm.s
+++ b/gas/testsuite/gas/riscv/c-zero-imm.s
@@ -4,6 +4,7 @@
c.li a1,0
andi a2,a2,0
c.andi a3,0
+ addi x0,x0,0
# Don't let this compress to a hint.
addi a4,a4,0
# These are hints.