| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2024-05-29 | x86/Intel: warn about undue mnemonic suffixes | Jan Beulich | 33 | -157/+117 |
| 2024-05-29 | x86/Intel: SHLD/SHRD have dual meaning | Jan Beulich | 4 | -2/+79 |
| 2024-05-29 | PR31796, Internal error in write_function_pdata at obj-coff-seh | Alan Modra | 1 | -2/+22 |
| 2024-05-28 | gas, aarch64: Add SVE2 lut extension | saurabh.jha@arm.com | 9 | -1/+464 |
| 2024-05-28 | gas, aarch64: Add AdvSIMD lut extension | saurabh.jha@arm.com | 10 | -0/+499 |
| 2024-05-28 | Fix typo in assembler documentation | Nick Clifton | 1 | -1/+1 |
| 2024-05-28 | Fix: internal error in write_function_pdata at obj-coff-seh | Nick Clifton | 1 | -0/+5 |
| 2024-05-28 | RISC-V: Fix U insn; replace opcode6 with opcode7 in gas/doc/c-riscv.texi | Javier Mora | 1 | -22/+22 |
| 2024-05-24 | Re: LoongArch: gas: Adjust DWARF CIE alignment factors | Alan Modra | 1 | -22/+22 |
| 2024-05-24 | gas: extend \+ support to .irp / .irpc | Jan Beulich | 6 | -23/+24 |
| 2024-05-24 | gas: adjust handling of quotes for .irpc | Jan Beulich | 5 | -21/+40 |
| 2024-05-24 | x86: simplify VexVVVV_SRC2 handling for the XOP case | Jan Beulich | 1 | -9/+5 |
| 2024-05-24 | x86: simplify / consolidate check_{word,long,qword}_reg() | Jan Beulich | 1 | -16/+4 |
| 2024-05-24 | x86: correct VCVT{,U}SI2SD | Jan Beulich | 3 | -5/+56 |
| 2024-05-22 | restore build with --enable-maintainer-mode | Indu Bhagat | 3 | -3/+0 |
| 2024-05-22 | aarch64: fix incorrect encoding for system register pmsdsfr_el1 | Matthieu Longo | 1 | -2/+2 |
| 2024-05-22 | Support APX zero-upper | Cui, Lili | 7 | -2/+288 |
| 2024-05-22 | X86: Remove "i.rex" to eliminate extra conditional branch | Cui, Lili | 1 | -1/+1 |
| 2024-05-22 | Add check for 8-bit old registers in EVEX format | Cui, Lili | 3 | -3/+9 |
| 2024-05-22 | x86: Split REX/REX2 old registers judgment. | Cui, Lili | 1 | -16/+14 |
| 2024-05-21 | gas: ginsn: remove unnecessary buffer allocation and free | Indu Bhagat | 1 | -15/+12 |
| 2024-05-21 | gas: drop remnants of ia64-*-aix* | Jan Beulich | 2 | -24/+0 |
| 2024-05-20 | aarch64: Add support for the fpmr system register | Claudio Bantaloukas | 4 | -0/+23 |
| 2024-05-20 | RISC-V: PR31733, Change initial CFI operation from DW_CFA_def_cfa_register to... | Sung-hun Kim | 1 | -1/+1 |
| 2024-05-17 | aarch64: correct SVE2.1 ld2q (scalar plus scalar) | Jan Beulich | 1 | -1/+1 |
| 2024-05-17 | aarch64: correct SVE2.1 ld{3,4}q / st{3,4}q (scalar plus immediate) | Jan Beulich | 3 | -13/+13 |
| 2024-05-17 | LoongArch: gas: Adjust DWARF CIE alignment factors | mengqinggang | 1 | -5/+9 |
| 2024-05-16 | gas: sframe: fix typo to use FP instead of BP | Indu Bhagat | 1 | -4/+4 |
| 2024-05-16 | aarch64: fp8 convert and scale - add sme2 insn variants | Victor Do Nascimento | 6 | -2/+623 |
| 2024-05-16 | aarch64: fp8 convert and scale - add sve2 insn variants | Victor Do Nascimento | 7 | -0/+313 |
| 2024-05-16 | aarch64: fp8 convert and scale - Add advsimd insn variants | Victor Do Nascimento | 5 | -0/+581 |
| 2024-05-16 | aarch64: fp8 convert and scale - add feature flags and related structures | Victor Do Nascimento | 2 | -0/+3 |
| 2024-05-16 | aarch64: add SPMU feature and its associated registers | Matthieu Longo | 3 | -0/+27 |
| 2024-05-16 | Move assembler "IRP \+" test into a separate file. Add XFAILs for targets th... | Nick Clifton | 6 | -9/+19 |
| 2024-05-16 | arm: remove incorrect handling of FP bignums in move_or_literal_pool | Richard Earnshaw | 1 | -6/+24 |
| 2024-05-16 | Fix FAIL: macros altmacro | Alan Modra | 1 | -5/+5 |
| 2024-05-15 | gas: Fix \+ expansion for .irp and .irpc | Fangrui Song | 3 | -1/+10 |
| 2024-05-15 | aarch64: Add sysreg features to +d128 dependencies | Andrew Carlotti | 1 | -2/+5 |
| 2024-05-15 | aarch64: Add simd dependency to +sha2 | Andrew Carlotti | 1 | -1/+1 |
| 2024-05-15 | aarch64: testsuite: share test utils macros and use them | Matthieu Longo | 23 | -519/+576 |
| 2024-05-15 | aarch64: testsuite: reorder write and read to match macro order | Matthieu Longo | 11 | -292/+286 |
| 2024-05-15 | aarch64: testsuite: use same regs for read and write tests | Matthieu Longo | 8 | -377/+377 |
| 2024-05-15 | aarch64: testsuite: replace instruction addresses by regex | Matthieu Longo | 1 | -28/+28 |
| 2024-05-14 | Fix gas's 'macro count' test for various targets | Nick Clifton | 2 | -10/+15 |
| 2024-05-14 | arm: update documentation for removal of the Maverick extension | Richard Earnshaw | 1 | -7/+4 |
| 2024-05-14 | arm: opcodes: remove Maverick disassembly. | Richard Earnshaw | 2 | -8/+8 |
| 2024-05-14 | arm: remove Maverick support from the assembler. | Richard Earnshaw | 1 | -179/+4 |
| 2024-05-14 | arm: remove tests for Maverick FPU extensions | Richard Earnshaw | 12 | -2010/+0 |
| 2024-05-13 | Add new assembler macro pseudo-variable \+ which counts the number of times a... | Nick Clifton | 10 | -14/+77 |
| 2024-05-08 | RISC-V: Support B, Zaamo and Zalrsc extensions. | Nelson Chu | 13 | -10/+25 |
