gas, aarch64: Add SVE2 lut extension

Introduces instructions for the SVE2 lut extension for AArch64. They are documented in the following links:
* luti2: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions/LUTI2--Lookup-table-read-with-2-bit-indices-?lang=en
* luti4: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions/LUTI4--Lookup-table-read-with-4-bit-indices-?lang=en

These instructions use new SVE2 vector operands. They are called
SVE_Zm1_23_INDEX, SVE_Zm2_22_INDEX, and Zm3_12_INDEX and they have
1 bit, 2 bit, and 3 bit indices respectively.

The lsb and width of these new operands are the same as many existing
operands but the convention is to give different names to fields that
serve different purpose so we introduced new fields in aarch64-opc.c
and aarch64-opc.h.

We made a design choice for the second operand of the halfword variant of
luti4 with two register tables. We could have either defined a new operand,
like SVE_Znx2, or we could have use the existing operand SVE_ZnxN. With
the new operand, we would need to implement constraints on register
lists based on either operand or opcode flag. With existing operand, we
could just existing constraint checks using opcode flag. We chose
the second approach and went with SVE_ZnxN and added opcode flag to
enforce lengths of vector register list operands. This way, we can reuse
the existing constraint check logic.

9 files changed, 464 insertions, 1 deletions

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 4154786..fec17c4 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -6784,7 +6784,10 @@ parse_operands (char *str, const aarch64_opcode *opcode)
 	  info->qualifier = AARCH64_OPND_QLF_S_D;
 	  break;
 
+	case AARCH64_OPND_SVE_Zm1_23_INDEX:
+	case AARCH64_OPND_SVE_Zm2_22_INDEX:
 	case AARCH64_OPND_SVE_Zm3_INDEX:
+	case AARCH64_OPND_SVE_Zm3_12_INDEX:
 	case AARCH64_OPND_SVE_Zm3_22_INDEX:
 	case AARCH64_OPND_SVE_Zm3_19_INDEX:
 	case AARCH64_OPND_SVE_Zm3_11_INDEX:
diff --git a/gas/testsuite/gas/aarch64/sme2-8-invalid.l b/gas/testsuite/gas/aarch64/sme2-8-invalid.l
index afea8bb..aa39365 100644
--- a/gas/testsuite/gas/aarch64/sme2-8-invalid.l
+++ b/gas/testsuite/gas/aarch64/sme2-8-invalid.l
@@ -128,7 +128,7 @@
 [^ :]+:[0-9]+: Info:    	luti2 {z0\.h-z3\.h}, zt0, z0\[0\]
 [^ :]+:[0-9]+: Info:    	luti2 {z0\.s-z3\.s}, zt0, z0\[0\]
 [^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti4 0,zt0,z0\[0\]'
-[^ :]+:[0-9]+: Error: expected a register at operand 2 -- `luti4 z0\.b,0,z0\[0\]'
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 2 -- `luti4 z0\.b,0,z0\[0\]'
 [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `luti4 z0\.b,zt0,0'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `luti4 z0\.h,zt0,z0\[-1\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `luti4 z0\.h,zt0,z0\[8\]'
diff --git a/gas/testsuite/gas/aarch64/sve2-lut-bad.d b/gas/testsuite/gas/aarch64/sve2-lut-bad.d
new file mode 100644
index 0000000..1134589
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-lut-bad.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a+lut
+#source: sve2-lut.s
+#error_output: sve2-lut-bad.l
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/sve2-lut-bad.l b/gas/testsuite/gas/aarch64/sve2-lut-bad.l
new file mode 100644
index 0000000..8bbdc3e
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-lut-bad.l
@@ -0,0 +1,34 @@
+[^ :]+: Assembler messages:
+.*: Error: selected processor does not support `luti2 z0.b,{z0.b},z0\[0\]'
+.*: Error: selected processor does not support `luti2 z31.b,{z0.b},z0\[0\]'
+.*: Error: selected processor does not support `luti2 z0.b,{z31.b},z0\[0\]'
+.*: Error: selected processor does not support `luti2 z0.b,{z0.b},z31\[0\]'
+.*: Error: selected processor does not support `luti2 z0.b,{z0.b},z0\[3\]'
+.*: Error: selected processor does not support `luti2 z4.b,{z9.b},z15\[2\]'
+.*: Error: selected processor does not support `luti2 z0.h,{z0.h},z0\[0\]'
+.*: Error: selected processor does not support `luti2 z31.h,{z0.h},z0\[0\]'
+.*: Error: selected processor does not support `luti2 z0.h,{z31.h},z0\[0\]'
+.*: Error: selected processor does not support `luti2 z0.h,{z0.h},z31\[0\]'
+.*: Error: selected processor does not support `luti2 z0.h,{z0.h},z0\[7\]'
+.*: Error: selected processor does not support `luti2 z4.h,{z9.h},z15\[2\]'
+.*: Error: selected processor does not support `luti2 z4.h,{z9.h},z15\[1\]'
+.*: Error: selected processor does not support `luti2 z4.h,{z9.h},z15\[4\]'
+.*: Error: selected processor does not support `luti4 z0.b,{z0.b},z0\[0\]'
+.*: Error: selected processor does not support `luti4 z31.b,{z0.b},z0\[0\]'
+.*: Error: selected processor does not support `luti4 z0.b,{z31.b},z0\[0\]'
+.*: Error: selected processor does not support `luti4 z0.b,{z0.b},z31\[0\]'
+.*: Error: selected processor does not support `luti4 z0.b,{z0.b},z0\[1\]'
+.*: Error: selected processor does not support `luti4 z4.b,{z9.b},z15\[1\]'
+.*: Error: selected processor does not support `luti4 z0.h,{z0.h},z0\[0\]'
+.*: Error: selected processor does not support `luti4 z31.h,{z0.h},z0\[0\]'
+.*: Error: selected processor does not support `luti4 z0.h,{z30.h},z0\[0\]'
+.*: Error: selected processor does not support `luti4 z0.h,{z0.h},z31\[0\]'
+.*: Error: selected processor does not support `luti4 z0.h,{z0.h},z0\[3\]'
+.*: Error: selected processor does not support `luti4 z4.h,{z9.h},z15\[2\]'
+.*: Error: selected processor does not support `luti4 z0.h,{z0.h,z1.h},z0\[0\]'
+.*: Error: selected processor does not support `luti4 z31.h,{z0.h,z1.h},z0\[0\]'
+.*: Error: selected processor does not support `luti4 z0.h,{z30.h,z31.h},z0\[0\]'
+.*: Error: selected processor does not support `luti4 z0.h,{z31.h,z0.h},z0\[0\]'
+.*: Error: selected processor does not support `luti4 z0.h,{z0.h,z1.h},z31\[0\]'
+.*: Error: selected processor does not support `luti4 z0.h,{z0.h,z1.h},z0\[3\]'
+.*: Error: selected processor does not support `luti4 z4.h,{z9.h,z10.h},z15\[2\]'
diff --git a/gas/testsuite/gas/aarch64/sve2-lut-illegal.d b/gas/testsuite/gas/aarch64/sve2-lut-illegal.d
new file mode 100644
index 0000000..5420963
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-lut-illegal.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a+lut+sve2
+#source: sve2-lut-illegal.s
+#error_output: sve2-lut-illegal.l
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/sve2-lut-illegal.l b/gas/testsuite/gas/aarch64/sve2-lut-illegal.l
new file mode 100644
index 0000000..bd6e419
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-lut-illegal.l
@@ -0,0 +1,212 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 z2\.b,\{z5\.h\},z7\[1\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	luti2 z2\.b, \{z5\.b\}, z7\[1\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 z2\.h,\{z5\.b\},z7\[1\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	luti2 z2\.b, \{z5\.b\}, z7\[1\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 z2\.b,\{z5\.h\},z7\[1\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	luti4 z2\.b, \{z5\.b\}, z7\[1\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 z2\.h,\{z5\.b\},z7\[1\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	luti4 z2\.b, \{z5\.b\}, z7\[1\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 z2\.b,\{z5\.h,z6\.h\},z12\[1\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	luti4 z2\.b, \{z5\.b-z6\.b\}, z12\[1\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 z2\.h,\{z5\.b,z6\.b\},z12\[1\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	luti4 z2\.b, \{z5\.b-z6\.b\}, z12\[1\]
+[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 2 -- `luti4 z2\.b,\{z5\.b,z6\.h\},z12\[1\]'
+[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 2 -- `luti4 z2\.h,\{z5\.h,z6\.b\},z12\[1\]'
+[^ :]+:[0-9]+: Error: syntax error in register list at operand 2 -- `luti2 z5\.b,\{\},z7\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti2 \{z5\.b\},z6\.b,z7\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 2 -- `luti2 z5\.b,\{z7\.b,z8\.b\},z9\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: syntax error in register list at operand 2 -- `luti2 z5\.h,\{\},z7\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti2 \{z5\.h\},z6\.h,z7\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 2 -- `luti2 z5\.h,\{z7\.h,z8\.h\},z9\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: syntax error in register list at operand 2 -- `luti4 z5\.b,\{\},z7\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti4 \{z5\.b\},z6\.b,z7\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 2 -- `luti4 z5\.b,\{z7\.b,z8\.b\},z9\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: syntax error in register list at operand 2 -- `luti4 z5\.h,\{\},z7\[1\]'
+[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti4 \{z5\.h\},z6\.h,z7\[1\]'
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 at operand 2 -- `luti4 z5\.h,\{z7\.h,z9\.h\},z3\[3\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 z5\.s,\{z7\.s\},z9\[1\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	luti2 z5\.b, \{z7\.b\}, z9\[1\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 z5\.s,\{z7\.s\},z9\[1\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	luti4 z5\.b, \{z7\.b\}, z9\[1\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 z5\.s,\{z7\.s,z8\.s\},z9\[1\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	luti4 z5\.b, \{z7\.b-z8\.b\}, z9\[1\]
+[^ :]+:[0-9]+: Error: comma expected between operands at operand 2 -- `luti2 z5\.b'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: comma expected between operands at operand 3 -- `luti2 z5\.b,\{z7\.b\}'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 3 -- `luti2 z5\.b,\{z7\.b\},z9\[1\],z11\.b'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: comma expected between operands at operand 2 -- `luti2 z5\.h'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: comma expected between operands at operand 3 -- `luti2 z5\.h,\{z7\.h\}'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 3 -- `luti2 z5\.h,\{z7\.h\},z9\[1\],z11\.h'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: comma expected between operands at operand 2 -- `luti4 z5\.b'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: comma expected between operands at operand 3 -- `luti4 z5\.b,\{z7\.b\}'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 3 -- `luti4 z5\.b,\{z7\.b\},z9\[1\],z11\.b'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: comma expected between operands at operand 2 -- `luti4 z5\.h'
+[^ :]+:[0-9]+: Error: comma expected between operands at operand 3 -- `luti4 z5\.h,\{z7\.h\}'
+[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 3 -- `luti4 z5\.h,\{z7\.h\},z9\[1\],z11\.h'
+[^ :]+:[0-9]+: Error: comma expected between operands at operand 3 -- `luti4 z5\.h,\{z7\.h,z8\.h\}'
+[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 3 -- `luti4 z5\.h,\{z7\.h,z8\.h\},z9\[1\],z11\.h'
+[^ :]+:[0-9]+: Error: unexpected character `t' in element size at operand 1 -- `luti2 z5\.t,\{z7\.b},z9\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: unexpected character `t' in element size at operand 2 -- `luti2 z5\.b,\{z7\.t},z9\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `luti2 z5\.b,\{z7\.b},z9\.b'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: unexpected character `t' in element size at operand 1 -- `luti2 z5\.t,\{z7\.h},z9\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: unexpected character `t' in element size at operand 2 -- `luti2 z5\.h,\{z7\.t},z9\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `luti2 z5\.h,\{z7\.h},z9\.h'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: unexpected character `t' in element size at operand 1 -- `luti4 z5\.t,\{z7\.b},z9\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: unexpected character `t' in element size at operand 2 -- `luti4 z5\.b,\{z7\.t},z9\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `luti4 z5\.b,\{z7\.b},z9\.b'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: unexpected character `t' in element size at operand 1 -- `luti4 z5\.t,\{z7\.h,z8\.h},z9\[1\]'
+[^ :]+:[0-9]+: Error: unexpected character `t' in element size at operand 2 -- `luti4 z5\.h,\{z7\.t,z8\.h},z9\[1\]'
+[^ :]+:[0-9]+: Error: unexpected character `t' in element size at operand 2 -- `luti4 z5\.h,\{z7\.h,z8\.t},z9\[1\]'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `luti4 z5\.h,\{z7\.h,z8\.h},z9\.h'
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti2 5.b,\{z7.b\},z9\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `luti2 z5.b,\{z7\},z9\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: syntax error in register list at operand 2 -- `luti2 z5.b,\{7.b\},z9\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `luti2 z5.b,\{z7.b\},9\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti2 5.h,\{z7.h\},z9\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `luti2 z5.h,\{z7\},z9\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: syntax error in register list at operand 2 -- `luti2 z5.h,\{7.h\},z9\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `luti2 z5.h,\{z7.h\},9\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti4 5\.b,\{z7.b},z9\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `luti4 z5\.b,\{z7\},z9\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: syntax error in register list at operand 2 -- `luti4 z5\.b,\{7\.b\},z9\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `luti4 z5\.b,\{z7\.b\},9\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 2 -- `luti4 z5\.h,\{z7,z8\.h\},z9\[1\]'
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti4 5\.h,\{z7\.h,z8\.h},z9\[1\]'
+[^ :]+:[0-9]+: Error: syntax error in register list at operand 2 -- `luti4 z5\.h,\{7\.h,z8\.h\},z9\[1\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `luti4 z5\.h,\{z7\.h,z8\.h\},9\[1\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 z5\.b,\{z7\.b\},z9\.b\[2\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	luti2 z5\.b, \{z7\.b\}, z9\[2\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 z5\.h,\{z7\.h\},z9\.h\[2\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	luti2 z5\.h, \{z7\.h\}, z9\[2\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 z5\.b,\{z7\.b\},z9\.b\[1\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	luti4 z5\.b, \{z7\.b\}, z9\[1\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 z5\.h,\{z7\.h\},z9\.h\[2\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	luti4 z5\.h, \{z7\.h\}, z9\[2\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 z5\.h,\{z7\.h,z8\.h\},z9\.h\[2\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	luti4 z5\.h, \{z7\.h-z8\.h\}, z9\[2\]
+[^ :]+:[0-9]+: Error: missing braces at operand 1 -- `luti2 z4\.b\[2\],\{z9\.b\},z15'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: missing braces at operand 1 -- `luti2 z4\[2\],\{z9\.b\},z15'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: index not allowed inside register list at operand 2 -- `luti2 z4.b,\{z9.b\[2\]\},z15'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: missing braces at operand 1 -- `luti2 z4\[2\],\{z9\[2\]\},z15'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: missing braces at operand 1 -- `luti2 z4\.h\[2\],\{z9\.h\},z15'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: missing braces at operand 1 -- `luti2 z4\[2\],\{z9\.h\},z15'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: index not allowed inside register list at operand 2 -- `luti2 z4.h,\{z9.h\[2\]\},z15'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: missing braces at operand 1 -- `luti2 z4\[2\],\{z9\[2\]\},z15'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: missing braces at operand 1 -- `luti4 z4\.b\[2\],\{z9\.b\},z15'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: missing braces at operand 1 -- `luti4 z4\[2\],\{z9\.b\},z15'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: index not allowed inside register list at operand 2 -- `luti4 z4.b,\{z9.b\[2\]\},z15'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: missing braces at operand 1 -- `luti4 z4\[2\],\{z9\[2\]\},z15'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: missing braces at operand 1 -- `luti4 z4\.h\[2\],\{z9.h,z10.h\},z15'
+[^ :]+:[0-9]+: Error: missing braces at operand 1 -- `luti4 z4\[2\],\{z9.h,z10.h\},z15'
+[^ :]+:[0-9]+: Error: index not allowed inside register list at operand 2 -- `luti4 z4.h,\{z9.h,z10.h\[2\]\},z15'
+[^ :]+:[0-9]+: Error: missing braces at operand 1 -- `luti4 z4\[2\],\{z9,z10\[2\]\},z15'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `luti2 z4.b,\{z9.b\},z15.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `luti2 z4.b,\{z9.b\},z15'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `luti2 z4.h,\{z9.h\},z15.h'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `luti2 z4.h,\{z9.h\},z15'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `luti4 z4.b,\{z9.b\},z15.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `luti4 z4.b,\{z9.b\},z15'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `luti4 z4.h,\{z9.h\},z15.h'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `luti4 z4.h,\{z9.h\},z15'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `luti4 z4.h,\{z9.h,z10.h\},z15.h'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `luti4 z4.h,\{z9.h,z10.h\},z15'
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti2 z32.b,\{z9.b\},z15\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `luti2 z4.b,\{z32.b\},z4\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `luti2 z4.b,\{z9.b\},z32\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `luti2 z2.b,\{z9.b\},z4\[4\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `luti2 z4.b,\{z9.b\},z15\[-1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti2 z32.h,\{z9.h\},z15\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `luti2 z4.h,\{z32.h\},z4\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `luti2 z4.h,\{z9.h\},z32\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `luti2 z2.h,\{z9.h\},z4\[8\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `luti2 z4.h,\{z9.h\},z15\[-1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti4 z32.b,\{z9.b\},z15\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `luti4 z4.b,\{z32.b\},z4\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `luti4 z4.b,\{z9.b\},z32\[1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `luti4 z2.b,\{z9.b\},z4\[2\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `luti4 z4.b,\{z9.b\},z15\[-1\]'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti4 z32.h,\{z9.h\},z4\[2\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `luti4 z4.h,\{z32.h\},z15\[2\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `luti4 z4.h,\{z9.h\},z32\[2\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `luti4 z2.h,\{z9.h\},z15\[4\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `luti4 z4.h,\{z9.h\},z15\[-1\]'
diff --git a/gas/testsuite/gas/aarch64/sve2-lut-illegal.s b/gas/testsuite/gas/aarch64/sve2-lut-illegal.s
new file mode 100644
index 0000000..6be60e2
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-lut-illegal.s
@@ -0,0 +1,128 @@
+	// Operand mismatch
+	luti2	z2.b, { z5.h }, z7[1]
+	luti2	z2.h, { z5.b }, z7[1]
+	luti4	z2.b, { z5.h }, z7[1]
+	luti4	z2.h, { z5.b }, z7[1]
+	luti4	z2.b, { z5.h, z6.h }, z12[1]
+	luti4	z2.h, { z5.b, z6.b }, z12[1]
+	luti4	z2.b, { z5.b, z6.h }, z12[1]
+	luti4	z2.h, { z5.h, z6.b }, z12[1]
+
+	// Incorrect operands
+	.macro incorrect_operands, op, operand_type
+	\op	z5\operand_type, { }, z7[1]
+	\op	{ z5\operand_type }, z6\operand_type, z7[1]
+	\op	z5\operand_type, { z7\operand_type, z8\operand_type }, z9[1]
+	.endm
+
+	incorrect_operands luti2 .b
+	incorrect_operands luti2 .h
+	incorrect_operands luti4 .b
+	luti4	z5.h, { }, z7[1]
+	luti4	{ z5.h }, z6.h, z7[1]
+	luti4	z5.h, { z7.h, z9.h }, z3[3]
+
+	// Disallowed types
+	luti2	z5.s, { z7.s }, z9[1]
+	luti4	z5.s, { z7.s }, z9[1]
+	luti4	z5.s, { z7.s, z8.s }, z9[1]
+
+	// Incorrect number of operands
+	.macro incorrect_number_of_operands, op, operand_type
+	\op	z5\operand_type
+	\op	z5\operand_type, { z7\operand_type }
+	\op	z5\operand_type, { z7\operand_type }, z9[1], z11\operand_type
+	.endm
+	incorrect_number_of_operands luti2 .b
+	incorrect_number_of_operands luti2 .h
+	incorrect_number_of_operands luti4 .b
+	luti4	z5.h
+	luti4	z5.h, { z7.h }
+	luti4	z5.h, { z7.h }, z9[1], z11.h
+	luti4	z5.h, { z7.h, z8.h }
+	luti4	z5.h, { z7.h, z8.h }, z9[1], z11.h
+
+	// Spelling mistakes
+	.macro spelling_mistakes, op, operand_type
+	\op	z5.t, { z7\operand_type }, z9[1]
+	\op	z5\operand_type, { z7.t }, z9[1]
+	\op	z5\operand_type, { z7\operand_type }, z9\operand_type
+	.endm
+
+	spelling_mistakes luti2 .b
+	spelling_mistakes luti2 .h
+	spelling_mistakes luti4 .b
+	luti4	z5.t, { z7.h, z8.h }, z9[1]
+	luti4	z5.h, { z7.t, z8.h }, z9[1]
+	luti4	z5.h, { z7.h, z8.t }, z9[1]
+	luti4	z5.h, { z7.h, z8.h }, z9.h
+
+	// Missing qualifiers
+	.macro missing_qualifiers, op, operand_type
+	\op	5\operand_type, { z7\operand_type }, z9[1]
+	\op	z5\operand_type, { z7 }, z9[1]
+	\op	z5\operand_type, { 7\operand_type }, z9[1]
+	\op	z5\operand_type, { z7\operand_type }, 9[1]
+	.endm
+
+	missing_qualifiers luti2 .b
+	missing_qualifiers luti2 .h
+	missing_qualifiers luti4 .b
+	luti4	z5.h, { z7, z8.h }, z9[1]
+	luti4	5.h, { z7.h, z8.h }, z9[1]
+	luti4	z5.h, { 7.h, z8.h }, z9[1]
+	luti4	z5.h, { z7.h, z8.h }, 9[1]
+
+	// Index with qualifiers
+	luti2	z5.b, { z7.b }, z9.b[2]
+	luti2	z5.h, { z7.h }, z9.h[2]
+	luti4	z5.b, { z7.b }, z9.b[1]
+	luti4	z5.h, { z7.h }, z9.h[2]
+	luti4	z5.h, { z7.h, z8.h }, z9.h[2]
+
+	// Index on the wrong operand
+	.macro index_wrong_operand op, operand_type
+	\op	z4\operand_type[2], { z9\operand_type }, z15
+	\op	z4[2], { z9\operand_type }, z15
+	\op	z4\operand_type, { z9\operand_type[2] }, z15
+	\op	z4[2], { z9[2] }, z15
+	.endm
+
+	index_wrong_operand luti2 .b
+	index_wrong_operand luti2 .h
+	index_wrong_operand luti4 .b
+	luti4	z4.h[2], { z9.h, z10.h }, z15
+	luti4	z4[2], { z9.h, z10.h }, z15
+	luti4	z4.h, { z9.h, z10.h[2] }, z15
+	luti4	z4[2], { z9, z10[2] }, z15
+
+	// Missing index
+	luti2	z4.b, { z9.b }, z15.b
+	luti2	z4.b, { z9.b }, z15
+	luti2	z4.h, { z9.h }, z15.h
+	luti2	z4.h, { z9.h }, z15
+
+	luti4	z4.b, { z9.b }, z15.b
+	luti4	z4.b, { z9.b }, z15
+	luti4	z4.h, { z9.h }, z15.h
+	luti4	z4.h, { z9.h }, z15
+	luti4	z4.h, { z9.h, z10.h }, z15.h
+	luti4	z4.h, { z9.h, z10.h }, z15
+
+	// Out of range numbers
+	.macro out_of_range op, operand_type, max_index_plus_one
+	\op	z32\operand_type, { z9\operand_type }, z15[1]
+	\op	z4\operand_type, { z32\operand_type }, z4[1]
+	\op	z4\operand_type, { z9\operand_type }, z32[1]
+	\op	z2\operand_type, { z9\operand_type }, z4[\max_index_plus_one]
+	\op	z4\operand_type, { z9\operand_type }, z15[-1]
+	.endm
+
+	out_of_range luti2, .b, 4
+	out_of_range luti2, .h, 8
+	out_of_range luti4, .b, 2
+	luti4	z32.h, { z9.h }, z4[2]
+	luti4	z4.h, { z32.h }, z15[2]
+	luti4	z4.h, { z9.h }, z32[2]
+	luti4	z2.h, { z9.h }, z15[4]
+	luti4	z4.h, { z9.h }, z15[-1]
diff --git a/gas/testsuite/gas/aarch64/sve2-lut.d b/gas/testsuite/gas/aarch64/sve2-lut.d
new file mode 100644
index 0000000..7b39b17
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-lut.d
@@ -0,0 +1,41 @@
+#objdump: -dr
+#as: -march=armv8-a+lut+sve2
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+[^:]+:	4520b000 	luti2	z0.b, \{z0.b\}, z0\[0\]
+[^:]+:	4520b01f 	luti2	z31.b, \{z0.b\}, z0\[0\]
+[^:]+:	4520b3e0 	luti2	z0.b, \{z31.b\}, z0\[0\]
+[^:]+:	453fb000 	luti2	z0.b, \{z0.b\}, z31\[0\]
+[^:]+:	45e0b000 	luti2	z0.b, \{z0.b\}, z0\[3\]
+[^:]+:	45afb124 	luti2	z4.b, \{z9.b\}, z15\[2\]
+[^:]+:	4520a800 	luti2	z0.h, \{z0.h\}, z0\[0\]
+[^:]+:	4520a81f 	luti2	z31.h, \{z0.h\}, z0\[0\]
+[^:]+:	4520abe0 	luti2	z0.h, \{z31.h\}, z0\[0\]
+[^:]+:	453fa800 	luti2	z0.h, \{z0.h\}, z31\[0\]
+[^:]+:	45e0b800 	luti2	z0.h, \{z0.h\}, z0\[7\]
+[^:]+:	456fa924 	luti2	z4.h, \{z9.h\}, z15\[2\]
+[^:]+:	452fb924 	luti2	z4.h, \{z9.h\}, z15\[1\]
+[^:]+:	45afa924 	luti2	z4.h, \{z9.h\}, z15\[4\]
+[^:]+:	4560a400 	luti4	z0.b, \{z0.b\}, z0\[0\]
+[^:]+:	4560a41f 	luti4	z31.b, \{z0.b\}, z0\[0\]
+[^:]+:	4560a7e0 	luti4	z0.b, \{z31.b\}, z0\[0\]
+[^:]+:	457fa400 	luti4	z0.b, \{z0.b\}, z31\[0\]
+[^:]+:	45e0a400 	luti4	z0.b, \{z0.b\}, z0\[1\]
+[^:]+:	45efa524 	luti4	z4.b, \{z9.b\}, z15\[1\]
+[^:]+:	4520bc00 	luti4	z0.h, \{z0.h\}, z0\[0\]
+[^:]+:	4520bc1f 	luti4	z31.h, \{z0.h\}, z0\[0\]
+[^:]+:	4520bfc0 	luti4	z0.h, \{z30.h\}, z0\[0\]
+[^:]+:	453fbc00 	luti4	z0.h, \{z0.h\}, z31\[0\]
+[^:]+:	45e0bc00 	luti4	z0.h, \{z0.h\}, z0\[3\]
+[^:]+:	45afbd24 	luti4	z4.h, \{z9.h\}, z15\[2\]
+[^:]+:	4520b400 	luti4	z0.h, \{z0.h-z1.h\}, z0\[0\]
+[^:]+:	4520b41f 	luti4	z31.h, \{z0.h-z1.h\}, z0\[0\]
+[^:]+:	4520b7c0 	luti4	z0.h, \{z30.h-z31.h\}, z0\[0\]
+[^:]+:	4520b7e0 	luti4	z0.h, \{z31.h-z0.h\}, z0\[0\]
+[^:]+:	453fb400 	luti4	z0.h, \{z0.h-z1.h\}, z31\[0\]
+[^:]+:	45e0b400 	luti4	z0.h, \{z0.h-z1.h\}, z0\[3\]
+[^:]+:	45afb524 	luti4	z4.h, \{z9.h-z10.h\}, z15\[2\]
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/sve2-lut.s b/gas/testsuite/gas/aarch64/sve2-lut.s
new file mode 100644
index 0000000..e9c79c6
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-lut.s
@@ -0,0 +1,39 @@
+	// Valid luti2 instructions
+	luti2	z0.b, { z0.b }, z0[0]
+	luti2	z31.b, { z0.b }, z0[0]
+	luti2	z0.b, { z31.b }, z0[0]
+	luti2	z0.b, { z0.b }, z31[0]
+	luti2	z0.b, { z0.b }, z0[3]
+	luti2	z4.b, { z9.b }, z15[2]
+
+	luti2	z0.h, { z0.h }, z0[0]
+	luti2	z31.h, { z0.h }, z0[0]
+	luti2	z0.h, { z31.h }, z0[0]
+	luti2	z0.h, { z0.h }, z31[0]
+	luti2	z0.h, { z0.h }, z0[7]
+	luti2	z4.h, { z9.h }, z15[2]
+	luti2	z4.h, { z9.h }, z15[1]
+	luti2	z4.h, { z9.h }, z15[4]
+
+	// Valid luti4 instructions
+	luti4	z0.b, { z0.b }, z0[0]
+	luti4	z31.b, { z0.b }, z0[0]
+	luti4	z0.b, { z31.b }, z0[0]
+	luti4	z0.b, { z0.b }, z31[0]
+	luti4	z0.b, { z0.b }, z0[1]
+	luti4	z4.b, { z9.b }, z15[1]
+
+	luti4	z0.h, { z0.h }, z0[0]
+	luti4	z31.h, { z0.h }, z0[0]
+	luti4	z0.h, { z30.h }, z0[0]
+	luti4	z0.h, { z0.h }, z31[0]
+	luti4	z0.h, { z0.h }, z0[3]
+	luti4	z4.h, { z9.h }, z15[2]
+
+	luti4	z0.h, { z0.h, z1.h }, z0[0]
+	luti4	z31.h, { z0.h, z1.h }, z0[0]
+	luti4	z0.h, { z30.h, z31.h }, z0[0]
+	luti4	z0.h, { z31.h, z0.h }, z0[0]
+	luti4	z0.h, { z0.h, z1.h }, z31[0]
+	luti4	z0.h, { z0.h, z1.h }, z0[3]
+	luti4	z4.h, { z9.h, z10.h }, z15[2]