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2019-07-04gas/ELF: don't accumulate .type settingsJan Beulich8-1/+118
Recently a patch was submitted for a Xen Project test harness binary to override the compiler specified @object to @func (see [1]). In a reply I suggested we shouldn't make ourselves dependent on currently unspecified behavior of gas here: It accumulates all requests, and then bfd/elf.c:swap_out_syms(), in an apparently ad hoc manner, prioritizes certain flags over others. Make the behavior predictable: Generally the last .type is what counts. Exceptions are directives which set multiple bits (TLS, IFUNC, and UNIQUE): Subsequent directives requesting just the more generic bit (i.e. FUNC following IFUNC) won't clear the more specific one. Warn about incompatible changes, except from/to STT_NOTYPE. Also add a new target hook, which hppa wants to use right away afaict. In the course of adding the warning I ran into two ld testsuite failures. I can only assume that it was a copy-and-paste mistake that lead to the same symbol having its type set twice. [1] https://lists.xenproject.org/archives/html/xen-devel/2019-05/msg01980.html
2019-07-03Fix assembler tests to work with toolchains that have been configured with ↵Nick Clifton93-64/+194
--enable-generate-build-notes.
2019-07-02This patch fixes a bug in the AArch64 assembler where an incorrect ↵Barnaby Wilks6-1/+29
structural load/store by element instruction would generate the wrong error message. For example, when provided with the (incorrect) instruction st4 {v0.16b-v3.16b}[4],[x0] currently assembler provides the following error message "Error: comma expected between operands at operand 2 -- `st4 {v0.16b-v3.16b}[4],[x0]'". This was due to the assembler consuming the {v0.16b-v3.16b} as the first operand leaving [4],[x0] as what it believed to be the second operand. The actual error is that the first operand should be of element type and not vector type (as provided). The new diagnostic for this error is "Error: expected element type rather than vector type at operand 1 -- `st4 {v0.16b-v3.16b}[4],[x0]'. Added testcases to check for the correct diagnostic message as well as checking that variations of the structural load/store by element instruction also generate the error when they have the same problem. * config/tc-aarch64.c (parse_operands): Add error check. * testsuite/gas/aarch64/diagnostic.l: New test. * testsuite/gas/aarch64/diagnostic.s: New test. * testsuite/gas/aarch64/illegal.l: New tests. * testsuite/gas/aarch64/illegal.s: New tests.
2019-07-02[AArch64] Allow MOVPRFX to be used with FMOVRichard Sandiford3-0/+30
The entry for the FMOV alias of FCPY was missing C_SCAN_MOVPRFX. (The entry for FCPY itself was OK.) This was the only /m-predicated instruction I could see that was missing the flag. 2019-07-02 Richard Sandiford <richard.sandiford@arm.com> opcodes/ * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the SVE FMOV alias of FCPY. gas/ * testsuite/gas/aarch64/sve-movprfx_27.s, * testsuite/gas/aarch64/sve-movprfx_27.d: New test.
2019-07-02[AArch64] Add missing C_MAX_ELEM flags for SVE conversionsRichard Sandiford4-7/+80
SVE FCVTZS, FCVTZU, SCVTF and UCVTF need the same treatment as FCVT: the register size used in a predicated MOVPRFX must be the wider of the destination and source sizes. Since I was adding a (supposedly) complete set of tests for converts, it seemed more consistent to add a complete set of tests for shifts as well, even though there's no bug to fix there. 2019-07-02 Richard Sandiford <richard.sandiford@arm.com> opcodes/ * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries. gas/ * testsuite/gas/aarch64/sve-movprfx_26.s: Also test FCVTZS, FCVTZU, SCVTF, UCVTF, LSR and ASR. * testsuite/gas/aarch64/sve-movprfx_26.d: Update accordingly. * testsuite/gas/aarch64/sve-movprfx_26.l: Likewise.
2019-07-02[AArch64] Fix bogus MOVPRFX warning for GPR form of CPYRichard Sandiford4-3/+9
One of the MOVPRFX tests has: output register of preceding `movprfx' used as input at operand 3 -- `cpy z1.d,p1/m,x1' But X1 and Z1 are not the same register, so the instruction is actually OK. 2019-07-02 Richard Sandiford <richard.sandiford@arm.com> opcodes/ * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the registers in an instruction prefixed by MOVPRFX. gas/ * testsuite/gas/aarch64/sve-movprfx_25.s: Allow CPY Z1.D.P1/M,X1 to be prefixed by MOVPRFX. * testsuite/gas/aarch64/sve-movprfx_25.d: Update accordingly. * testsuite/gas/aarch64/sve-movprfx_25.l: Likewise.
2019-07-01Fix bug when generating REL type relocs for assembler generated build notes.Nick Clifton2-10/+21
PR 24748 * write.c (create_note_reloc): Add desc2_offset parameter. Change name of offset parameter to note_offset. Only use desc2_offset when placing addend into REL reloc's address space. (maybe_generate_build_notes): Update parameters passed to create_note_reloc.
2019-07-01[gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AESMatthew Malcomson7-11/+43
I had mistakenly given all variants of the new SVE2 instructions pmull{t,b} a dependency on the feature +sve2-aes. Only the variant specifying .Q -> .D sizes should have that restriction. This patch fixes that mistake and updates the testsuite to have extra tests (matching the given set of tests per line in aarch64-tbl.h that the rest of the SVE2 tests follow). We also add a line in the documentation of the command line to clarify how to enable `pmull{t,b}` of this larger size. This is needed because all other instructions gated under the `sve2-aes` architecture extension are marked in the instruction documentation by an `HaveSVE2AES` check while pmull{t,b} is gated under the `HaveSVE2PMULL128` check. Regtested targeting aarch64-linux. gas/ChangeLog: 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com> * testsuite/gas/aarch64/illegal-sve2-aes.d: Update tests. * testsuite/gas/aarch64/illegal-sve2.l: Update tests. * doc/c-aarch64.texi: Add special note of pmull{t,b} instructions under the sve2-aes architecture extension. * testsuite/gas/aarch64/illegal-sve2.s: Add small size pmull{t,b} instructions. * testsuite/gas/aarch64/sve2.d: Add small size pmull{t,b} disassembly. * testsuite/gas/aarch64/sve2.s: Add small size pmull{t,b} instructions. include/ChangeLog: 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): sve_size_013 renamed to sve_size_13. opcodes/ChangeLog: 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new sve_size_13 icode to account for variant behaviour of pmull{t,b}. * aarch64-dis-2.c: Regenerate. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new sve_size_13 icode to account for variant behaviour of pmull{t,b}. * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier. (OP_SVE_VVV_Q_D): Add new qualifier. (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier. (struct aarch64_opcode): Split pmull{t,b} into those requiring AES and those not.
2019-07-01Document the .value directive supported by the x86 and x86_64 assemblers.Nick Clifton2-0/+12
PR 24738 * doc/c-i386.texi (i386-Directives): Add a description of the Value directive.
2019-07-01Correct a typo in the description of the Align and P2align directives.Nick Clifton2-2/+9
PR 24737 * doc/as.texi (Align): Add missing word to description of pseudo-op. (P2align): Likewise.
2019-07-01Fix spelling error in assembler documentation.Nick Clifton2-1/+6
2019-07-01x86: drop Vec_Imm4Jan Beulich2-25/+19
It is pretty wasteful to have a per-operand flag which is used in exactly 4 cases. It can be relatively easily replaced, and by doing so I've actually found some dead code to remove at the same time (there's no case of ImmExt set at the same time as Vec_Imm4).
2019-07-01x86: limit ImmExt abuseJan Beulich2-13/+17
In quite a few cases ImmExt gets used when there's not really any immediate, but rather a degenerate ModR/M byte. ENCL{S,U} show how this case is supposed to be dealt with. Eliminate most abuses, leaving in place (for now) only ones where process_immext() is involved.
2019-07-01x86: optimize AND/OR with twice the same registerJan Beulich10-1/+435
It seems to be not uncommon for people to use AND or OR in this form for just setting the status flags. TEST, which doesn't write to any register other than EFLAGS, ought to be preferred. Make the change only for -O2 and above though, at least for now.
2019-07-01x86-64: optimize certain commutative VEX-encoded insnsJan Beulich14-1246/+1048
When they're in the 0F opcode space, swapping their source operands may allow switching from 3-byte to 2-byte VEX prefix encoding. Note that NaN behavior precludes us doing so for many packed and scalar floating point insns; such an optimization would need to be done by the compiler instead in this case, when it knows that NaN-s have undefined behavior anyway. While for explicitly specified AVX/AVX2 insns the optimization (for now at least) gets done only for -O2 and -Os, it is utilized by default in SSE2AVX mode, as there we're re-writing the programmer's specified insns anyway. Rather than introducing a new attribute flag, the change re-uses one which so far was meaningful only for EVEX-encoded insns.
2019-07-01x86: StaticRounding implies SAEJan Beulich2-6/+8
This implication allows to simplify some conditionals, thus slightly improving performance. This change also paves the way for re-using StaticRounding for non-EVEX insns.
2019-07-01x86: optimize EVEX packed integer logical instructionsJan Beulich24-17/+955
As long as there's no write mask as well as no broadcast, and as long as the scaled Disp8 wouldn't result in a shorter EVEX encoding, encode VPAND{D,Q}, VPANDN{D,Q}, VPOR{D,Q}, and VPXOR{D,Q} acting on only the lower 16 XMM/YMM registers using their VEX equivalents with -O1. Also take the opportunity and avoid looping twice over all operands when dealing with memory-with-displacement ones.
2019-07-01x86: add missing pseudo ops for VPCLMULQDQ ISA extensionJan Beulich19-18/+145
While the ISA extensions doc suggests them to be made available just like the SDM does for the PCLMULQDQ ISA extension, these weren't added when supposrt for the new extension was introduced. Also make sure the 64-bit non-AVX512 test actually tests VEX encodings, not EVEX ones.
2019-07-01x86: use encoding_length() also elsewhereJan Beulich2-32/+8
2019-07-01x86: warn about insns exceeding the 15-byte limitJan Beulich7-0/+146
Such insns will cause #UD when an attempt to execute them is made. See also http://www.sandpile.org/x86/opc_enc.htm.
2019-06-27i386: Check vector length for scatter/gather prefetch instructionsH.J. Lu1-0/+9
Since not all vector lengths are supported by scatter/gather prefetch instructions, decode them only with supported vector lengths. gas/ PR binutils/24719 * testsuite/gas/i386/disassem.s: Add test for vgatherpf0dps with invalid vector length. * testsuite/gas/i386/x86-64-disassem.s: Likewise. * testsuite/gas/i386/disassem.d: Updated. * testsuite/gas/i386/x86-64-disassem.d: Likewise. opcodes/ PR binutils/24719 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and EVEX_LEN_0F38C7_R_6_P_2_W_1. * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and PREFIX_EVEX_0F38C6_REG_6 entries. * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and EVEX_W_0F38C7_R_6_P_2 entries. * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
2019-06-27This fixes a bug in the ARm assembler where an immediate operand larger than ↵Barnaby Wilk s9-10/+54
4 bits (0xF) could be passed to the SMC (Secure Monitor Call) instruction. For example, this code is invalid: smc #0x6951 The code would previously check for and encode for up to 16 bit immediate values, however this immediate should instead be only a 4 bit value (as documented herehttps://static.docs.arm.com/ddi0406/c/DDI0406C_C_arm_architecture_reference_manual.pdf ). Fixed this by adding range checks in the relevant areas and also removing code that would encode more than the first 4 bits of the immediate (code that is now redundant, as any immediate operand larger than 0xF would error now anyway). gas * config/tc-arm.c (do_smc): Add range check for immediate operand. (do_t_smc): Add range check for immediate operand. Remove obsolete immediate encoding. (md_apply_fix): Fix range check. Remove obsolete immediate encoding. * testsuite/gas/arm/arch6zk.d: Fix test. * testsuite/gas/arm/arch6zk.s: Fix test. * testsuite/gas/arm/smc-bad.d: New test. * testsuite/gas/arm/smc-bad.l: New test. * testsuite/gas/arm/smc-bad.s: New test. * testsuite/gas/arm/thumb32.d: Fix test. * testsuite/gas/arm/thumb32.s: Fix test.
2019-06-27x86: add missing testJan Beulich2-0/+174
These files were mistakenly left out of commit c1dc7af521.
2019-06-27x86: allow VEX et al encodings in 16-bit (protected) modeJan Beulich15-4/+16793
These encodings aren't valid in real and VM86 modes, but they are very well usable in 16-bit protected mode. A few adjustments in the disassembler tables are needed where Ev or Gv were wrongly used. Additionally an adjustment is needed to avoid printing "addr32" when that's already recognizable by the use of %eiz. Furthermore the Iq operand template was wrong for XOP:0Ah encoding insns: They're having a uniform 32-bit immediate. Drop Iq and introduce Id instead. Clone a few existing test cases to exercise assembler and disassembler.
2019-06-26Fix a few non-dash safe xstormy16 shell scripts.Jim Wilson3-2/+8
Noticed by a customer while looking at a tangentially related problem. The gas testsuite for xstormy16 has two scripts that have a typo on the first line, they are missing the !. They also use shell syntax that doesn't work on a system where /bin/sh is dash. So I fixed the typo, changed the shell to bash, and made them executable, so that they now work when run directly even if /bin/sh is dash. gas/ * testsuite/gas/xstormy16/allinsn.sh: Change first line to #!/bin/bash and make it executable. * testsuite/gas/xstormy16/gcc.sh: Likewise.
2019-06-26i386: Document memory size reference in assemblerLili Cui2-5/+16
* doc/c-i386.texi: Document x/y/z instruction sufffixes in AT&T syntax and xmmword/ymmword/zmmword/fword/tbyte/oword ptr in Intel syntax.
2019-06-25MIPS/gas: Fix order of instructions in LI macro expansionFaraz Shahbazker7-37/+140
When MTHC1 instruction is paired with MTC1 to write a value to a 64-bit FPR, the MTC1 must be executed first, because the semantic definition of MTC1 is not aware that software will be using an MTHC1 to complete the operation, and sets the upper half of the 64-bit FPR to an UNPREDICTABLE value[1]. Fix the order of MTHC1 and MTC1 instructions in LI macro expansion. Modify the expansions to exploit moves from $zero directly by-passing the use of $AT, where ever possible. [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Wave Computing, Inc., Document Number: MD00086, Revision 5.04, December 11, 2013, Section 3.2 "Alphabetical List of Instructions", pp. 217. gas/ * config/tc-mips.c (macro) <M_LI>: Re-order MTHC1 with respect to MTC1 and use $0 for either part where possible. * testsuite/gas/mips/li-d.s: Add test cases for non-zero words in double precision constants. * testsuite/gas/mips/li-d.d: Update reference output. * testsuite/gas/mips/micromips@isa-override-1.d: Likewise. * testsuite/gas/mips/mips32r2@isa-override-1.d: Likewise. * testsuite/gas/mips/mips64r2@isa-override-1.d: Likewise.
2019-06-25x86: correct / adjust debug printingJan Beulich2-9/+19
For quite some time we've been using combinations of bits for specifying various registers in operands and templates. I think it was Alan who had indicated that likely the debug printing would need adjustment as a result. Here we go. Accumulator handling for GPRs gets changed to match that for FPU regs. For this to work, OPERAND_TYPE_ACC{32,64} get repurposed, with their original uses replaced by direct checks of the two bits of interest, which is cheaper than operand_type_equal() invocations. For SIMD registers nothing similar appears to be needed, as respective operands get stripped from the (copy of the) template before pt() is reached. The type change on pi() is to silence a compiler diagnostic. Arguably its other parameter could also be const-qualified.
2019-06-25x86: document certain command line options as "dangerous"Jan Beulich2-0/+11
Errata BT36, BT41, and BT230 mean that gas may, when using one ofthese options, produce code that causes #UD on (at least) SandyBridge systems.
2019-06-25x86: don't open code is_any_vex_encoding()Jan Beulich2-3/+5
2019-06-25x86: fix (dis)assembly of certain SSE2 insns in 16-bit modeJan Beulich4-0/+181
MOVNTI was wrongly assembled with a 66h prefix. Add IgnoreSize to address this. It and the scalar to/from integer conversion insns also were also wrongly using Ev / Gv, leading to 16-bit register names being printed when 32-bit ones were meant. Clone the 32-bit SSE2 test to cover both assembler and disassembler.
2019-06-25x86-64: also optimize ANDQ with immediate fitting in 7 bitsJan Beulich4-1/+25
The same reasoning applies here as did/does for immediates fitting in 31 bits.
2019-06-25x86: add CVT{,T}PS2PI cases to xmmwords testJan Beulich3-0/+12
I've (not so) recently noticed this further pair which should be tested here.
2019-06-25Fix logical expression in last commitAlan Modra2-1/+5
* config/tc-ppc.c (ppc_handle_align): Add parentheses.
2019-06-25PowerPC nopsAlan Modra6-19/+106
This patch corrects ppc rs_align_code handling to choose the alignment nops based on the machine in force at the alignment directive rather than the machine at the end of file. * config/tc-ppc.h (ppc_nop_select): Declare. (NOP_OPCODE): Define. * config/tc-ppc.c (ppc_elf_end, ppc_xcoff_end): Zero ppc_cpu. (ppc_nop_encoding_for_rs_align_code): New enum. (ppc_nop_select): New function. (ppc_handle_align): Don't use ppc_cpu here. Get nop type from frag. * testsuite/gas/ppc/groupnop.d, * testsuite/gas/ppc/groupnop.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2019-06-19i386: Check vector length for EVEX broadcast instructionsH.J. Lu5-4/+20
Since not all vector lengths are supported by EVEX broadcast instructions, decode them only with supported vector lengths. gas/ PR binutils/24700 * testsuite/gas/i386/disassem.s: Add test for vbroadcasti32x8 with invalid vector length. * testsuite/gas/i386/x86-64-disassem.s: Likewise. * testsuite/gas/i386/disassem.d: Updated. * testsuite/gas/i386/x86-64-disassem.d: Likewise. opcodes/ PR binutils/24700 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and EVEX_W_0F385B_P_2. (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0, EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and EVEX_LEN_0F385B_P_2_W_1. * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum. (EVEX_LEN_0F3819_P_2_W_1): Likewise. (EVEX_LEN_0F381A_P_2_W_0): Likewise. (EVEX_LEN_0F381A_P_2_W_1): Likewise. (EVEX_LEN_0F381B_P_2_W_0): Likewise. (EVEX_LEN_0F381B_P_2_W_1): Likewise. (EVEX_LEN_0F385A_P_2_W_0): Likewise. (EVEX_LEN_0F385A_P_2_W_1): Likewise. (EVEX_LEN_0F385B_P_2_W_0): Likewise. (EVEX_LEN_0F385B_P_2_W_1): Likewise.
2019-06-17i386: Check vector length for vshufXXX/vinsertXXX/vextractXXXH.J. Lu5-2/+19
Since not all vector lengths are supported by vshufXXX, vinsertXXX and vextractXXX, decode them only with supported vector lengths. gas/ PR binutils/24691 * testsuite/gas/i386/disassem.s: Add test for vshuff32x4 with invalid vector length. * testsuite/gas/i386/x86-64-disassem.s: Likewise. * testsuite/gas/i386/disassem.d: Updated. * testsuite/gas/i386/x86-64-disassem.d: Likewise. opcodes/ PR binutils/24691 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2. (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and EVEX_LEN_0F3A43_P_2_W_1. * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum. (EVEX_LEN_0F3A23_P_2_W_1): Likewise. (EVEX_LEN_0F3A38_P_2_W_0): Likewise. (EVEX_LEN_0F3A38_P_2_W_1): Likewise. (EVEX_LEN_0F3A39_P_2_W_0): Likewise. (EVEX_LEN_0F3A39_P_2_W_1): Likewise. (EVEX_LEN_0F3A3A_P_2_W_0): Likewise. (EVEX_LEN_0F3A3A_P_2_W_1): Likewise. (EVEX_LEN_0F3A3B_P_2_W_0): Likewise. (EVEX_LEN_0F3A3B_P_2_W_1): Likewise. (EVEX_LEN_0F3A43_P_2_W_0): Likewise. (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
2019-06-14Regenerate with approved autotools versionAlan Modra4-22/+14
bfd/ * Makefile.in: Regenerate. * configure: Regenerate. binutils/ * Makefile.in: Regenerate. * aclocal.m4: Regenerate. * doc/Makefile.in: Regenerate. gas/ * Makefile.in: Regenerate. * configure: Regenerate. * doc/Makefile.in: Regenerate. ld/ * Makefile.in: Regenerate. * configure: Regenerate. libctf/ * configure: Regenerate.
2019-06-12Add missing ChangeLog entriesPeter Bergner1-0/+5
2019-06-12Remove the ldmx mnemonic that never made it into POWER9.Peter Bergner2-4/+0
opcodes/ * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic. gas/ * testsuite/gas/ppc/power9.d: Delete ldmx tests. * testsuite/gas/ppc/power9.s: Likewise.
2019-06-06gas: Add .enqcmd and noenqcmd directivesH.J. Lu3-0/+10
2019-06-06 Lili Cui <lili.cui@intel.com> * config/tc-i386.c (cpu_arch): Add .enqcmd. (cpu_noarch): Add noenqcmd. * doc/c-i386.texi: Document noenqcmd.
2019-06-06gas: Correct ChangeLog for commit 5d79adc4b22b0abdH.J. Lu1-12/+14
2019-06-05i386: Check vector length for EVEX vextractfXX and vinsertfXXH.J. Lu5-2/+21
Since not all vector lengths are supported by EVEX vextractfXX and vinsertfXX, decode them only with supported vector lengths. gas/ PR binutils/24633 * testsuite/gas/i386/disassem.s: Add tests for invalid vector lengths for EVEX vextractfXX and vinsertfXX. * testsuite/gas/i386/x86-64-disassem.s: Likewise. * testsuite/gas/i386/disassem.d: Updated. * testsuite/gas/i386/x86-64-disassem.d: Likewise. opcodes/ PR binutils/24633 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2. (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0, EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0, EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0, EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0, EVEX_LEN_0F3A1B_P_2_W_1. * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum. (EVEX_LEN_0F3A18_P_2_W_1): Likewise. (EVEX_LEN_0F3A19_P_2_W_0): Likewise. (EVEX_LEN_0F3A19_P_2_W_1): Likewise. (EVEX_LEN_0F3A1A_P_2_W_0): Likewise. (EVEX_LEN_0F3A1A_P_2_W_1): Likewise. (EVEX_LEN_0F3A1B_P_2_W_0): Likewise. (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
2019-06-04i386: Check for reserved VEX.vvvv and EVEX.vvvvH.J. Lu5-0/+22
If VEX.vvvv and EVEX.vvvv are reserved, they must be all 1s, which are all 0s in inverted form. Add check for unused VEX.vvvv and EVEX.vvvv when disassembling VEX and EVEX instructions. gas/ PR binutils/24626 * testsuite/gas/i386/disassem.s: Add tests for reserved VEX.vvvv and EVEX.vvvv. * testsuite/gas/i386/x86-64-disassem.s: Likewise. * testsuite/gas/i386/disassem.d: Updated. * testsuite/gas/i386/x86-64-disassem.d: Likewise. opcodes/ PR binutils/24626 * i386-dis.c (print_insn): Check for unused VEX.vvvv and EVEX.vvvv when disassembling VEX and EVEX instructions. (OP_VEX): Set vex.register_specifier to 0 after readding vex.register_specifier. (OP_Vex_2src_1): Likewise. (OP_Vex_2src_2): Likewise. (OP_LWP_E): Likewise. (OP_EX_Vex): Don't check vex.register_specifier. (OP_XMM_Vex): Likewise.
2019-06-04Enable Intel AVX512_VP2INTERSECT insnH.J. Lu18-1/+425
This patch enables support for VP2INTERSECT in binutils. Please refer to https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf for VP2INTERSECT details. Make check-gas is ok. gas/ 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (cpu_arch): Add .avx512_vp2intersect. (cpu_noarch): Likewise. * doc/c-i386.texi: Document avx512_vp2intersect. * testsuite/gas/i386/i386.exp: Run vp2intersect tests. * testsuite/gas/i386/vp2intersect-intel.d: New test. * testsuite/gas/i386/vp2intersect.d: Likewise. * testsuite/gas/i386/vp2intersect.s: Likewise. * testsuite/gas/i386/vp2intersect-inval-bcast.l: Likewise. * testsuite/gas/i386/vp2intersect-inval-bcast.s: Likewise. * testsuite/gas/i386/x86-64-vp2intersect-intel.d: Likewise. * testsuite/gas/i386/x86-64-vp2intersect.d: Likewise. * testsuite/gas/i386/x86-64-vp2intersect.s: Likewise. * testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.l: Likewise. * testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.s: Likewise. opcodes/ 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3. * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT instructions. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS, CPU_ANY_AVX512_VP2INTERSECT_FLAGS. (cpu_flags): Add CpuAVX512_VP2INTERSECT. * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT. (i386_cpu_flags): Add cpuavx512_vp2intersect. * i386-opc.tbl: Add AVX512_VP2INTERSECT insns. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2019-06-04Add support for Intel ENQCMD[S] instructionsH.J. Lu13-1/+183
This patch enables support for ENQCMD[S] in binutils. Please refer to https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf for ENQCMD[S] details. Make check-gas is ok. gas/ChangeLog: 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com> Lili Cui <lili.cui@intel.com> * doc/c-i386.texi: Document enqcmd. * testsuite/gas/i386/enqcmd-intel.d: New file. * testsuite/gas/i386/enqcmd-inval.l: Likewise. * testsuite/gas/i386/enqcmd-inval.s: Likewise. * testsuite/gas/i386/enqcmd.d: Likewise. * testsuite/gas/i386/enqcmd.s: Likewise. * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise. * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise. * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise. * testsuite/gas/i386/x86-64-enqcmd.d: Likewise. * testsuite/gas/i386/x86-64-enqcmd.s: Likewise. * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval, enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval, and x86-64-enqcmd. opcodes/ChangeLog: 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (enum): Add MOD_0F38F8_PREFIX_1 and MOD_0F38F8_PREFIX_3. (prefix_table): New instructions (see prefix above). (mod_table): New instructions (see prefix above). * i386-gen.c (cpu_flag_init): Add entries for enqcmd. (cpu_flags): Add a bitfield for enqmcd. * i386-init.h: Regenerated. * i386-opc.h (enum): Add CpuENQCMD. (i386_cpu_flags): Add a bitfield for cpuenqcmd. * i386-opc.tbl: Add enqcmd and enqcmds instructions. * i386-init.h: Regenerated. * i386-tbl.h: Regenerated.
2019-05-30RISC-V: Fix lui argument parsing.Jim Wilson4-5/+16
This fixes a bug reported on the riscv.org sw-dev mailing list. This rejects "lui x1,symbol", as a symbol should only be accepted here when used inside %hi(). Without the fix, this gets assembled as "lui x1,0" with no relocation which is clearly wrong. gas/ * config/tc-riscv.c (riscv_ip) <'u'>: Move O_constant check inside if statement. Delete O_symbol and O_constant check after if statement. * testsuite/gas/riscv/auipc-parsing.s: Test lui with missing %hi. * testsuite/gas/riscv/auipc-parsing.l: Update.
2019-05-28x86: Add CheckRegSize to AVX512_BF16 instructions with Disp8ShiftVLH.J. Lu5-0/+27
For AVX512 instructions with Disp8ShiftVL and Broadcast, we may need to add CheckRegSize to check if broadcast matches the destination register size. gas/ PR gas/24625 * testsuite/gas/i386/inval-avx512f.s: Add tests for AVX512_BF16 instructions with invalid broadcast. * testsuite/gas/i386/x86-64-inval-avx512f.s: Likewise. * testsuite/gas/i386/inval-avx512f.l: Updated. * testsuite/gas/i386/x86-64-inval-avx512f.l: Likewise. opcodes/ PR gas/24625 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with Disp8ShiftVL. * i386-tbl.h: Regenerated.
2019-05-27Fix failure on powerpc 32-bit only targetsAlan Modra3-51/+140
Targets that lack ppc64 support were failing the new prefix-reloc test. This patch adds some test infrastructure to deal with that, and changes the powerpc gas usage info so that "-a64" is omitted when unsupported. I've been meaning to break up the usage message for a long time; While doing so causes translators some work now, it should make it easier next time a new powerpc option is added. * config/tc-ppc.c (is_ppc64_target): New function. (md_show_usage): Split up usage message. Don't show -a64 when unsupported. testsuite/gas/ppc/ppc.exp (supports_ppc64): New. (prefix-reloc): Only run for ppc64.
2019-05-24aarch64: override default elf .set handling in gasSzabolcs Nagy5-0/+78
Allow st_other values such as STO_AARCH64_VARIANT_PCS to be set for alias symbols independently. This is needed for ifunc symbols which are aliased to the resolver using .set and don't expect resolver attributes to override the ifunc symbol attributes. This means .variant_pcs must be added explicitly to aliases. gas/ChangeLog: * config/tc-aarch64.c (aarch64_elf_copy_symbol_attributes): Define. * config/tc-aarch64.h (aarch64_elf_copy_symbol_attributes): Declare. (OBJ_COPY_SYMBOL_ATTRIBUTES): Define. * testsuite/gas/aarch64/symbol-variant_pcs-3.d: New test. * testsuite/gas/aarch64/symbol-variant_pcs-3.s: New test.
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