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authorLili Cui <lili.cui@intel.com>2019-06-26 15:12:58 -0700
committerH.J. Lu <hjl.tools@gmail.com>2019-06-26 15:13:55 -0700
commitaa108c0c462e43ab77a1f178d8c8d2277ac73a57 (patch)
tree9ef0b21434fdc7e6e8cd3006922ea9cce4e841eb /gas
parenta68aa5d3020948564ef99d704d27e458ba22ad9d (diff)
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i386: Document memory size reference in assembler
* doc/c-i386.texi: Document x/y/z instruction sufffixes in AT&T syntax and xmmword/ymmword/zmmword/fword/tbyte/oword ptr in Intel syntax.
Diffstat (limited to 'gas')
-rw-r--r--gas/ChangeLog6
-rw-r--r--gas/doc/c-i386.texi15
2 files changed, 16 insertions, 5 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index bcc193e..c1b4625 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2019-06-26 Lili Cui <lili.cui@intel.com>
+
+ * doc/c-i386.texi: Document x/y/z instruction sufffixes in AT&T
+ syntax and xmmword/ymmword/zmmword/fword/tbyte/oword ptr in
+ Intel syntax.
+
2019-06-25 Faraz Shahbazker <fshahbazker@wavecomp.com>
* config/tc-mips.c (macro) <M_LI>: Re-order MTHC1 with
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 908c6ca..80bbcbe 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -590,11 +590,16 @@ instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
In AT&T syntax the size of memory operands is determined from the last
character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
@samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
-(32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
-this by prefixing memory operands (@emph{not} the instruction mnemonics) with
-@samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus,
-Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
-syntax.
+(32-bit) and quadruple word (64-bit) memory references. Mnemonic suffixes
+of @samp{x}, @samp{y} and @samp{z} specify xmm (128-bit vector), ymm
+(256-bit vector) and zmm (512-bit vector) memory references, only when there's
+no other way to disambiguate an instruction. Intel syntax accomplishes this by
+prefixing memory operands (@emph{not} the instruction mnemonics) with
+@samp{byte ptr}, @samp{word ptr}, @samp{dword ptr}, @samp{qword ptr},
+@samp{xmmword ptr}, @samp{ymmword ptr} and @samp{zmmword ptr}. Thus, Intel
+syntax @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
+syntax. In Intel syntax, @samp{fword ptr}, @samp{tbyte ptr} and
+@samp{oword ptr} specify 48-bit, 80-bit and 128-bit memory references.
In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
instruction with the 64-bit displacement or immediate operand.