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AgeCommit message (Expand)AuthorFilesLines
2022-11-14aarch64: Add support for Common Short Sequence Compression extensionAndre Vieira4-0/+340
2022-11-14x86: fold special-operand insn attributes into a single enumJan Beulich1-12/+12
2022-11-14[gas] arm: Add support for new unwinder directive ".pacspval".Srinath Parvathaneni4-0/+76
2022-11-14arm: Add support for Cortex-X1C CPU.Srinath Parvathaneni4-0/+12
2022-11-14objcopy renaming section with explicit flagsAlan Modra1-8/+1
2022-11-12PowerPC64 paddi -MrawAlan Modra2-0/+3
2022-11-11gas: accept custom ".linefile <n> ."Jan Beulich1-2/+4
2022-11-11x86: drop stray IsString from PadLock insnsJan Beulich1-1/+0
2022-11-11x86: drop duplicate sse4a entry from cpu_arch[]Jan Beulich1-1/+0
2022-11-10i386: Check invalid (%dx) usageH.J. Lu5-0/+44
2022-11-09x86/Intel: don't accept malformed EXTRQ / INSERTQJan Beulich4-16/+17
2022-11-09RISC-V: xtheadfmemidx: Use fp register in mnemonicsChristoph Müllner4-48/+50
2022-11-08Support Intel RAO-INTKong Lingling10-1/+115
2022-11-07configure: require libzstd >= 1.4.0Christophe Lyon1-10/+10
2022-11-07RISC-V: Remove RV32EF conflictTsukasa OI2-5/+0
2022-11-04x86: adjust recently introduced testcasesJan Beulich8-0/+8
2022-11-04Support Intel AVX-NE-CONVERTkonglin110-0/+1023
2022-11-04Support multiple .eh_frame sectionsJojo R3-3/+35
2022-11-04gas/doc/internals.texi: fix typoJojo R1-2/+1
2022-11-02x86: simplify expressions in update_imm()Jan Beulich1-23/+14
2022-11-02RISC-V: Fixed the missing $x+arch when adding odd paddings for alignment.Nelson Chu4-38/+67
2022-11-02Support Intel MSRLISTHu, Lin19-1/+47
2022-11-02Support Intel WRMSRNSHu, Lin19-1/+44
2022-11-02Add handler for more i386_cpu_flagsKong Lingling1-0/+17
2022-11-02Support Intel CMPccXADDHaochen Jiang9-1/+818
2022-11-02Support Intel AVX-VNNI-INT8Cui,Lili10-1/+547
2022-11-02Support Intel AVX-IFMAHongyu Wang15-15/+252
2022-11-01opcodes/arm: use '@' consistently for the comment characterAndrew Burgess121-2291/+2291
2022-10-31x86: minor improvements to optimize_imm() (part III)Jan Beulich1-9/+8
2022-10-31x86: Silence GCC 12 warning on tc-i386.cH.J. Lu2-5/+5
2022-10-31Support Intel PREFETCHICui, Lili13-3/+103
2022-10-31RX assembler: switch arguments of thw MVTACGU insn.Yoshinori Sato2-4/+8
2022-10-29RISC-V: Always generate mapping symbols at the start of the sections.Nelson Chu3-41/+0
2022-10-28gas: NEWS: Note support for RISC-V ZawrsPalmer Dabbelt1-0/+2
2022-10-28gas: NEWS: Add a missing newlinePalmer Dabbelt1-0/+1
2022-10-28RISC-V: Improve "bits undefined" diagnosticsTsukasa OI1-2/+2
2022-10-28RISC-V: Fallback for instructions longer than 64bTsukasa OI1-5/+8
2022-10-28RISC-V/gas: fix build with certain gcc versionsJan Beulich1-7/+7
2022-10-28RISC-V: Fix build failure for -Werror=maybe-uninitializedTsukasa OI1-1/+1
2022-10-28RISC-V: Output mapping symbols with ISA string.Nelson Chu24-328/+404
2022-10-27PowerPC: Add support for RFC02658 - MMA+ Outer-Product InstructionsPeter Bergner4-2/+81
2022-10-27PowerPC: Add support for RFC02653 - Dense Math FacilityPeter Bergner6-65/+270
2022-10-27re: Support Intel AMX-FP16Alan Modra2-0/+2
2022-10-24x86: consolidate VPCLMUL testsJan Beulich15-268/+156
2022-10-24x86: consolidate VAES testsJan Beulich15-352/+211
2022-10-24x86: emit {evex} prefix when disassembling ambiguous AVX512VL insnsJan Beulich31-361/+361
2022-10-21Support Intel AMX-FP16Cui,Lili9-1/+97
2022-10-20x86: Check VEX/EVEX encoding before checking vector operandsH.J. Lu5-4/+8
2022-10-20x86: re-work AVX-VNNI supportJan Beulich7-12/+36
2022-10-19aarch64-pe support for LD, GAS and BFDJedidiah Thompson8-25/+108
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