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2019-09-20bfd macro conversion to inline functions, sectionAlan Modra2-1/+5
This one exposed a bug in tic6x gas, found with inline function parameter type checking. struct bfd_section and struct bfd_symbol both have a flags field, so bfd_is_com_section (symbol) compiled OK when bfd_is_com_section was a macro but didn't special case common symbols. bfd/ * bfd-in.h (bfd_section_name, bfd_section_size, bfd_section_vma), (bfd_section_lma, bfd_section_alignment, bfd_section_flags), (bfd_section_userdata, bfd_is_com_section, discarded_section), (bfd_get_section_limit_octets, bfd_get_section_limit): Delete macros. * bfd.c (bfd_get_section_limit_octets, bfd_get_section_limit), (bfd_section_list_remove, bfd_section_list_append), (bfd_section_list_prepend, bfd_section_list_insert_after), (bfd_section_list_insert_before, bfd_section_removed_from_list): New inline functions. * section.c (bfd_is_und_section, bfd_is_abs_section), (bfd_is_ind_section, bfd_is_const_section, bfd_section_list_remove), (bfd_section_list_append, bfd_section_list_prepend), (bfd_section_list_insert_after, bfd_section_list_insert_before), (bfd_section_removed_from_list): Delete macros. (bfd_section_name, bfd_section_size, bfd_section_vma), (bfd_section_lma, bfd_section_alignment, bfd_section_flags), (bfd_section_userdata, bfd_is_com_section, bfd_is_und_section), (bfd_is_abs_section, bfd_is_ind_section, bfd_is_const_section), (discarded_section): New inline functions. * bfd-in2.h: Regenerate. gas/ * config/tc-tic6x.c (tc_gen_reloc): Correct common symbol check. ld/ * emultempl/xtensaelf.em (xtensa_get_section_deps): Comment. Use bfd_section_userdata. (xtensa_set_section_deps): Use bfd_set_section_userdata. * ldlang.c (lang_output_section_get): Use bfd_section_userdata. (sort_def_symbol): Likewise, and bfd_set_section_userdata. (init_os): Use bfd_set_section_userdata. (print_all_symbols): Use bfd_section_userdata. * ldlang.h (get_userdata): Delete.
2019-09-20x86-64: fix handling of PUSH/POP of segment registerJan Beulich4-4/+25
Commit 21df382b91 ("x86: fold SReg{2,3}") went too far: Folding 64-bit PUSH/POP templates into non-64-bit ones isn't correct, due to the different operand widths, and hence suffixes permitted. Restore the separate templates. Add tests of PUSH/POP with q suffix and %fs/%gs operands to the testsuite. While doing so also add PUSHF/POPF ones _without_ suffix.
2019-09-19[gas][news] NEWS (2.33) note new SVE2 and TME instructions for AArch64Matthew Malcomson2-0/+10
These NEWS entries had been missed when the instructions were added. gas/ChangeLog: 2019-09-19 Matthew Malcomson <matthew.malcomson@arm.com> * NEWS: Add SVE2 and TME entries.
2019-09-19bfd_section_* macrosAlan Modra73-370/+358
This large patch removes the unnecessary bfd parameter from various bfd section macros and functions. The bfd is hardly ever used and if needed for the bfd_set_section_* or bfd_rename_section functions can be found via section->owner except for the com, und, abs, and ind std_section special sections. Those sections shouldn't be modified anyway. The patch also removes various bfd_get_section_<field> macros, replacing their use with bfd_section_<field>, and adds bfd_set_section_lma. I've also fixed a minor bug in gas where compressed section renaming was done directly rather than calling bfd_rename_section. This would have broken bfd_get_section_by_name and similar functions, but that hardly mattered at such a late stage in gas processing. bfd/ * bfd-in.h (bfd_get_section_name, bfd_get_section_vma), (bfd_get_section_lma, bfd_get_section_alignment), (bfd_get_section_size, bfd_get_section_flags), (bfd_get_section_userdata): Delete. (bfd_section_name, bfd_section_size, bfd_section_vma), (bfd_section_lma, bfd_section_alignment): Lose bfd parameter. (bfd_section_flags, bfd_section_userdata): New. (bfd_is_com_section): Rename parameter. * section.c (bfd_set_section_userdata, bfd_set_section_vma), (bfd_set_section_alignment, bfd_set_section_flags, bfd_rename_section), (bfd_set_section_size): Delete bfd parameter, rename section parameter. (bfd_set_section_lma): New. * bfd-in2.h: Regenerate. * mach-o.c (bfd_mach_o_init_section_from_mach_o): Delete bfd param, update callers. * aoutx.h, * bfd.c, * coff-alpha.c, * coff-arm.c, * coff-mips.c, * coff64-rs6000.c, * coffcode.h, * coffgen.c, * cofflink.c, * compress.c, * ecoff.c, * elf-eh-frame.c, * elf-hppa.h, * elf-ifunc.c, * elf-m10200.c, * elf-m10300.c, * elf-properties.c, * elf-s390-common.c, * elf-vxworks.c, * elf.c, * elf32-arc.c, * elf32-arm.c, * elf32-avr.c, * elf32-bfin.c, * elf32-cr16.c, * elf32-cr16c.c, * elf32-cris.c, * elf32-crx.c, * elf32-csky.c, * elf32-d10v.c, * elf32-epiphany.c, * elf32-fr30.c, * elf32-frv.c, * elf32-ft32.c, * elf32-h8300.c, * elf32-hppa.c, * elf32-i386.c, * elf32-ip2k.c, * elf32-iq2000.c, * elf32-lm32.c, * elf32-m32c.c, * elf32-m32r.c, * elf32-m68hc1x.c, * elf32-m68k.c, * elf32-mcore.c, * elf32-mep.c, * elf32-metag.c, * elf32-microblaze.c, * elf32-moxie.c, * elf32-msp430.c, * elf32-mt.c, * elf32-nds32.c, * elf32-nios2.c, * elf32-or1k.c, * elf32-ppc.c, * elf32-pru.c, * elf32-rl78.c, * elf32-rx.c, * elf32-s390.c, * elf32-score.c, * elf32-score7.c, * elf32-sh.c, * elf32-spu.c, * elf32-tic6x.c, * elf32-tilepro.c, * elf32-v850.c, * elf32-vax.c, * elf32-visium.c, * elf32-xstormy16.c, * elf32-xtensa.c, * elf64-alpha.c, * elf64-bpf.c, * elf64-hppa.c, * elf64-ia64-vms.c, * elf64-mmix.c, * elf64-ppc.c, * elf64-s390.c, * elf64-sparc.c, * elf64-x86-64.c, * elflink.c, * elfnn-aarch64.c, * elfnn-ia64.c, * elfnn-riscv.c, * elfxx-aarch64.c, * elfxx-mips.c, * elfxx-sparc.c, * elfxx-tilegx.c, * elfxx-x86.c, * i386msdos.c, * linker.c, * mach-o.c, * mmo.c, * opncls.c, * pdp11.c, * pei-x86_64.c, * peicode.h, * reloc.c, * section.c, * syms.c, * vms-alpha.c, * xcofflink.c: Update throughout for bfd section macro and function changes. binutils/ * addr2line.c, * bucomm.c, * coffgrok.c, * dlltool.c, * nm.c, * objcopy.c, * objdump.c, * od-elf32_avr.c, * od-macho.c, * od-xcoff.c, * prdbg.c, * rdcoff.c, * rddbg.c, * rescoff.c, * resres.c, * size.c, * srconv.c, * strings.c, * windmc.c: Update throughout for bfd section macro and function changes. gas/ * as.c, * as.h, * dw2gencfi.c, * dwarf2dbg.c, * ecoff.c, * read.c, * stabs.c, * subsegs.c, * subsegs.h, * write.c, * config/obj-coff-seh.c, * config/obj-coff.c, * config/obj-ecoff.c, * config/obj-elf.c, * config/obj-macho.c, * config/obj-som.c, * config/tc-aarch64.c, * config/tc-alpha.c, * config/tc-arc.c, * config/tc-arm.c, * config/tc-avr.c, * config/tc-bfin.c, * config/tc-bpf.c, * config/tc-d10v.c, * config/tc-d30v.c, * config/tc-epiphany.c, * config/tc-fr30.c, * config/tc-frv.c, * config/tc-h8300.c, * config/tc-hppa.c, * config/tc-i386.c, * config/tc-ia64.c, * config/tc-ip2k.c, * config/tc-iq2000.c, * config/tc-lm32.c, * config/tc-m32c.c, * config/tc-m32r.c, * config/tc-m68hc11.c, * config/tc-mep.c, * config/tc-microblaze.c, * config/tc-mips.c, * config/tc-mmix.c, * config/tc-mn10200.c, * config/tc-mn10300.c, * config/tc-msp430.c, * config/tc-mt.c, * config/tc-nds32.c, * config/tc-or1k.c, * config/tc-ppc.c, * config/tc-pru.c, * config/tc-rl78.c, * config/tc-rx.c, * config/tc-s12z.c, * config/tc-s390.c, * config/tc-score.c, * config/tc-score7.c, * config/tc-sh.c, * config/tc-sparc.c, * config/tc-spu.c, * config/tc-tic4x.c, * config/tc-tic54x.c, * config/tc-tic6x.c, * config/tc-tilegx.c, * config/tc-tilepro.c, * config/tc-v850.c, * config/tc-visium.c, * config/tc-wasm32.c, * config/tc-xc16x.c, * config/tc-xgate.c, * config/tc-xstormy16.c, * config/tc-xtensa.c, * config/tc-z8k.c: Update throughout for bfd section macro and function changes. * write.c (compress_debug): Use bfd_rename_section. gdb/ * aarch64-linux-tdep.c, * arm-tdep.c, * auto-load.c, * coff-pe-read.c, * coffread.c, * corelow.c, * dbxread.c, * dicos-tdep.c, * dwarf2-frame.c, * dwarf2read.c, * elfread.c, * exec.c, * fbsd-tdep.c, * gcore.c, * gdb_bfd.c, * gdb_bfd.h, * hppa-tdep.c, * i386-cygwin-tdep.c, * i386-fbsd-tdep.c, * i386-linux-tdep.c, * jit.c, * linux-tdep.c, * machoread.c, * maint.c, * mdebugread.c, * minidebug.c, * mips-linux-tdep.c, * mips-sde-tdep.c, * mips-tdep.c, * mipsread.c, * nto-tdep.c, * objfiles.c, * objfiles.h, * osabi.c, * ppc-linux-tdep.c, * ppc64-tdep.c, * record-btrace.c, * record-full.c, * remote.c, * rs6000-aix-tdep.c, * rs6000-tdep.c, * s390-linux-tdep.c, * s390-tdep.c, * solib-aix.c, * solib-dsbt.c, * solib-frv.c, * solib-spu.c, * solib-svr4.c, * solib-target.c, * spu-linux-nat.c, * spu-tdep.c, * symfile-mem.c, * symfile.c, * symmisc.c, * symtab.c, * target.c, * windows-nat.c, * xcoffread.c, * cli/cli-dump.c, * compile/compile-object-load.c, * mi/mi-interp.c: Update throughout for bfd section macro and function changes. * gcore (gcore_create_callback): Use bfd_set_section_lma. * spu-tdep.c (spu_overlay_new_objfile): Likewise. gprof/ * corefile.c, * symtab.c: Update throughout for bfd section macro and function changes. ld/ * ldcref.c, * ldctor.c, * ldelf.c, * ldlang.c, * pe-dll.c, * emultempl/aarch64elf.em, * emultempl/aix.em, * emultempl/armcoff.em, * emultempl/armelf.em, * emultempl/cr16elf.em, * emultempl/cskyelf.em, * emultempl/m68hc1xelf.em, * emultempl/m68kelf.em, * emultempl/mipself.em, * emultempl/mmix-elfnmmo.em, * emultempl/mmo.em, * emultempl/msp430.em, * emultempl/nios2elf.em, * emultempl/pe.em, * emultempl/pep.em, * emultempl/ppc64elf.em, * emultempl/xtensaelf.em: Update throughout for bfd section macro and function changes. libctf/ * ctf-open-bfd.c: Update throughout for bfd section macro changes. opcodes/ * arc-ext.c: Update throughout for bfd section macro changes. sim/ * common/sim-load.c, * common/sim-utils.c, * cris/sim-if.c, * erc32/func.c, * lm32/sim-if.c, * m32c/load.c, * m32c/trace.c, * m68hc11/interp.c, * ppc/hw_htab.c, * ppc/hw_init.c, * rl78/load.c, * rl78/trace.c, * rx/gdb-if.c, * rx/load.c, * rx/trace.c: Update throughout for bfd section macro changes.
2019-09-18bfd_asymbol_* macrosAlan Modra2-2/+7
The main point of this patch is to give bfd_get_section a better name, bfd_asymbol_section. bfd/ * bfd-in.h (bfd_asymbol_section): Rename from bfd_get_section. (bfd_get_output_section): Delete. (bfd_asymbol_base): Delete. (bfd_asymbol_section, bfd_asymbol_value, bfd_asymbol_name), (bfd_asymbol_bfd, bfd_asymbol_flavour): Tidy. (bfd_set_asymbol_name): New macro. * bfd-in2.h: Regenerate. * aout-cris.c: Update throughout to use bfd_asymbol_section. * aoutx.h: Likewise. * cofflink.c: Likewise. * dwarf2.c: Likewise. * ecoff.c: Likewise. * elf.c: Likewise. * elf32-arm.c: Likewise. * elf32-mips.c: Likewise. * elf32-score.c: Likewise. * elf32-score7.c: Likewise. * elfn32-mips.c: Likewise. * elfnn-aarch64.c: Likewise. * elfxx-mips.c: Likewise. * linker.c: Likewise. * pdp11.c: Likewise. * elf64-mmix.c (mmix_elf_reloc): Expand bfd_get_output_section. binutils/ * nm.c: Update bfd_get_section to bfd_asymbol_section throughout. * objcopy.c: Likewise. * objdump.c: Likewise. * rdcoff.c: Likewise. * objcopy.c (create_new_symbol): Use bfd_set_asymbol_name. (filter_symbols): Likewise. gas/ * symbols.c (S_IS_LOCAL): Update bfd_get_section to bfd_asymbol_section. gdb/ * arm-tdep.c (arm_record_special_symbol): Update bfd_get_section to bfd_asymbol_section. ld/ * ldcref.c (check_reloc_refs): Update bfd_get_section to bfd_asymbol_section.
2019-09-18Re-generate many configure and Makefile.in filesSimon Marchi4-22/+14
I get some spurious changes when running autoconf/automake for various projects in the tree. This is likely because they were generated using distro-patched tools last time. I ran `autoreconf -f` in the various automake projects of the binutils-gdb tree, and this is the result. The tools I am using have been compiled from source, from the upstream release. bfd/ChangeLog: * Makefile.in: Re-generate. * configure: Re-generate. * doc/Makefile.in: Re-generate. binutils/ChangeLog: * Makefile.in: Re-generate. * configure: Re-generate. * doc/Makefile.in: Re-generate. gas/ChangeLog: * Makefile.in: Re-generate. * configure: Re-generate. * doc/Makefile.in: Re-generate. gold/ChangeLog: * testsuite/Makefile.in: Re-generate. gprof/ChangeLog: * Makefile.in: Re-generate. * configure: Re-generate. ld/ChangeLog: * Makefile.in: Re-generate. * configure: Re-generate. opcodes/ChangeLog: * Makefile.in: Re-generate. * configure: Re-generate.
2019-09-17RISC-V: Gate opcode tables by enum rather than string.Jim Wilson2-7/+26
Generalize opcode arch dependencies so that we can support the overlapping B extension Zb* subsets. 2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com> gas/ * config/tc-riscv.c (riscv_multi_subset_supports): Handle insn_class enum rather than subset char string. (riscv_ip): Update call to riscv_multi_subset_supports. include/ * opcode/riscv.h (riscv_insn_class): New enum. * opcode/riscv.h (struct riscv_opcode): Change subset field to insn_class field. opcodes/ * riscv-opc.c (riscv_opcodes): Change subset field to insn_class field for all instructions. (riscv_insn_types): Likewise.
2019-09-16Update version to 2.33.50 and regenerate configure scripts.Phil Blundell4-18/+36
2019-09-10Enhance the disassembler so that it will reliably determine whether a reloc ↵Nick Clifton3-0/+41
applies to the middle of the next insn. PR 24907 binutils* objdump.c (null_print): New function. (disassemble_bytes): Delete previous_octets local and replace with a test of the max_reloc_offset_into_insn field of the bfd_arch_info structure. If a reloc is a potential match for the next insn, then perform a dummy disassembly in order to calculate its real length. bfd * archures.c (bfd_arch_info_type): Add max_reloc_offset_into_insn field. (bfd_default_arch_struct): Initialise the new field. * bfd-in2.h: Regenerate. * cpu-aarch64.c: Initialise the new field. * cpu-alpha.c: Likewise. * cpu-arc.c: Likewise. * cpu-arm.c: Likewise. * cpu-avr.c: Likewise. * cpu-bfin.c: Likewise. * cpu-bpf.c: Likewise. * cpu-cr16.c: Likewise. * cpu-cr16c.c: Likewise. * cpu-cris.c: Likewise. * cpu-crx.c: Likewise. * cpu-csky.c: Likewise. * cpu-d10v.c: Likewise. * cpu-d30v.c: Likewise. * cpu-dlx.c: Likewise. * cpu-epiphany.c: Likewise. * cpu-fr30.c: Likewise. * cpu-frv.c: Likewise. * cpu-ft32.c: Likewise. * cpu-h8300.c: Likewise. * cpu-hppa.c: Likewise. * cpu-i386.c: Likewise. * cpu-ia64.c: Likewise. * cpu-iamcu.c: Likewise. * cpu-ip2k.c: Likewise. * cpu-iq2000.c: Likewise. * cpu-k1om.c: Likewise. * cpu-l1om.c: Likewise. * cpu-lm32.c: Likewise. * cpu-m10200.c: Likewise. * cpu-m10300.c: Likewise. * cpu-m32c.c: Likewise. * cpu-m32r.c: Likewise. * cpu-m68hc11.c: Likewise. * cpu-m68hc12.c: Likewise. * cpu-m68k.c: Likewise. * cpu-m9s12x.c: Likewise. * cpu-m9s12xg.c: Likewise. * cpu-mcore.c: Likewise. * cpu-mep.c: Likewise. * cpu-metag.c: Likewise. * cpu-microblaze.c: Likewise. * cpu-mips.c: Likewise. * cpu-mmix.c: Likewise. * cpu-moxie.c: Likewise. * cpu-msp430.c: Likewise. * cpu-mt.c: Likewise. * cpu-nds32.c: Likewise. * cpu-nfp.c: Likewise. * cpu-nios2.c: Likewise. * cpu-ns32k.c: Likewise. * cpu-or1k.c: Likewise. * cpu-pdp11.c: Likewise. * cpu-pj.c: Likewise. * cpu-plugin.c: Likewise. * cpu-powerpc.c: Likewise. * cpu-pru.c: Likewise. * cpu-riscv.c: Likewise. * cpu-rl78.c: Likewise. * cpu-rs6000.c: Likewise. * cpu-rx.c: Likewise. * cpu-s12z.c: Likewise. * cpu-s390.c: Likewise. * cpu-score.c: Likewise. * cpu-sh.c: Likewise. * cpu-sparc.c: Likewise. * cpu-spu.c: Likewise. * cpu-tic30.c: Likewise. * cpu-tic4x.c: Likewise. * cpu-tic54x.c: Likewise. * cpu-tic6x.c: Likewise. * cpu-tic80.c: Likewise. * cpu-tilegx.c: Likewise. * cpu-tilepro.c: Likewise. * cpu-v850.c: Likewise. * cpu-v850_rh850.c: Likewise. * cpu-vax.c: Likewise. * cpu-visium.c: Likewise. * cpu-wasm32.c: Likewise. * cpu-xc16x.c: Likewise. * cpu-xgate.c: Likewise. * cpu-xstormy16.c: Likewise. * cpu-xtensa.c: Likewise. * cpu-z80.c: Likewise. * cpu-z8k.c: Likewise. gas * testsuite/gas/arm/pr24907.s: New test. * testsuite/gas/arm/pr24907.d: Expected disassembly.
2019-09-10[PATCH][ARM][GAS]: Support to MVE VCTP instruction.Srinath Parvathaneni6-0/+177
This patch adds support for MVE VCTP instruction in assembler. gas ChangeLog: 2019-09-10 Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/tc-arm.c (M_MNEM_vctp): Add new Mnemonic. (do_mve_vctp): Add function to encode VCTP instruction. * testsuite/gas/arm/mve-vctp-bad.d: New test. * testsuite/gas/arm/mve-vctp-bad.l: Likewise. * testsuite/gas/arm/mve-vctp-bad.s: Likewise. * testsuite/gas/arm/mve-vctp.d: Likewise. * testsuite/gas/arm/mve-vctp.s: Likewise.
2019-09-09Add markers for 2.33 branch to NEWS and ChangeLog files.Phil Blundell2-0/+6
2019-09-05PowerPC warning on symbol+offset@gotAlan Modra2-3/+8
* config/tc-ppc.c (ppc_elf_suffix): Display the relocation operator on GOT reloc warnings/errors.
2019-08-30[PATCH][ARM][GAS]: Assembler support to interpret MVE VMOV instruction ↵Srinath Parvathaneni3-1/+86
correctly. This patch make changes to the assembler to encode MVE VMOV instruction "a" same as "b". a: VMOV<c><q> <Dd>, <Dm> b: VMOV<c><q>.F64 <Dd>, <Dm> gas/ChangeLog: 2019-08-30 Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/tc-arm.c (do_neon_mov): Modify "if" statement. * testsuite/gas/arm/mve-vmov-bad-3.d: New test. * testsuite/gas/arm/mve-vmov-bad-3.l: Likewise. * testsuite/gas/arm/mve-vmov-bad-3.s: Likewise.
2019-08-27Add support for the MVE VMOV instruction to the ARM assembler. This ↵Srinath Parvathaneni5-202/+243
instruction copies the value of one vector register to another vector register. The patch also modifies the decoding of VORR instruction which is effecting decoding of VMOV instruction. gas * config/tc-arm.c (parse_neon_mov): Add check to accept vector register to both the arguments in VMOV instruction. * testsuite/gas/arm/mve-vmov-1.d: Modify. * testsuite/gas/arm/mve-vmov-1.s: Likewise. * testsuite/gas/arm/mve-vorr.d: Likewise. opcodes * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC. (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC. (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
2019-08-25RISC-V: Improve li expansion for better code density.Kito Cheng5-5/+108
li is a pseudo instruction in RISC-V, it might expand to more than one instructions if the immediate value can't fit addi or lui, but the assembler will always using 4-byte instructions during expansion. For example: li a0, 0x12345001 will expand into 12345537 lui a0,0x12345 00150513 addi a0,a0,1 but addi could be compress into 0505 addi a0,a0,1 It because load_const use macro_build to emit instructions, and macro_build call append_insn, and expect it will compress it if possible, but the fact is append_insn never compress anything, So this patch redirect the li expansion flow to normal instruction emission flow via md_assemble, added md_assemblef as an wrapper for that for easier emit instruction with printf-style argument to build instruction. gas/ChangeLog: * tc-riscv.c (md_assemblef): New. (load_const) Use md_assemblef instead of macro_build to emit instructions. * testsuite/gas/riscv/li32.d: New. * testsuite/gas/riscv/li32.s: Ditto. * testsuite/gas/riscv/li64.d: Ditto. * testsuite/gas/riscv/li64.s: Ditto.
2019-08-23Updated Swedish translation for the gas sub-directory.Nick Clifton2-49/+26
2019-08-23 Nick Clifton <nickc@redhat.com> * po/sv.po: Updated Swedish translation.
2019-08-22Arm: Add support for missing CPUsDennis Zhang6-0/+39
This patch adds support for following CPUs: Cortex-M35P, Cortex-A77, Cortex-A76AE. Related specifications can be found at https://developer.arm.com/ip-products/processors. gas/ChangeLog: * config/tc-arm.c: New entries for Cortex-M35P, Cortex-A77, and Cortex-A76AE. * doc/c-arm.texi: Document new processors. * testsuite/gas/arm/cpu-cortex-a76ae.d: New test. * testsuite/gas/arm/cpu-cortex-a77.d: New test. * testsuite/gas/arm/cpu-cortex-m35p.d: New test. bfd/ChangeLog: * cpu-arm.c: New entries for Cortex-M35P, Cortex-A77, Cortex-A76AE.
2019-08-22Fix the assembler's floating point number parser so that it can correctly ↵Bosco Garc?a5-7/+49
handle numbers encoded as a leading decimal point, followed by zeroes, followed by a non-zero sequence. * atof-generic.c (atof_generic): Do not ignore leading zeros if they appear after a decimal point. * testsuite/gas/all/float.s: Extend test to include a number with a leading decimal point followed by several zeroes. * testsuite/gas/i386/fp.s: Likewise. * testsuite/gas/i386/fp.d: Update expected output.
2019-08-22Implement a float16 directive for assembling 16 bit IEEE 754 floating point ↵Barnaby Wilks7-5/+70
numbers for the AArch64 assembler. The syntax of the directive is: .float16 <0-n decimal numbers> e.g. .float16 0.5 .float16 10.2, NaN, 452.09 The floats will always be encoded using the binary16 format as described in the IEEE 754-2008 standard. There is no need to support Arm's alternative half-precision format since AArch64 only supports the IEEE format. gas * config/tc-aarch64.c: Add float16 directive and add "Hh" to acceptable float characters. * doc/c-aarch64.texi: Documentation for float16 directive. * testsuite/gas/aarch64/float16-be.d: New test. * testsuite/gas/aarch64/float16-le.d: New test. * testsuite/gas/aarch64/float16.s: New test. * NEWS: Add NEWS entry.
2019-08-22[AArch64][gas] Update MTE system register encodingsKyrylo Tkachov2-10/+15
The MTE specification adjusted the encoding of the TFSRE0_EL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12 system registers. This patch brings binutils up to date. The references for the encodings are at: https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsre0_el1 (also contains TFSR_EL12 description) https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsr_el1 https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsr_el2 https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsr_el3 Tested check-gas for aarch64-none-elf. opcodes/ * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1, tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12. (aarch64_sys_reg_supported_p): Update checks for the above. gas/ * testsuite/gas/aarch64/sysreg-4.d: Update expected disassembly for tfsre0_el1, tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12 system registers.
2019-08-20Remove test files for a different patch accidentally committed with patch ↵Nick Clifton2-35/+0
for ARM CPU additions.
2019-08-20Adds support for following CPUs to the ARM and Aarch64 assemblers: ↵Dennis Zhang12-0/+112
Cortex-A77, Cortex-A76AE, Cortex-A34, Cortex-A65, and Cortex-A65AE. Related specifications can be found at https://developer.arm.com/ip-products/processors. gas * NEWS: Mention the Arm and AArch64 new processors. * config/tc-aarch64.c: New entries for Cortex-A34, Cortex-A65, Cortex-A77, cortex-A65AE, and Cortex-A76AE. * doc/c-aarch64.texi: Document new CPUs. * testsuite/gas/aarch64/cpu-cortex-a34.d: New test. * testsuite/gas/aarch64/cpu-cortex-a65.d: New test. * testsuite/gas/aarch64/cpu-cortex-a65ae.d: New test. * testsuite/gas/aarch64/cpu-cortex-a76ae.d: New test. * testsuite/gas/aarch64/cpu-cortex-a77.d: New test. * testsuite/gas/aarch64/nop-asm.s: New test. bfd * cpu-aarch64.c: New entries for Cortex-A34, Cortex-A65, Cortex-A77, cortex-A65AE, and Cortex-A76AE.
2019-08-19MIPS/gas: Fix misaligned address errors to disregard ISA mode bitFaraz Shahbazker2-5/+32
gas/ * config/tc-mips.c (fix_bad_misaligned_address): New function. (fix_validate_branch): Call fix_bad_misaligned address_to calculate the target address. (md_apply_fix): Likewise. (md_convert_frag): Update misaligned address calculation to disregard ISA mode bit.
2019-08-19MIPS/gas: Retain ISA mode bit for labels with .insn annotationFaraz Shahbazker5-3/+45
gas/ * config/tc-mips.c (mips_move_labels): Retain ISA mode bit when moving labels in text segments. (mips_align): Indicate text mode when aligning labels in text segments. * gas/testsuite/gas/mips/insn-isa-mode.d: New test. * gas/testsuite/gas/mips/insn-isa-mode.s: New test source. * gas/testsuite/gas/mips/mips.exp: Run the new test.
2019-08-19Float16: Fix test failures for non ELF targetsBarnaby Wilks2-27/+26
The tests were failing due to md_atof trying to do word-wise endian switching on the float16 (for little-endian targets sometimes multi word values have their word order changed). However since a float16 is only 1 word wide, it would end up writing incorrect data, as you cannot switch the word order of just one word. * config/tc-arm.c (md_atof): Add precision check. Formatting.
2019-08-15Updatesd Swdish translation for the gas sub-directory.Nick Clifton2-872/+466
* po/sv.po: Updated Swedish translation.
2019-08-12Modify the ARM encoding and decoding of SQRSHRL and UQRSHLL MVE instructions.Srinath Parvathaneni6-8/+76
This is a change to the first published specifications [1][a] but since there is no hardware out there that uses the old instructions we do not want to support the old variant. This changes are done based on the latest published specifications [1][b]. [1] https://developer.arm.com/architectures/cpu-architecture/m-profile/docs/ddi0553/latest/armv81-m-architecture-reference-manual [a] version bf [b] version bh gas * config/tc-arm.c (enum operand_parse_code): Add the entry OP_I48_I64. (po_imm1_or_imm2_or_fail): Marco to check the immediate is either of 48 or 64. (parse_operands): Add case OP_I48_I64. (do_mve_scalar_shift1): Add function to encode the MVE shift instructions with 4 arguments. * testsuite/gas/arm/mve-shift-bad.l: Modify. * testsuite/gas/arm/mve-shift-bad.s: Likewise. * testsuite/gas/arm/mve-shift.d: Likewise. * testsuite/gas/arm/mve-shift.s: Likewise. opcodes * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for cases MVE_SQRSHRL and MVE_UQRSHLL. (print_insn_mve): Add case for specifier 'k' to check specific bit of the instruction.
2019-08-12Add generic and ARM specific support for half-precision IEEE 754 floating ↵Barnaby Wilks20-8/+324
point numbers to the assembler. Half precision floating point numbers will be encoded using the IEEE 754 half precision floating point format - 16 bits in total, 1 for sign, 5 for exponent and 10 bits of mantissa. This patch implements the float16 directive for both the IEEE 754 format and the Arm alternative format for the Arm backend. The syntax of the directive is: .float16 <0-n decimal numbers> e.g. .float16 12.0 .float16 0.23, 433.1, 0.06 The Arm alternative format is almost identical to the IEEE 754 format, except that it doesn't encode for NaNs or Infinity (instead an exponent of 0x1F represents a normalized number in the range 65536 to 131008). The alternative format is documented in the reference manual: https://static.docs.arm.com/ddi0487/db/DDI0487D_b_armv8_arm.pdf?_ga=2.72318806.49764181.1561632697-999473562.1560847439 Which format is used is controlled by the .float16_format <format> directive, where if <format> = ieee, then use the IEEE 754 half-precision format else if <format> = alternative, then use the Arm alternative format Or the format can be set on the command line via the -mfp16-format option that has a similar syntax. -mfp16-format=<ieee|alternative>. This also fixes the format and it cannot be changed by any directives. Once the format has been set (either by the command line option or a directive) it cannot be changed, and any attempts to change it (i.e. with the float16_format directive) will result in a warning and the line being ignored. For ELF targets the appropriate EABI attribute will be written out at the end of assembling if the format has been explicitly specified. If no format has been explicitly specified then no EABI attributes will be written. If the format is not explicitly specified then any float16 directives are encoding using the IEEE 754-2008 format by default until the format is fixed or changed with the float16_format directive. gas * config/tc-arm.c (enum fp_16bit_format): Add enum to represent the 2 float16 encodings. (md_atof): Set precision for float16 type. (arm_is_largest_exponent_ok): Check for whether to encode with the IEEE or alternative format. (set_fp16_format): Parse a float16_format directive. (arm_parse_fp16_opt): Parse the fp16-format command line option. (aeabi_set_public_attributes): For ELF encode the FP16 format EABI attribute. * config/tc-arm.h (TC_LARGEST_EXPONENT_IS_NORMAL): Macro that expands to arm_is_largest_exponent_ok. (arm_is_largest_exponent_ok): Add prototype for arm_is_largest_exponent_ok function. * doc/c-arm.texi: Add documentation for .float16, .float16_format and -mfp16-format= * testsuite/gas/arm/float16-bad.d: New test. * testsuite/gas/arm/float16-bad.l: New test. * testsuite/gas/arm/float16-bad.s: New test. * testsuite/gas/arm/float16-be.d: New test. * testsuite/gas/arm/float16-format-bad.d: New test. * testsuite/gas/arm/float16-format-bad.l: New test. * testsuite/gas/arm/float16-format-bad.s: New test. * testsuite/gas/arm/float16-format-opt-bad.d: New test. * testsuite/gas/arm/float16-format-opt-bad.l: New test. * testsuite/gas/arm/float16-le.d: New test. * testsuite/gas/arm/float16.s: New test. * testsuite/gas/arm/float16-eabi-alternative-format.d: New test. * testsuite/gas/arm/float16-eabi-ieee-format.d: New test. * testsuite/gas/arm/float16-eabi-no-format.d: New test. * testsuite/gas/arm/float16-eabi.s: New test. * config/atof-ieee.c (H_PRECISION): Macro for precision of float16 type. (atof_ieee): Set precision and exponent bits for encoding float16 types. (gen_to_words): NaN and Infinity encoding for float16. (ieee_md_atof): Set precision for encoding float16 type.
2019-08-12PR24851, gas/testsuite/gas/epiphany/badrelax.s failure with MALLOC_PERTURB_=1Alan Modra2-17/+28
PR 24851 * config/tc-epiphany.c (md_estimate_size_before_relax): Clear extra opcode bytes when changing from a 2-byte to a 4-byte insn.
2019-08-09x86-64: generalize SIMD test expectationsJan Beulich7-927/+212
In order to be able to add/remove insns to/from the middle of these tests, generalize the patterns for the symbol reference comments of RIP- relative operands.
2019-08-08Change the output of readelf's note display so that the "Data size" column ↵Nick Clifton5-4/+13
header is left justified. PR 24887 binutils* readelf.c (process_notes_at): Left justify the "Data size" column heading. * testsuite/binutils-all/i386/empty.d: Adjust for new output format. * testsuite/binutils-all/i386/ibt.d: Likewise. * testsuite/binutils-all/i386/pr21231a.d: Likewise. * testsuite/binutils-all/i386/pr21231b.d: Likewise. * testsuite/binutils-all/i386/shstk.d: Likewise. * testsuite/binutils-all/note-2-32.d: Likewise. * testsuite/binutils-all/note-2-64.d: Likewise. * testsuite/binutils-all/x86-64/empty-x32.d: Likewise. * testsuite/binutils-all/x86-64/empty.d: Likewise. * testsuite/binutils-all/x86-64/ibt-x32.d: Likewise. * testsuite/binutils-all/x86-64/ibt.d: Likewise. * testsuite/binutils-all/x86-64/pr21231a.d: Likewise. * testsuite/binutils-all/x86-64/pr21231b.d: Likewise. * testsuite/binutils-all/x86-64/pr23494a-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494a.d: Likewise. * testsuite/binutils-all/x86-64/pr23494c-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494c.d: Likewise. * testsuite/binutils-all/x86-64/pr23494d-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494d.d: Likewise. * testsuite/binutils-all/x86-64/pr23494e-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494e.d: Likewise. * testsuite/binutils-all/x86-64/shstk-x32.d: Likewise. * testsuite/binutils-all/x86-64/shstk.d: Likewise. ld * testsuite/ld-aarch64/bti-plt-2.d: Adjust for new output format from readelf. * testsuite/ld-aarch64/bti-plt-4.d: Likewise. * testsuite/ld-aarch64/bti-plt-6.d: Likewise. * testsuite/ld-aarch64/bti-plt-7.d: Likewise. * testsuite/ld-aarch64/bti-warn.d: Likewise. * testsuite/ld-aarch64/property-bti-pac1.d: Likewise. * testsuite/ld-aarch64/property-bti-pac2.d: Likewise. * testsuite/ld-aarch64/property-bti-pac3.d: Likewise. * testsuite/ld-elf/x86-feature-1a.rd: Likewise. * testsuite/ld-elf/x86-feature-1b.rd: Likewise. * testsuite/ld-elf/x86-feature-1c.rd: Likewise. * testsuite/ld-elf/x86-feature-1d.rd: Likewise. * testsuite/ld-elf/x86-feature-1e.rd: Likewise. * testsuite/ld-i386/ibt-plt-2d.d: Likewise. * testsuite/ld-i386/ibt-plt-3d.d: Likewise. * testsuite/ld-i386/pr23372a.d: Likewise. * testsuite/ld-i386/pr23372c.d: Likewise. * testsuite/ld-i386/pr23486a.d: Likewise. * testsuite/ld-i386/pr23486b.d: Likewise. * testsuite/ld-i386/pr23486c.d: Likewise. * testsuite/ld-i386/pr23486d.d: Likewise. * testsuite/ld-i386/pr24322a.d: Likewise. * testsuite/ld-i386/pr24322b.d: Likewise. * testsuite/ld-i386/property-x86-3.d: Likewise. * testsuite/ld-i386/property-x86-4a.d: Likewise. * testsuite/ld-i386/property-x86-5.d: Likewise. * testsuite/ld-i386/property-x86-cet1.d: Likewise. * testsuite/ld-i386/property-x86-cet2a.d: Likewise. * testsuite/ld-i386/property-x86-cet5a.d: Likewise. * testsuite/ld-i386/property-x86-cet5b.d: Likewise. * testsuite/ld-i386/property-x86-ibt1a.d: Likewise. * testsuite/ld-i386/property-x86-ibt1b.d: Likewise. * testsuite/ld-i386/property-x86-ibt2.d: Likewise. * testsuite/ld-i386/property-x86-ibt3a.d: Likewise. * testsuite/ld-i386/property-x86-ibt3b.d: Likewise. * testsuite/ld-i386/property-x86-ibt4.d: Likewise. * testsuite/ld-i386/property-x86-ibt5.d: Likewise. * testsuite/ld-i386/property-x86-shstk1a.d: Likewise. * testsuite/ld-i386/property-x86-shstk1b.d: Likewise. * testsuite/ld-i386/property-x86-shstk2.d: Likewise. * testsuite/ld-i386/property-x86-shstk3a.d: Likewise. * testsuite/ld-i386/property-x86-shstk3b.d: Likewise. * testsuite/ld-i386/property-x86-shstk4.d: Likewise. * testsuite/ld-i386/property-x86-shstk5.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2d-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2d.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3d-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3d.d: Likewise. * testsuite/ld-x86-64/pr23372a-x32.d: Likewise. * testsuite/ld-x86-64/pr23372a.d: Likewise. * testsuite/ld-x86-64/pr23372c-x32.d: Likewise. * testsuite/ld-x86-64/pr23372c.d: Likewise. * testsuite/ld-x86-64/pr23486a-x32.d: Likewise. * testsuite/ld-x86-64/pr23486a.d: Likewise. * testsuite/ld-x86-64/pr23486b-x32.d: Likewise. * testsuite/ld-x86-64/pr23486b.d: Likewise. * testsuite/ld-x86-64/pr23486c-x32.d: Likewise. * testsuite/ld-x86-64/pr23486c.d: Likewise. * testsuite/ld-x86-64/pr23486d-x32.d: Likewise. * testsuite/ld-x86-64/pr23486d.d: Likewise. * testsuite/ld-x86-64/pr24322a-x32.d: Likewise. * testsuite/ld-x86-64/pr24322a.d: Likewise. * testsuite/ld-x86-64/pr24322b-x32.d: Likewise. * testsuite/ld-x86-64/pr24322b.d: Likewise. * testsuite/ld-x86-64/pr24458a-x32.d: Likewise. * testsuite/ld-x86-64/pr24458a.d: Likewise. * testsuite/ld-x86-64/pr24458b-x32.d: Likewise. * testsuite/ld-x86-64/pr24458b.d: Likewise. * testsuite/ld-x86-64/pr24458c-x32.d: Likewise. * testsuite/ld-x86-64/pr24458c.d: Likewise. * testsuite/ld-x86-64/property-1.r: Likewise. * testsuite/ld-x86-64/property-1a.r: Likewise. * testsuite/ld-x86-64/property-2.r: Likewise. * testsuite/ld-x86-64/property-2a.r: Likewise. * testsuite/ld-x86-64/property-3.r: Likewise. * testsuite/ld-x86-64/property-3a.r: Likewise. * testsuite/ld-x86-64/property-4.r: Likewise. * testsuite/ld-x86-64/property-4a.r: Likewise. * testsuite/ld-x86-64/property-5.r: Likewise. * testsuite/ld-x86-64/property-5a.r: Likewise. * testsuite/ld-x86-64/property-6.r: Likewise. * testsuite/ld-x86-64/property-7.r: Likewise. * testsuite/ld-x86-64/property-7a.r: Likewise. * testsuite/ld-x86-64/property-x86-3-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-3.d: Likewise. * testsuite/ld-x86-64/property-x86-4a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-4a.d: Likewise. * testsuite/ld-x86-64/property-x86-5-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-5.d: Likewise. * testsuite/ld-x86-64/property-x86-cet1-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet1.d: Likewise. * testsuite/ld-x86-64/property-x86-cet2a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet2a.d: Likewise. * testsuite/ld-x86-64/property-x86-cet5a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet5a.d: Likewise. * testsuite/ld-x86-64/property-x86-cet5b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet5b.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1a.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1b.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt2-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt2.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3a.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3b.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt4-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt4.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt5-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt5.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk1a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk1a.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk1b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk1b.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk2-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk2.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3a.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3b.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk4-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk4.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk5-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk5.d: Likewise. gas * testsuite/gas/i386/property-1.d: Adjust for new output format from readelf. * testsuite/gas/i386/property-2.d: Likewise. * testsuite/gas/i386/x86-64-property-1.d: Likewise. * testsuite/gas/i386/x86-64-property-2.d: Likewise.
2019-08-08Update the handling of shift rotate and load/store multiple instructions in ↵Yoshinori Sato1-4/+4
the H8300 assembler. incldue * opcode/h8300.h (EXPAND_UNOP_EXTENDED_B): Add MODEL. (EXPAND_UNOP_EXTENDED_W): Likewise. (EXPAND_UNOP_EXTENDED_L): Likewise. (struct h8_opcode h8_opcodes): Likewise. (struct h8_opcode h8_opcodes): tas / ldm / stm supported H8S or later.
2019-08-08Move the h8300 assembler's MOVFPE and MOVTPE tests to the correct location.Yoshinori Sato5-50/+56
* gas/testsuite/gas/h8300/h8300.exp: Fix movfpe and movtpe tests. * gas/testsuite/gas/h8300/misc.s: Likewise. * gas/testsuite/gas/h8300/misch.s: Likewise. * gas/testsuite/gas/h8300/miscs.s: Likewise.
2019-08-05Removes support in the ARM assembler for the unsigned variants of the ↵Barnaby Wilks12-2712/+55
VQ(R)DMLAH and VQ(R)DMLASH MVE instructions. Previously GAS would accept .u32, .u16 and .u8 suffixes to the VQ(R)DMLAH and VQ(R)DMLASH instructions, however the Armv8.1-M Mainline specification states that these functions only have signed variations (.s32, .s16 and .s8 suffixes). This is documented here: https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf?_ga=2.143079093.1892401233.1563295591-999473562.1560847439#page=1183 gas * config/tc-arm.c (do_mve_vqdmlah): Use N_S_32 macro. (do_neon_qrdmlah): Use N_S_32 macro. * testsuite/gas/arm/mve-vqdmlah-bad.d: New test. * testsuite/gas/arm/mve-vqdmlah-bad.l: New test. * testsuite/gas/arm/mve-vqdmlah-bad.s: New test. * testsuite/gas/arm/mve-vqdmlah.d: Remove unsigned instruction tests. * testsuite/gas/arm/mve-vqdmlah.s: Remove unsigned instruction tests. * testsuite/gas/arm/mve-vqdmlash-bad.d: New test. * testsuite/gas/arm/mve-vqdmlash-bad.l: New test. * testsuite/gas/arm/mve-vqdmlash-bad.s: New test. * testsuite/gas/arm/mve-vqdmlash.d: Remove unsigned instruction tests. * testsuite/gas/arm/mve-vqdmlash.s: Remove unsigned instruction tests. opcodes * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH instructions.
2019-07-30RISC-V: Fix minor issues with FP csr instructions.Jim Wilson5-1/+71
Mel Chen <mel.chen@sifive.com> gas/ * testsuite/gas/riscv/alias-csr.s: Add testcase for CSR-access alias instructions. * testsuite/gas/riscv/no-aliases-csr.d: Run testcase alias-csr.s with -Mno-aliases. * testsuite/gas/riscv/alias-csr.d: Run testcase alias-csr.s. * testsuite/gas/riscv/priv-reg.d: Update. opcodes/ * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm, fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions. * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr, fscsr.
2019-07-24Update the Swedish translation for the gas sub-directory.Nick Clifton2-4191/+5083
2019-07-24[ARC] Update disassembler opcode selectionClaudiu Zissulescu2-1/+5
New instruction are added, and some of them are overlapping. Update disassembler to correctly recognize them. Introduce nps400 option. opcodes/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes, and MPY class instructions. (parse_option): Add nps400 option. (print_arc_disassembler_options): Add nps400 info. gas/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/nps400-6.d: Update test.
2019-07-24Complain about mbind, ifunc, and unique in final_writeAlan Modra4-2/+11
It's not as good as complaining in gas/config/obj-elf.c since you lose any reference to the source file. bfd/ * elf-bfd.h (struct elf_backend_data): Return bfd_boolean from elf_backend_final_write_processing, don't pass linker arg. (_bfd_elf_final_write_processing): Update prototype. * elf.c (_bfd_elf_write_object_contents): Adjust call. (_bfd_elf_final_write_processing): Return error on incompatible OSABI and has_gnu_osabi. Remove linker arg. * elf-nacl.h (nacl_final_write_processing): Update prototype. * elf-vxworks.h (elf_vxworks_final_write_processing): Likewise. * elfxx-mips.h (_bfd_mips_final_write_processing): Likewise. (_bfd_mips_elf_final_write_processing): Likewise. * elf-hppa.h (elf_hppa_final_write_processing): Return status and remove linker arg. * elf-m10300.c (_bfd_mn10300_elf_final_write_processing): Likewise. * elf-nacl.c (nacl_final_write_processing): Likewise. * elf-vxworks.c (elf_vxworks_final_write_processing): Likewise. * elf32-arc.c (arc_elf_final_write_processing): Likewise. * elf32-arm.c (arm_final_write_processing): Likewise. (elf32_arm_final_write_processing): Likewise. (elf32_arm_nacl_final_write_processing): Likewise. (elf32_arm_vxworks_final_write_processing): Likewise. * elf32-avr.c (bfd_elf_avr_final_write_processing): Likewise. * elf32-bfin.c (elf32_bfin_final_write_processing): Likewise. * elf32-cr16.c (_bfd_cr16_elf_final_write_processing): Likewise. * elf32-cris.c (cris_elf_final_write_processing): Likewise. * elf32-h8300.c (elf32_h8_final_write_processing): Likewise. * elf32-lm32.c (lm32_elf_final_write_processing): Likewise. * elf32-m32r.c (m32r_elf_final_write_processing): Likewise. * elf32-m68k.c (elf_m68k_final_write_processing): Likewise. * elf32-mips.c (mips_vxworks_final_write_processing): Likewise. * elf32-msp430.c (bfd_elf_msp430_final_write_processing): Likewise. * elf32-nds32.c (nds32_elf_final_write_processing): Likewise. * elf32-or1k.c (or1k_elf_final_write_processing): Likewise. * elf32-pj.c (pj_elf_final_write_processing): Likewise. * elf32-ppc.c (ppc_final_write_processing): Likewise. (ppc_elf_final_write_processing): Likewise. (ppc_elf_vxworks_final_write_processing): Likewise. * elf32-sparc.c (sparc_final_write_processing): Likewise. (elf32_sparc_final_write_processing): Likewise. (elf32_sparc_vxworks_final_write_processing): Likewise. * elf32-v850.c (v850_elf_final_write_processing): Likewise. * elf32-xc16x.c (elf32_xc16x_final_write_processing): Likewise. * elf32-xtensa.c (elf_xtensa_final_write_processing): Likewise. * elf64-ia64-vms.c (elf64_vms_final_write_processing): Likewise. * elfnn-ia64.c (elfNN_ia64_final_write_processing): Likewise. * elfxx-mips.c (_bfd_mips_final_write_processing): Likewise. (_bfd_mips_elf_final_write_processing): Likewise. gas/ * config/obj-elf.c (obj_elf_section, obj_elf_type): Set has_gnu_osabi. * testsuite/gas/elf/section12a.d: Update xfails. * testsuite/gas/elf/section12b.d: Likewise.
2019-07-24Define ELF_OSABI for visiumAlan Modra4-5/+16
and update expected results for gas mbind tests. bfd/ * elf32-visium.c (visium_elf_post_process_headers): Don't set EI_OSABI header byte here. (ELF_OSABI): Define. gas/ * testsuite/gas/elf/section12a.d: xfail visium and cloudabi. * testsuite/gas/elf/section12b.d: Likewise. * testsuite/gas/elf/section13.d: Likewise.
2019-07-23[AArch64] Add support for GMID_EL1 register for +memtagKyrylo Tkachov4-0/+9
We're missing support for the GMID_EL1 system register from the Memory Tagging Extension in binutils. This is specified at: https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/gmid_el1 This simple patch adds the support for this read-only register. Tested make check on gas.
2019-07-23SHF_GNU_MBIND requires ELFOSABI_GNUAlan Modra6-29/+65
When SHF_GNU_MBIND was added in the SHF_LOOS to SHF_HIOS range, it should have required ELFOSABI_GNU since these flags are already in use by other OSes. HPUX SHF_HP_TLS in fact has the same value. That means no place in binutils should test SHF_GNU_MBIND without first checking OSABI, and SHF_GNU_MBIND should not be set without also setting OSABI. At least, that's the ideal, but the patch accepts SHF_GNU_MBIND on ELFOSABI_NONE object files since gas didn't always set OSABI. However, to reinforce the fact that SHF_GNU_MBIND isn't proper without a non-zero OSABI, readelf will display the flag as LOOS+0 if OSABI isn't set. The clash with SHF_HP_TLS means that hppa64-linux either has that flag on .tbss sections or supports GNU_MBIND, not both. (hppa64-linux users, if there are any, may have noticed that GNU ld since 2017 mysteriously aligned their .tbss sections to a 4k boundary. That was one consequence of SHF_HP_TLS being blindly interpreted as SHF_GNU_MBIND.) Since it seems that binutils, gdb, gcc, glibc, and the linux kernel don't care about SHF_HP_TLS I took that flag out of .tbss for hppa64-linux. bfd/ * elf-bfd.h (enum elf_gnu_osabi): Add elf_gnu_osabi_mbind. * elf.c (_bfd_elf_make_section_from_shdr): Set elf_gnu_osabi_mbind. (get_program_header_size): Formatting. Only test SH_GNU_MBIND when elf_gnu_osabi_mbind is set. (_bfd_elf_map_sections_to_segments): Likewise. (_bfd_elf_init_private_section_data): Likewise. (_bfd_elf_final_write_processing): Update comment. * elf64-hppa.c (elf64_hppa_special_sections): Move .tbss entry. (elf_backend_special_sections): Define without .tbss for linux. binutils/ * readelf.c (get_parisc_segment_type): Split off hpux entries.. (get_ia64_segment_type): ..and these.. (get_hpux_segment_type): ..to here. (get_segment_type): Condition GNU_MBIND on osabi. Use get_hpux_segment_type. (get_symbol_binding): Do not print UNIQUE for ELFOSABI_NONE. (get_symbol_type): Do not print IFUNC for ELFOSABI_NONE. gas/ * config/obj-elf.c (obj_elf_change_section): Don't emit a fatal error for non-SHF_ALLOC SHF_GNU_MBIND here. (obj_elf_parse_section_letters): Return SHF_GNU_MBIND in new gnu_attr param. (obj_elf_section): Adjust obj_elf_parse_section_letters call. Formatting. Set SHF_GNU_MBIND and elf_osabi from gnu_attr. Emit normal error for non-SHF_ALLOC SHF_GNU_MBIND and wrong osabi. (obj_elf_type): Set elf_osabi for ifunc. * testsuite/gas/elf/section12a.d: xfail msp430 and hpux. * testsuite/gas/elf/section12b.d: Likewise. * testsuite/gas/elf/section13.d: Likewise. * testsuite/gas/elf/section13.l: Adjust expected error. ld/ * emultempl/elf32.em (gld${EMULATION_NAME}_place_orphan): Condition SHF_GNU_MBIND on osabi. Set output elf_gnu_osabi_mbind.
2019-07-23gas "mbind sections" testAlan Modra2-2/+4
Doesn't fail on rx-elf * testsuite/gas/elf/section12a.d: Don't skip for rx.
2019-07-22This patch addresses the change in the June Armv8.1-M Mainline ↵Barnaby Wilks10-137/+136
specification, that marks certain MVE instructions as no longer UNPREDICTABLE when a source operand is the same as a destination operand for a 32-bit element size. The instructions that this change apply to are: VQDMLADH, VQRDMLADH, VQDMLSDH, VQRDMLSDH The updated documentation is here: https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf Fixed this by removing the check for this warning from GAS as well as opcodes. Added testcases to test that the warning is not generated for the instructions that have a 32-bit element size and the same source and destination operand. Also fixed tests that would previously check for this warning. gas * config/tc-arm.c (do_mve_vqdmladh): Remove check for UNPREDICTABLE. * testsuite/gas/arm/mve-vqdmladh-bad.l: Remove tests. * testsuite/gas/arm/mve-vqdmladh-bad.s: Remove tests. * testsuite/gas/arm/mve-vqdmladh.d: New tests. * testsuite/gas/arm/mve-vqdmladh.s: New tests. * testsuite/gas/arm/mve-vqdmlsdh-bad.l: Remove tests. * testsuite/gas/arm/mve-vqdmlsdh-bad.s: Remove tests. * testsuite/gas/arm/mve-vqdmlsdh.d: New tests. * testsuite/gas/arm/mve-vqdmlsdh.s: New tests. opcodes * arm-dis.c (is_mve_unpredictable): Stop marking some MVE instructions as UNPREDICTABLE.
2019-07-19x86: Pass -O0 to assembler in noextreg.dH.J. Lu2-0/+5
* testsuite/gas/i386/noextreg.d: Pass -O0 to assembler.
2019-07-19cpu,opcodes,gas: use %r0 and %r6 instead of %a and %ctf in eBPF disassemblerJose E. Marchesi7-52/+60
This patch changes the eBPF CPU description to prefer the register names %r0 and %r6 instead of %a and %ctx when disassembling. This matches better with the current practice, vs. cBPF. It also updates the GAS tests in order to reflect this change. Tested in a x86_64 host. cpu/ChangeLog: 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf.cpu (h-gpr): when disassembling, use %r0 and %r6 instead of %a and %ctx. opcodes/ChangeLog: 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-desc.c: Regenerated. gas/ChangeLog: 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/alu.d: Use %r6 instead of %ctx. * testsuite/gas/bpf/lddw-be.d: Likewise. * testsuite/gas/bpf/lddw.d: Likewise. * testsuite/gas/bpf/alu-be.d: Likewise. * testsuite/gas/bpf/alu32.d: Likewise.
2019-07-19gas: make .lcomm to accept an optional aligmnet in eBPF targetsJose E. Marchesi2-1/+49
Tested in a x86_64 host. gas/ChangeLog: 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c (pe_lcomm_internal): Adapted from tc-i386.c. (pe_lcomm): Likewise. (md_pseudo_table): Use pe_lcomm to implement .lcomm.
2019-07-19[AArch64] Rename +bitperm to +sve2-bitpermRichard Sandiford8-7/+17
After some discussion, we've decided to rename the +bitperm feature flag to +sve2-bitperm, so that it's consistent with the other SVE2 feature flags. The associated internal macros already used "SVE2_BITPERM", so only the feature flag itself needs to change. 2019-07-19 Richard Sandiford <richard.sandiford@arm.com> gas/ * doc/c-aarch64.texi: Remame the +bitperm extension to +sve2-bitperm. * config/tc-aarch64.c (aarch64_features): Likewise. * testsuite/gas/aarch64/illegal-sve2-aes.d: Update accordingly. * testsuite/gas/aarch64/illegal-sve2-sha3.d: Likewise. * testsuite/gas/aarch64/illegal-sve2-sm4.d: Likewise. * testsuite/gas/aarch64/illegal-sve2.d: Likewise. * testsuite/gas/aarch64/sve2.d: Likewise.
2019-07-19[PowerPC64] pc-relative TLS relocationsAlan Modra2-5/+47
This patch supports using pcrel instructions in TLS code sequences. A number of new relocations are needed, gas operand modifiers to generate those relocations, and new TLS optimisation. For optimisation it turns out that the new pcrel GD and LD sequences can be distinguished from the non-pcrel GD and LD sequences by there being different relocations on the new sequence. The final "add ra,rb,13" on IE sequences similarly needs a new relocation, or as I chose, a modification of R_PPC64_TLS. On pcrel IE code, the R_PPC64_TLS points one byte into the "add" instruction rather than being on the instruction boundary. GD: pla 3,z@got@tlsgd@pcrel # R_PPC64_GOT_TLSGD34 bl __tls_get_addr@notoc(z@tlsgd) # R_PPC64_TLSGD and R_PPC64_REL24_NOTOC edited to IE pld 3,z@got@tprel@pcrel add 3,3,13 edited to LE paddi 3,13,z@tprel nop LD: pla 3,z@got@tlsld@pcrel # R_PPC64_GOT_TLSLD34 bl __tls_get_addr@notoc(z@tlsld) # R_PPC64_TLSLD and R_PPC64_REL24_NOTOC .. paddi 9,3,z2@dtprel pld 10,z3@got@dtprel@pcrel add 10,10,3 edited to LE paddi 3,13,0x1000 nop IE: pld 9,z@got@tprel@pcrel # R_PPC64_GOT_TPREL34 add 3,9,z@tls@pcrel # R_PPC64_TLS at insn+1 ldx 4,9,z@tls@pcrel lwax 5,9,z@tls@pcrel stdx 5,9,z@tls@pcrel edited to LE paddi 9,13,z@tprel nop ld 4,0(9) lwa 5,0(9) std 5,0(9) LE: paddi 10,13,z@tprel include/ * elf/ppc64.h (R_PPC64_TPREL34, R_PPC64_DTPREL34), (R_PPC64_GOT_TLSGD34, R_PPC64_GOT_TLSLD34), (R_PPC64_GOT_TPREL34, R_PPC64_GOT_DTPREL34): Define. (IS_PPC64_TLS_RELOC): Include new tls relocs. bfd/ * reloc.c (BFD_RELOC_PPC64_TPREL34, BFD_RELOC_PPC64_DTPREL34), (BFD_RELOC_PPC64_GOT_TLSGD34, BFD_RELOC_PPC64_GOT_TLSLD34), (BFD_RELOC_PPC64_GOT_TPREL34, BFD_RELOC_PPC64_GOT_DTPREL34), (BFD_RELOC_PPC64_TLS_PCREL): New pcrel tls relocs. * elf64-ppc.c (ppc64_elf_howto_raw): Add howtos for pcrel tls relocs. (ppc64_elf_reloc_type_lookup): Translate pcrel tls relocs. (must_be_dyn_reloc, dec_dynrel_count): Add R_PPC64_TPREL64. (ppc64_elf_check_relocs): Support pcrel tls relocs. (ppc64_elf_tls_optimize, ppc64_elf_relocate_section): Likewise. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas/ * config/tc-ppc.c (ppc_elf_suffix): Map "tls@pcrel", "got@tlsgd@pcrel", "got@tlsld@pcrel", "got@tprel@pcrel", and "got@dtprel@pcrel". (fixup_size, md_assemble): Handle pcrel tls relocs. (ppc_force_relocation, ppc_fix_adjustable): Likewise. (md_apply_fix, tc_gen_reloc): Likewise. ld/ * testsuite/ld-powerpc/tlsgd.d, * testsuite/ld-powerpc/tlsgd.s, * testsuite/ld-powerpc/tlsie.d, * testsuite/ld-powerpc/tlsie.s, * testsuite/ld-powerpc/tlsld.d, * testsuite/ld-powerpc/tlsld.s: New tests. * testsuite/ld-powerpc/powerpc.exp: Run them.
2019-07-18gas: .lcomm gets an alignment argument in eBPFJose E. Marchesi2-1/+8
gas/ChangeLog: 2019-07-17 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c: Make .lcomm to get a third argument with the alignment.
2019-07-17gas: support .half, .word and .dword directives in eBPFJose E. Marchesi7-0/+58
This little patch adds support to the eBPF port of GAS for a few data directives. The names for the directives have been chosen to be coherent with the suffixes used in eBPF instructions: b, h, w and dw for 8, 16, 32 and 64-bit values respectively. Documentation and tests included. Tested in a x86_64 host. gas/ChangeLog: 2019-07-17 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c (md_pseudo_table): .half, .word and .dword. * testsuite/gas/bpf/data.s: New file. * testsuite/gas/bpf/data.d: Likewise. * testsuite/gas/bpf/data-be.d: Likewise. * testsuite/gas/bpf/bpf.exp: Run data and data-be. * doc/c-bpf.texi (BPF Directives): New section.
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