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This patch makes GAS emit a warning when trying to assemble the Armv8.2
FP16 instructions VMOVX and VINS with condition codes. The Armv8-A
Reference Manual specifies these instructions without conditional codes
and says that if they are found in an IT block that they are CONSTRAINED
UNPREDICABLE.
gas/ChangeLog:
2018-02-22 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_neon_movhf): If conditional error out when in arm
mode and emit warning in thumb mode.
* testsuite/gas/arm/armv8-2-fp16-scalar-bad.s: Add new tests.
* testsuite/gas/arm/armv8-2-fp16-scalar-bad.l: Idem.
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Add {rex} pseudo prefix to generate a REX byte for integer and legacy
vector instructions if possible. Note that this differs from the rex
prefix which generates REX prefix unconditionally.
gas/
* config/tc-i386.c (_i386_insn): Add rex_encoding.
(md_assemble): When i.rex_encoding is true, generate a REX byte
if possible.
(parse_insn): Set i.rex_encoding for {rex}.
* doc/c-i386.texi: Document {rex}.
* testsuite/gas/i386/x86-64-pseudos.s: Add {rex} tests.
* testsuite/gas/i386/x86-64-pseudos.d: Updated.
opcodes/
* i386-opc.tbl: Add {rex},
* i386-tbl.h: Regenerated.
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instruction during lookup.
PR 22014
* config/tc-mips.c (mips_lookup_insn): Use memmove to strip the
instruction size suffix.
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Add a pair of MIPS16 branch tests to verify correct R_MIPS16_PC16_S1
relocation generation for cross-section references in a single source.
This complements commit c9775dde3277 ("MIPS16: Add R_MIPS16_PC16_S1
branch relocation support").
gas/
* testsuite/gas/mips/mips16-branch-reloc-4.d: New test.
* testsuite/gas/mips/mips16-branch-reloc-5.d: New test.
* testsuite/gas/mips/mips16-branch-reloc-4.s: New test source.
* testsuite/gas/mips/mips16-branch-reloc-5.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
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Literal movement code may grow auto litpool so big that it won't be
possible to jump around it. Limit the size of auto litpools by 1/2 of
the jump range.
gas/
2018-02-20 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (struct litpool_frag): Add new field
literal_count.
(MAX_AUTO_POOL_LITERALS, MAX_EXPLICIT_POOL_LITERALS)
(MAX_POOL_LITERALS): New macro definitions.
(auto_litpool_limit): Initialize to 0.
(md_parse_option): Set auto_litpool_limit in the presence of
--auto-litpools option.
(xtensa_maybe_create_literal_pool_frag): Zero-initialize
literal_count field.
(xg_find_litpool): New function. Make sure that found literal
pool size is within the limit.
(xtensa_move_literals): Extract literal pool search code into
the new function.
* testsuite/gas/xtensa/all.exp: Add auto-litpools-2 test.
* testsuite/gas/xtensa/auto-litpools-2.d: New file.
* testsuite/gas/xtensa/auto-litpools-2.s: New file.
* testsuite/gas/xtensa/auto-litpools.d: Fix up changed
addresses.
* testsuite/gas/xtensa/auto-litpools.s: Change literal value so
that objdump doesn't get out of sync.
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Documentation for .arch_extension says it accepts the same architectural
extensions as those accepted by -mcpu. Given the name and the fact that
-march for obvious reason also accept the same extensions, I believe
it's worth mentioning that it accepts the same extensions as both
-march and -mcpu. This commit addresses that.
2018-02-20 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* doc/c-arm.texi (.arch_extension): Mention extensions it accepts are
also the same as -march.
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Implement the '.nop SIZE[, CONTROL]' assembler directive, which emits
SIZE bytes filled with no-op instructions. SIZE is absolute expression.
The optional CONTROL byte controls how no-op instructions should be
generated. If the comma and @var{control} are omitted, CONTROL is
assumed to be zero.
For Intel 80386 and AMD x86-64 targets, CONTROL byte specifies the size
limit of a single no-op instruction. The valid values of CONTROL byte
are between 0 and 8 for 16-bit mode, between 0 and 10 for 32-bit mode,
between 0 and 11 for 64-bit mode. When 0 is used, the no-op size limit
is set to the maximum supported size.
2 new relax states, rs_space_nop and rs_fill_nop, are added to enum
_relax_state, which are similar to rs_space and rs_fill, respectively,
but they fill with no-op instructions, instead of a single byte. A
target backend must override the default md_generate_nops to generate
proper no-op instructions. Otherwise, an error of unimplemented .nop
directive will be issued whenever .nop directive is used.
* NEWS: Mention .nop directive.
* as.h (_relax_state): Add rs_space_nop and rs_fill_nop.
* read.c (potable): Add .nop.
(s_nop): New function.
* read.h (s_nop): New prototype.
* write.c (cvt_frag_to_fill): Handle rs_space_nop and
rs_fill_nop.
(md_generate_nops): New function.
(relax_segment): Likewise.
(write_contents): Use md_generate_nops for rs_fill_nop.
* config/tc-i386.c (alt64_11): New.
(alt64_patt): Likewise.
(md_convert_frag): Handle rs_space_nop.
(i386_output_nops): New function.
(i386_generate_nops): Likewise.
(i386_align_code): Call i386_output_nops.
* config/tc-i386.h (i386_generate_nops): New.
(md_generate_nops): Likewise.
* doc/as.texinfo: Document .nop directive.
* testsuite/gas/i386/i386.exp: Run .nop directive tests.
* testsuite/gas/i386/nop-1.d: New file.
* testsuite/gas/i386/nop-1.s: Likewise.
* testsuite/gas/i386/nop-2.d: Likewise.
* testsuite/gas/i386/nop-2.s: Likewise.
* testsuite/gas/i386/nop-3.d: Likewise.
* testsuite/gas/i386/nop-3.s: Likewise.
* testsuite/gas/i386/nop-4.d: Likewise.
* testsuite/gas/i386/nop-4.s: Likewise.
* testsuite/gas/i386/nop-5.d: Likewise.
* testsuite/gas/i386/nop-5.s: Likewise.
* testsuite/gas/i386/nop-6.d: Likewise.
* testsuite/gas/i386/nop-6.s: Likewise.
* testsuite/gas/i386/nop-bad-1.l: Likewise.
* testsuite/gas/i386/nop-bad-1.s: Likewise.
* testsuite/gas/i386/x86-64-nop-1.d: Likewise.
* testsuite/gas/i386/x86-64-nop-2.d: Likewise.
* testsuite/gas/i386/x86-64-nop-3.d: Likewise.
* testsuite/gas/i386/x86-64-nop-4.d: Likewise.
* testsuite/gas/i386/x86-64-nop-5.d: Likewise.
* testsuite/gas/i386/x86-64-nop-6.d: Likewise.
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The build attribute number for Armv8.4-A is currently incorrectly set to that of Armv8-M.
This patch fixes that by setting it as part of the Armv8-A family and adds a test for it.
gas/
2018-02-15 Tamar Christina <tamar.christina@arm.com>
* config/tc-arm.c (cpu_arch_ver): Renumber ARM_ARCH_V8_4A.
* testsuite/gas/arm/attr-march-armv8_4-a.d: New.
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For jumps requiring multiple trampolines trampoline placement code may
place multiple sequential trampolines into the same frag. Don't do that.
gas/
2018-02-13 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (xg_find_best_trampoline): Skip trampoline
frag that contains source address.
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ORR instruction.
PR 22773
* config/tc-arm.c (md_apply_fix): Test Rn field of Thumb ORR
instruction before assuming that it is a MOV instruction.
* testsuite/gas/arm/pr22773.s: New test.
* testsuite/gas/arm/pr22773.d: New test driver.
* testsuite/gas/arm/pr22773.l: New expected output.
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Since there is no need to prepare for PLT branch on x86-64, generate
R_X86_64_PLT32, instead of R_X86_64_PC32, if possible, which can be
used as a marker for 32-bit PC-relative branches.
To compile Linux kernel, this patch:
From: "H.J. Lu" <hjl.tools@gmail.com>
Subject: [PATCH] x86: Treat R_X86_64_PLT32 as R_X86_64_PC32
On i386, there are 2 types of PLTs, PIC and non-PIC. PIE and shared
objects must use PIC PLT. To use PIC PLT, you need to load
_GLOBAL_OFFSET_TABLE_ into EBX first. There is no need for that on
x86-64 since x86-64 uses PC-relative PLT.
On x86-64, for 32-bit PC-relative branches, we can generate PLT32
relocation, instead of PC32 relocation, which can also be used as
a marker for 32-bit PC-relative branches. Linker can always reduce
PLT32 relocation to PC32 if function is defined locally. Local
functions should use PC32 relocation. As far as Linux kernel is
concerned, R_X86_64_PLT32 can be treated the same as R_X86_64_PC32
since Linux kernel doesn't use PLT.
is needed. It is available on hjl/plt32/master branch at
https://github.com/hjl-tools/linux
bfd/
PR gas/22791
* elf64-x86-64.c (is_32bit_relative_branch): Removed.
(elf_x86_64_relocate_section): Check PIC relocations in PIE.
Remove is_32bit_relative_branch usage. Disallow PC32 reloc
against protected function in shared object.
gas/
PR gas/22791
* config/tc-i386.c (need_plt32_p): New function.
(output_jump): Generate BFD_RELOC_X86_64_PLT32 if possible.
(md_estimate_size_before_relax): Likewise.
* testsuite/gas/i386/reloc64.d: Updated.
* testsuite/gas/i386/x86-64-jump.d: Likewise.
* testsuite/gas/i386/x86-64-mpx-branch-1.d: Likewise.
* testsuite/gas/i386/x86-64-mpx-branch-2.d: Likewise.
* testsuite/gas/i386/x86-64-relax-2.d: Likewise.
* testsuite/gas/i386/x86-64-relax-3.d: Likewise.
* testsuite/gas/i386/ilp32/reloc64.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise.
ld/
PR gas/22791
* testsuite/ld-x86-64/mpx1c.rd: Updated.
* testsuite/ld-x86-64/pr22791-1.err: New file.
* testsuite/ld-x86-64/pr22791-1a.c: Likewise.
* testsuite/ld-x86-64/pr22791-1b.s: Likewise.
* testsuite/ld-x86-64/pr22791-2.rd: Likewise.
* testsuite/ld-x86-64/pr22791-2a.s: Likewise.
* testsuite/ld-x86-64/pr22791-2b.c: Likewise.
* testsuite/ld-x86-64/pr22791-2c.s: Likewise.
* testsuite/ld-x86-64/x86-64.exp: Run PR ld/22791 tests.
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incompatible function types.
PR 22823
bfd Fix compile time warnings generated by gcc version 8.
* libbfd-in.h: Remove extraneous text from prototypes.
Add prototypes for bfd_false_any, bfd_true_any,
bfd_nullvoidptr_any, bfd_0_any, bfd_0u_any, bfd_0l_any,
bfd_n1_any, bfd_void_any.
(_bfd_generic_bfd_copy_private_bfd_data): Use vararg based dummy
function.
(_bfd_generic_bfd_merge_private_bfd_data): Likewise.
(_bfd_generic_bfd_set_private_flags): Likewise.
(_bfd_generic_bfd_copy_private_section_data): Likewise.
(_bfd_generic_bfd_copy_private_symbol_data): Likewise.
(_bfd_generic_bfd_copy_private_header_data): Likewise.
(_bfd_generic_bfd_print_private_bfd_data): Likewise.
(_bfd_noarchive_construct_extended_name_table): Likewise.
(_bfd_noarchive_truncate_arname): Likewise.
(_bfd_noarchive_write_ar_hdr): Likewise.
(_bfd_noarchive_get_elt_at_index): Likewise.
(_bfd_nosymbols_canonicalize_symtab): Likewise.
(_bfd_nosymbols_print_symbol): Likewise.
(_bfd_nosymbols_get_symbol_info): Likewise.
(_bfd_nosymbols_get_symbol_version_string): Likewise.
(_bfd_nosymbols_bfd_is_local_label_name): Likewise.
(_bfd_nosymbols_bfd_is_target_special_symbol): Likewise.
(_bfd_nosymbols_get_lineno): Likewise.
(_bfd_nosymbols_find_nearest_line): Likewise.
(_bfd_nosymbols_find_line): Likewise.
(_bfd_nosymbols_find_inliner_info): Likewise.
(_bfd_nosymbols_bfd_make_debug_symbol): Likewise.
(_bfd_nosymbols_read_minisymbols): Likewise.
(_bfd_nosymbols_minisymbol_to_symbol): Likewise.
(_bfd_norelocs_bfd_reloc_type_lookup): Likewise.
(_bfd_norelocs_bfd_reloc_name_lookup): Likewise.
(_bfd_nowrite_set_arch_mach): Likewise.
(_bfd_nowrite_set_section_contents): Likewise.
(_bfd_nolink_sizeof_headers): Likewise.
(_bfd_nolink_bfd_get_relocated_section_contents): Likewise.
(_bfd_nolink_bfd_relax_section): Likewise.
(_bfd_nolink_bfd_gc_sections): Likewise.
(_bfd_nolink_bfd_lookup_section_flags): Likewise.
(_bfd_nolink_bfd_merge_sections): Likewise.
(_bfd_nolink_bfd_is_group_section): Likewise.
(_bfd_nolink_bfd_discard_group): Likewise.
(_bfd_nolink_bfd_link_hash_table_create): Likewise.
(_bfd_nolink_bfd_link_add_symbols): Likewise.
(_bfd_nolink_bfd_link_just_syms): Likewise.
(_bfd_nolink_bfd_copy_link_hash_symbol_type): Likewise.
(_bfd_nolink_bfd_final_link): Likewise.
(_bfd_nolink_bfd_link_split_section): Likewise.
(_bfd_nolink_section_already_linked): Likewise.
(_bfd_nolink_bfd_define_common_symbol): Likewise.
(_bfd_nolink_bfd_define_start_stop): Likewise.
(_bfd_nodynamic_canonicalize_dynamic_symtab): Likewise.
(_bfd_nodynamic_get_synthetic_symtab): Likewise.
(_bfd_nodynamic_get_dynamic_reloc_upper_bound _bfd_): Likewise.
(_bfd_nodynamic_canonicalize_dynamic_reloc): Likewise.
* libbfd.c (bfd_false_any): New function. Like bfd_false but
accepts one or more arguments.
(bfd_true_any): Likewise.
(bfd_nullvoidptr_any): Likewise.
(bfd_0_any): Likewise.
(bfd_0u_any): Likewise.
(bfd_0l_any): Likewise.
(_bfd_n1_any): Likewise.
(bfd_void_any): Likewise.
* libbfd.h (extern): Regenerate
* aout-target.h (MY_bfd_is_target_special_symbol): Use vararg
based dummy function.
* aout-tic30.c (tic30_aout_set_arch_mach): Likewise.
* binary.c (binary_get_symbol_info): Likewise.
* coff-alpha.c (alpha_ecoff_backend_data): Likewise.
* coff-mips.c (mips_ecoff_backend_data): Likewise.
* coffcode.h (coff_set_alignment_hook): Likewise.
(symname_in_debug_hook): Likewise.
(bfd_coff_backend_data bigobj_swap_table): Likewise.
* elf-m10300.c (elf_backend_omit_section_dynsym): Likewise.
* elf32-cr16.c (elf_backend_omit_section_dynsym): Likewise.
* elf32-lm32.c (elf_backend_omit_section_dynsym): Likewise.
* elf32-m32r.c (elf_backend_omit_section_dynsym): Likewise.
* elf32-metag.c (elf_backend_omit_section_dynsym): Likewise.
* elf32-score.c (elf_backend_omit_section_dynsym): Likewise.
* elf32-score7.c (elf_backend_omit_section_dynsym): Likewise.
* elf32-xstormy16.c (elf_backend_omit_section_dynsym): Likewise.
* elf32-xtensa.c (elf_backend_omit_section_dynsym): Likewise.
* elf64-alpha.c (elf_backend_omit_section_dynsym): Likewise.
* elf64-hppa.c (elf_backend_omit_section_dynsym): Likewise.
* elf64-ia64-vms.c (elf_backend_omit_section_dynsym): Likewise.
* elf64-mmix.c (elf_backend_omit_section_dynsym): Likewise.
* elf64-sh64.c (elf_backend_omit_section_dynsym): Likewise.
* elfnn-ia64.c (elf_backend_omit_section_dynsym): Likewise.
* elfxx-target.h (bfd_elfNN_bfd_debug_info_accumulate): Likewise.
(bfd_elfNN_bfd_make_debug_symbol): Likewise.
(bfd_elfNN_bfd_merge_private_bfd_data): Likewise.
(bfd_elfNN_bfd_set_private_flags): Likewise.
(bfd_elfNN_bfd_is_target_special_symbol): Likewise.
(elf_backend_init_index_section): Likewise.
(elf_backend_allow_non_load_phdr): Likewise.
* elfxx-x86.h (elf_backend_omit_section_dynsym): Likewise.
* i386msdos.c (msdos_bfd_is_target_special_symbol): Likewise.
* ieee.c (ieee_construct_extended_name_table): Likewise.
(ieee_write_armap): Likewise.
(ieee_write_ar_hdr): Likewise.
(ieee_bfd_is_target_special_symbol): Likewise.
* ihex.c (ihex_canonicalize_symtab): Likewise.
(ihex_bfd_is_target_special_symbol): Likewise.
* libaout.h (aout_32_bfd_is_target_special_symbol): Likewise.
* libecoff.h (_bfd_ecoff_bfd_is_target_special_symbol): Likewise.
(_bfd_ecoff_set_alignment_hook): Likewise.
* mach-o-target.c (bfd_mach_o_bfd_is_target_special_symbol): Likewise.
* mmo.c (mmo_bfd_is_target_special_symbol): Likewise.
* nlm-target.h (nlm_bfd_is_target_special_symbol): Likewise.
* oasys.c (oasys_construct_extended_name_table): Likewise.
(oasys_write_armap): Likewise.
(oasys_write_ar_hdr): Likewise.
(oasys_bfd_is_target_special_symbol): Likewise.
* pef.c (bfd_pef_bfd_is_target_special_symbol): Likewise.
* plugin.c (bfd_plugin_bfd_is_target_special_symbol): Likewise.
* ppcboot.c (ppcboot_bfd_is_target_special_symbol): Likewise.
* som.c (som_bfd_is_target_special_symbol): Likewise.
* srec.c (srec_bfd_is_target_special_symbol): Likewise.
* tekhex.c (tekhex_bfd_is_target_special_symbol): Likewise.
* verilog.c (verilog_bfd_is_target_special_symbol): Likewise.
* versados.c (versados_bfd_is_target_special_symbol): Likewise.
(versados_bfd_reloc_name_lookup): Likewise.
* vms-alpha.c (vms_bfd_is_target_special_symbol): Likewise.
(vms_bfd_define_start_stop): Likewise.
(alpha_vms_bfd_is_target_special_symbol): Likewise.
* wasm-module.c (wasm_bfd_is_target_special_symbol): Likewise.
* xsym.c (bfd_sym_bfd_is_target_special_symbol): Likewise.
* elf32-arc.c (get_replace_function): Assign replacement function
to func pointer.
* elf32-i370.c (i370_noop): Update prototype.
gas * config/obj-elf.c (elf_pseudo_table): Remove now redundant
casts.
(obj_elf_vtable_inherit): Rename to obj_elf_get_vtable_inherit.
(obj_elf_vtable_inherit): New stub function that calls
obj_elf_get_vtable_inherit.
(obj_elf_vtable_entry): Rename to obj_elf_get_vtable_entry.
(obj_elf_vtable_entry): New stub function that calls
obj_elf_get_vtable_entry.
* config/obj-elf.h (obj_elf_vtable_inherit): Update prototype.
(obj_elf_vtable_entry) Likewise.
(obj_elf_get_vtable_inherit) Likewise.
(obj_elf_get_vtable_entry) Likewise.
* config/tc-arm.c (md_pseudo_table): Remove now redundant cast.
* config/tc-i386c (md_pseudo_table): Likewise.
* config/tc-hppa.c (pa_vtable_entry): Call
obj_elf_get_vtable_entry.
(pa_vtable_inherit): Call obj_elf_get_vtable_inherit.
* config/tc-mips.c (s_mips_file): Replace call to dwarf2_get_file
with call to dwarf2_get_filename.
* dwarf2dbg.c (dwarf2_directive_file): Rename to
dwarf2_directive_filename.
(dwarf2_directive_file): New stub function that calls
dwarf2_directive_filename.
* dwarf2dbg.h: Prototype dwarf2_directive_filename.
opcodes * metag-dis.c (print_fmmov): Double buffer size to avoid warning
about truncation of printing.
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Correct a duplicate `Loongson-3A tests' GAS test name introduced with
commit 986754024085 ("Add Loongson3A specific instructions"),
<https://sourceware.org/ml/binutils/2010-12/msg00447.html>, shared
between gas/testsuite/gas/mips/loongson-3a.d and
gas/testsuite/gas/mips/loongson-3a-2.d.
gas/
* testsuite/gas/mips/loongson-3a-2.d: Rename test.
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Correct a commit 2d6dda71611b ("MIPS/BFD: Correctly report unsupported
`.reginfo' section size") issue and avoid a GAS test failure:
regexp_diff match failure
regexp "^.*: Incorrect `\.reginfo' section size; expected 24, got 28$"
line "../as-new: dump.o: Incorrect `.reginfo' section size; expected 24, got 32"
FAIL: MIPS assembled .reginfo section size (n32)
on MIPS targets other than bare-metal ones. The reason for this failure
is section padding to alignment, done in `size_seg'. For n32 `.reginfo'
the section alignment is set to 3, and therefore the section is padded
to a multiple of 8, except for bare-metal targets, for which padding is
unconditionally disabled in `md_section_align'.
Use `--no-pad-sections' then to disable padding for all targets, so that
the size of `.reginfo' is always the same, matching the message pattern.
gas/
* testsuite/gas/mips/reginfo-2-n32.d: Add `--no-pad-sections' to
`as' flags.
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The instruction encoding for the MIPS r6 sigrie instruction seems to be
incorrect. It's currently 0x4170xxxx (which overlaps with ei, di, evp,
and dvp), but should be 0x0417xxxx. See ISA reference[1][2].
References:
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies, Inc., Document
Number: MD00086, Revision 6.06, December 15, 2016, Table A.4 "MIPS32
REGIMM Encoding of rt Field", p. 452
[2] "MIPS Architecture For Programmers Volume II-A: The MIPS64
Instruction Set Reference Manual", Imagination Technologies, Inc.,
Document Number: MD00087, Revision 6.06, December 15, 2016, Table
A.4 "MIPS64 REGIMM Encoding of rt Field", p. 581
opcodes/
* mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
gas/
* testsuite/gas/mips/r6.d: Update for "sigrie" encoding fix.
* testsuite/gas/mips/r6-n32.d: Likewise.
* testsuite/gas/mips/r6-n64.d: Likewise.
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Checks for insn alignment were hopelessly confused when misaligned
data starts a new frag. The real-world testcase happened to run out
of frag space in the middle of emitting a trace-back table via
something like:
.byte 0 /* VERSION=0 */
.byte 9 /* LANG=C++ */
.byte 34 /* Bits on: has_tboff, fp_present */
.byte 64 /* Bits on: name_present */
.byte 128 /* Bits on: stores_bc, FP_SAVED=0 */
.byte 0 /* Bits on: GP_SAVED=0 */
.byte 2 /* FIXEDPARMS=2 */
.byte 1 /* FLOATPARMS=0, parmsonstk */
.long 0
.long 768 /* tb_offset: 0x300 */
.hword 45 /* Function name length: 45 */
.long 0x334e5a5f
.long 0x31766f70
.long 0x65744932
.long 0x69746172
.long 0x7a5f6e6f
.long 0x64504533
.long 0x5f534e50
.long 0x72463431
.long 0x61746361
.long 0x74535f6c
.long 0x74637572
.byte 0x45
.byte 0
The trigger being those misaligned .long's output for the function
name. A most horrible way to output a string, especially considering
endian issues..
PR 22819
* config/tc-ppc.c (md_assemble): Rewrite insn alignment checking.
(ppc_frag_check): Likewise.
* testsuite/gas/ppc/misalign.d,
* testsuite/gas/ppc/misalign.l,
* testsuite/gas/ppc/misalign.s: New test.
* testsuite/gas/ppc/misalign2.d,
* testsuite/gas/ppc/misalign2.s: New test.
* testsuite/gas/ppc/ppc.exp: Run them.
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Correct a commit f0531ed6a429 ("Compress loads/stores with implicit 0
offset.") regression and remove a `-Wshadow' compilation error:
cc1: warnings being treated as errors
.../gas/config/tc-riscv.c: In function 'riscv_handle_implicit_zero_offset':
.../gas/config/tc-riscv.c:1194: error: declaration of 'expr' shadows a global declaration
.../gas/expr.h:180: error: shadowed declaration is here
make[4]: *** [tc-riscv.o] Error 1
which for versions of GCC before 4.8 prevents GAS for RISC-V targets
from being built. See also GCC PR c/53066.
gas/
* config/tc-riscv.c (riscv_handle_implicit_zero_offset): Rename
`expr' parameter to `ep'.
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Report an error when an unsupported `.reginfo' section size is found in
`_bfd_mips_elf_section_processing', removing an assertion that triggers
at elfxx-mips.c:7105 in GAS when assembling input like:
.section .reginfo
.word 0xdeadbeef
and in `objcopy --rename-section' when renaming an incorrectly sized
section to `.reginfo'.
bfd/
* elfxx-mips.c (_bfd_mips_elf_section_processing): For
SHT_MIPS_REGINFO sections don't assert the correct size and
report an error instead.
binutils/
* testsuite/binutils-all/mips/mips-reginfo.d: New test.
* testsuite/binutils-all/mips/mips-reginfo-n32.d: New test.
* testsuite/binutils-all/mips/mips-reginfo.s: New test source.
* testsuite/binutils-all/mips/mips.exp: Run the new tests.
gas/
* testsuite/gas/mips/reginfo-2.d: New test.
* testsuite/gas/mips/reginfo-2-n32.d: New test.
* testsuite/gas/mips/reginfo-2.l: New test stderr output.
* testsuite/gas/mips/reginfo-2.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
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The PR22714 testcase is such that the input buffer processed by
do_scrub_chars ends on this line
1: bug "Returning to usermode but unexpected PSR bits set?", \@
right at the backslash. (The line is part of a macro definition.)
The next input buffer then starts with '@' which starts a comment on
ARM, and the check for \@ fails due to to == tostart. Now it would be
possible to simply access to[-1] in this particular case, but that's
ugly, and to be absolutely safe from people deliberately trying to
crash gas we'd need the read.c:read_a_source_file buffer passed to
do_scrub_chars to have a single byte pad at the start.
PR 22714
* app.c (last_char): New static var.
(struct app_save): Add last_char field.
(app_push, app_pop): Handle it.
(do_scrub_chars): Use last_char in test for "\@". Set last_char.
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The .dc.a directive has wrong size (32 bits) on SPARC 64-bit because
the assembler sets the correct BFD architecture only at the very end
of the processing and it's too late for the directive. It's fixed by
defining TARGET_MACH and making it return a sensible default value.
gas/
* config/tc-sparc.h (sparc_mach): Declare.
(TARGET_MACH): Define to above.
* config/tc-sparc.c (sparc_mach): New function.
(sparc_md_end): Minor tweak.
ld/
* testsuite/ld-elf/pr22450.d: Remove reference to SPARC64.
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Fix a commit 0a44bf6950b3 ("mips-vxworks support"),
<https://sourceware.org/ml/binutils/2006-03/msg00179.html>, regression
and override the choice of the `vxworks' target environment introduced
with commit ea3eed15006f ("Add generic vxworks GAS target."),
<https://sourceware.org/ml/binutils/2005-01/msg00052.html>, for
`mips-*-windiss' targets as they have not been converted to the VxWorks
target format introduced with the former commit, removing a GAS target
format selection failure:
Assembler messages:
Fatal error: selected target format 'elf32-bigmips-vxworks' unknown
on any assembly attempt with `mips-windiss' and equivalent target
configurations.
gas/
* configure.tgt: Use generic emulation for `mips-*-windiss',
overriding the blanket choice made for `*-*-windiss'.
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Use `mips-*-sysv4*' rather than `mips-*-sysv4*MP*' to match the system
type for System V Release 4 MIPS targets, removing a GAS target
selection failure:
Assembler messages:
Fatal error: selected target format 'elf32-bigmips' unknown
on any assembly attempt with `mips-sysv4' and equivalent target
configurations. These would typically be called `mips-sni-sysv4'
(Sinix) vs `mips-dde-sysv4.2MP' (Supermax).
This corrects commit 8614eeee67f9 ("Traditional MIPS patches"),
<https://sourceware.org/ml/binutils/2000-07/msg00018.html>, making GAS
target selection match commit dd745cfae548 ("Traditional MIPS patches"),
<https://sourceware.org/ml/binutils/2000-07/msg00018.html>, and commit
3548145dcbf6 ("Traditional MIPS patches"),
<https://sourceware.org/ml/binutils/2000-07/msg00018.html>, which added
support for these targets to BFD and LD respectively.
gas/
* configure.tgt: Use `mips-*-sysv4*' rather than
`mips-*-sysv4*MP*'.
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This is a patch to add the gas support for group relocations to create a
16, 32, 48, or 64 bit PC-relative offset inline.
The following relocations are added along with the test cases:
BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G3.
bfd/
2018-01-24 Renlin Li <renlin.li@arm.com>
* reloc.c: Add BFD_RELOC_AARCH64_MOVW_PREL_G0,
BFD_RELOC_AARCH64_MOVW_PREL_G0_NC, BFD_RELOC_AARCH64_MOVW_PREL_G1,
BFD_RELOC_AARCH64_MOVW_PREL_G1_NC, BFD_RELOC_AARCH64_MOVW_PREL_G2,
BFD_RELOC_AARCH64_MOVW_PREL_G2_NC, BFD_RELOC_AARCH64_MOVW_PREL_G3.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* elfnn-aarch64.c (elfNN_aarch64_howto_table): Add entries for
BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G3.
gas/
2018-01-24 Renlin Li <renlin.li@arm.com>
* config/tc-aarch64.c (reloc_table): add entries for
BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G3.
(process_movw_reloc_info): Supports newly added MOVW_PREL relocations.
(md_apply_fix): Likewise
* testsuite/gas/aarch64/prel_g0.s: New.
* testsuite/gas/aarch64/prel_g0.d: New.
* testsuite/gas/aarch64/prel_g0_nc.s: New.
* testsuite/gas/aarch64/prel_g0_nc.d: New.
* testsuite/gas/aarch64/prel_g1.s: New.
* testsuite/gas/aarch64/prel_g1.d: New.
* testsuite/gas/aarch64/prel_g1_nc.s: New.
* testsuite/gas/aarch64/prel_g1_nc.d: New.
* testsuite/gas/aarch64/prel_g2.s: New.
* testsuite/gas/aarch64/prel_g2.d: New.
* testsuite/gas/aarch64/prel_g2_nc.s: New.
* testsuite/gas/aarch64/prel_g2_nc.d: New.
* testsuite/gas/aarch64/prel_g3.s: New.
* testsuite/gas/aarch64/prel_g3.d: New.
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Correct an issue with the `mips64*-ps2-elf*' target introduced with
commit e407c74b5b60 ("Support for MIPS R5900 (Sony Playstation 2)"),
<https://sourceware.org/ml/binutils/2012-12/msg00240.html> and make
the n32 ABI the default for GAS, consistently with how BFD and LD
are configured for this target.
gas/
* configure.ac: Also set `mips_default_abi' to N32_ABI for
`mips64*-ps2-elf*'.
* configure: Regenerate.
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Complement commit 23fce1e31156 ("MIPS16 intermix test failure"),
<https://sourceware.org/ml/binutils/2009-01/msg00335.html>, and
remove a stale option marker entry.
gas/
* config/tc-mips.c (options): Remove OPTION_COMPAT_ARCH_BASE
enum value.
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Intel has disclosed a set of new instructions for Icelake processor.
The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
This patch enables Intel PCONFIG instruction.
gas/
* config/tc-i386.c (cpu_arch): Add .pconfig.
* doc/c-i386.texi: Document .pconfig.
* testsuite/gas/i386/i386.exp: Add PCONFIG tests.
* testsuite/gas/i386/pconfig-intel.d: New test.
* testsuite/gas/i386/pconfig.d: Likewise.
* testsuite/gas/i386/pconfig.s: Likewise.
* testsuite/gas/i386/x86-64-pconfig-intel.d: Likewise.
* testsuite/gas/i386/x86-64-pconfig.d: Likewise.
* testsuite/gas/i386/x86-64-pconfig.s: Likewise.
opcodes/
* i386-dis.c (enum): Add pconfig.
* i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
(cpu_flags): Add CpuPCONFIG.
* i386-opc.h (enum): Add CpuPCONFIG.
(i386_cpu_flags): Add cpupconfig.
* i386-opc.tbl: Add PCONFIG instruction.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
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Intel has disclosed a set of new instructions for Icelake processor.
The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
This patch enables Intel WBNOINVD instruction.
gas/
* config/tc-i386.c (cpu_arch): Add .wbnoinvd.
* doc/c-i386.texi: Document .wbnoinvd.
* testsuite/gas/i386/i386.exp: Add WBNOINVD tests.
* testsuite/gas/i386/wbnoinvd-intel.d: New test.
* testsuite/gas/i386/wbnoinvd.d: Likewise.
* testsuite/gas/i386/wbnoinvd.s: Likewise.
* testsuite/gas/i386/x86-64-wbnoinvd-intel.d: Likewise.
* testsuite/gas/i386/x86-64-wbnoinvd.d: Likewise.
* testsuite/gas/i386/x86-64-wbnoinvd.s: Likewise.
opcodes/
* i386-dis.c (enum): Add PREFIX_0F09.
* i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
(cpu_flags): Add CpuWBNOINVD.
* i386-opc.h (enum): Add CpuWBNOINVD.
(i386_cpu_flags): Add cpuwbnoinvd.
* i386-opc.tbl: Add WBNOINVD instruction.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
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Remove an issue with `as --help' always reporting `o32' as the default
ABI regardless of what the default actually is, originally caused by
commit cac012d6d394 ("check mips abi x linker emulation compatibility"),
<https://sourceware.org/ml/binutils/2003-05/msg00187.html> missing an
update here.
gas/
* config/tc-mips.c (md_show_usage): Correctly indicate the
configuration-specific default ABI.
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Correct a commit 25499ac7ee92 ("MIPS16e2: Add MIPS16e2 ASE support") GAS
bug and add missing help text for the `-mmips16e2' and `-mno-mips16e2'
options added with said commit.
gas/
* config/tc-mips.c (md_show_usage): Report `-mmips16e2' and
`-mno-mips16e2' options.
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gas/
* doc/c-mips.texi (MIPS ASE Instruction Generation Overrides):
Correct syntax of the `.set nomips16e2' directive description.
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ie: \"
PR 22737
* config/tc-rx.c (rx_start_line): Handle escaped double-quote character.
* testsuite/gas/rx/pr22737.s: New test.
* testsuite/gas/rx/pr22737.d: Likewise.
* testsuite/gas/rx/rx.exp: Run the new test.
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Remove spurious comments after the definition of ToC and ToU.
2018-01-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (ToC macro): Remove spurious comment.
(ToU macro): Likewise.
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gas/
* config/tc-riscv.c (validate_riscv_insn) <'z'>: New.
(riscv_ip) <'z'>: New.
opcodes/
* riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
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The latest specification for Intel CET technology defined two
new bits instead of previously used CET bit. These are IBT and
SHSTK bits. The patch replaces CET bit with IBT and SHSTK bits.
gas/
* config/tc-i386.c (cpu_arch): Delete .cet. Add .ibt, .shstk.
(cpu_noarch): Add noibt, noshstk.
(parse_insn): Change cpucet to cpuibt.
* doc/c-i386.texi: Delete .cet. Add .ibt, .shstk.
* testsuite/gas/i386/cet-ibt-inval.l: New test.
* testsuite/gas/i386/cet-ibt-inval.s: Likewise.
* testsuite/gas/i386/cet-shstk-inval.l: Likewise.
* testsuite/gas/i386/cet-shstk-inval.s: Likewise.
* testsuite/gas/i386/x86-64-cet-ibt-inval.l: Likewise.
* testsuite/gas/i386/x86-64-cet-ibt-inval.s: Likewise.
* testsuite/gas/i386/x86-64-cet-shstk-inval.l: Likewise.
* testsuite/gas/i386/x86-64-cet-shstk-inval.s: Likewise.
opcodes/
* i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS,
CpuCET. Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
(cpu_flags): Add CpuIBT, CpuSHSTK.
* i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
(i386_cpu_flags): Add cpuibt, cpushstk.
* i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
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ld * po/pt_BR.po: Updated Brazilian Portugese translation.
opcodes * po/pt_BR.po: Updated Brazilian Portugese translation.
* po/de.po: Updated German translation.
gas * po/fr.po: Updated French translation.
binutils* po/fr.po: Updated French translation.
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gas/
* testsuite/gas/riscv/c-zero-imm.s: Test addi that compresses to c.nop.
* testsuite/gas/riscv/c-zero-imm.d: Likewise.
opcodes/
* riscv-opc.c (match_c_nop): New.
(riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
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Armv8-M Security Extensions introduced some Thumb-only opcodes
(eg. sg). These are defined using the TUE and TCE macros, setting the
Arm execution state related fields to 0/NULL.
This patch adds 2 new macros to avoid filling this field and clearly
identify Thumb-only instructions.
2018-01-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (ToC): Define macro.
(ToU): Likewise.
(insns): Make use of above macros for new instructions introduced in
Armv8-M.
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Newly introduced instructions common to ARMv8-M Baseline and Mainline
are currently all marked as unconditional. However, all instructions but
sg (ie. blxns, bxns, tt, ttt, tta, ttat, vlldm and vlstm) do actually
support conditional execution. This patch fixes the definition of these
instructions accordingly.
2018-01-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (insns): Make blxns, bxns, tt, ttt, tta, ttat, vlldm
and vlstm conditionally executable and reindent parameters.
* testsuite/gas/arm/archv8m-cmse-main.s: Add conditional version of
aforementionned instructions.
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Deprecations related to the use of the IT instruction introduced in
Armv8-A do not apply to Armv8-M Baseline and mainline. However the
warning logic do not distinguish between the various profiles and warn
whenever the architecture version is 8.
This patch adds a check to exclude M profile architectures from this
warning. This works as expected when -march is specified on the
command-line or a .arch/.cpu directive exist. However, in autodetection
mode the CPU/architecture targeted is only known once the instructions
have been all processed but this code is run when IT instruction is
processed. It is therefore not possible to distinguish between Armv8-M
and Armv8-A in that mode.
The approach chosen here is not to warn in autodetection mode. The udf.d
testcase that relied on that behavior to test deprecation warning for
Armv8-A is therefore updated to explicitely pass -march=armv8-a.
2018-01-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (it_fsm_post_encode): Do not warn if targeting M
profile architecture or if in autodetection mode. Clarify that
deprecation is for performance reason and concerns Armv8-A and Armv8-R.
* testsuite/gas/arm/armv8-ar-bad.l: Adapt to new IT deprecation warning
message.
* testsuite/gas/arm/armv8-ar-it-bad.l: Likewise.
* testsuite/gas/arm/sp-pc-validations-bad-t-v8a.l: Likewise.
* testsuite/gas/arm/udf.l: Likewise.
* testsuite/gas/arm/udf.d: Assemble for Armv8-A explicitely.
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bfd/
* version.m4: Bump version to 2.30.51
* configure: Regenerate.
binutils/
* configure: Regenerate.
gas/
* configure: Regenerate.
gprof/
* configure: Regenerate.
ld/
* configure: Regenerate.
opcodes/
* configure: Regenerate.
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binutils/
* NEWS: Add marker for 2.30.
gas/
* NEWS: Add marker for 2.30.
ld/
* NEWS: Add marker for 2.30.
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Occasionally I build an out-of-tree a.out target (m68k-amigaos). After
a system upgrade which included a newer compiler (clang 4) the build
produces warnings like this:
warning: macro expansion producing 'defined' has undefined behavior
[-Wexpansion-to-defined]
This is caused by the macro gas/config/aout_gnu.h:USE_EXTENDED_RELOC.
Since it is in a header file, the warning triggers for several files.
I am unsure what solution is preferable, thus I am suggesting two
patches:
a) keep the offending macro but define it explicitly to 0 and 1
b) replace the macro usage with its value where it is used.
Either patch removes the warning for clang. I did not check with a
recent GCC.
* gas/config/aout_gnu.h (USE_EXTENDED_RELOC): Explicitly
define to 0 and 1. Remove a dangling reference to "AMD 29000"
in a comment.
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AVX512_4FMAPS and AVX512_4VNNIW insns are marked as having AVX512VL
variants. That is wrong as SDM doesn't define such instructions. The
patch removes these VL variants.
gas/
* testsuite/gas/i386/avx512_4fmaps-warn.l: Change xmm to zmm.
* testsuite/gas/i386/avx512_4fmaps-warn.s: Likewise.
* testsuite/gas/i386/avx512_4fmaps_vl-intel.d: Delete.
* testsuite/gas/i386/avx512_4fmaps_vl-warn.l: Likewise.
* testsuite/gas/i386/avx512_4fmaps_vl-warn.s: Likewise.
* testsuite/gas/i386/avx512_4fmaps_vl.d: Likewise.
* testsuite/gas/i386/avx512_4fmaps_vl.s: Likewise.
* testsuite/gas/i386/avx512_4vnniw_vl-intel.d: Likewise.
* testsuite/gas/i386/avx512_4vnniw_vl.d: Likewise.
* testsuite/gas/i386/avx512_4vnniw_vl.s: Likewise.
* testsuite/gas/i386/i386.exp: Delete _vl tests for 4fmaps an
4vnniw tests.
* testsuite/gas/i386/x86-64-avx512_4fmaps_vl-intel.d: Delete.
* testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.l: Likewise.
* testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.s: Likewise.
* testsuite/gas/i386/x86-64-avx512_4fmaps_vl.d: Likewise.
* testsuite/gas/i386/x86-64-avx512_4fmaps_vl.s: Likewise.
* testsuite/gas/i386/x86-64-avx512_4vnniw_vl-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx512_4vnniw_vl.d: Likewise.
* testsuite/gas/i386/x86-64-avx512_4vnniw_vl.s: Likewise.
opcodes/
* i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW
insns.
* i386-tbl.h: Regenerate.
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* config/tc-arm.c (aeabi_set_public_attributes): Avoid false
positive "‘profile’ may be used uninitialized".
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