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2023-07-26bpf: fix register NEG[32] instructionsJose E. Marchesi14-16/+33
This patch fixes the BPF_INSN_NEGR and BPF_INSN_NEG32R BPF instructions to not use their source registers. Tested in bpf-unknown-none. opcodes/ChangeLog: 2023-07-26 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Fix BPF_INSN_NEGR to not use a src register. gas/ChangeLog: 2023-07-26 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/alu.s: The register neg instruction gets only one argument. * testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-pseudoc.s: Likewise. * testsuite/gas/bpf/alu-pseudoc.d: Likewise. * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise. * testsuite/gas/bpf/alu-pseudoc.s: Likewise. * testsuite/gas/bpf/alu-be.d: Likewise. * testsuite/gas/bpf/alu.d: Likewise. * testsuite/gas/bpf/alu32-be.d: Likewise. * testsuite/gas/bpf/alu32.d: Likewise. * testsuite/gas/bpf/alu32.s: Likewise. * doc/c-bpf.texi (BPF Instructions): Update accordingly.
2023-07-26Don't warn on .attach_to_group to same groupAlan Modra1-2/+3
* config/obj-elf.c (obj_elf_attach_to_group): Don't warn if group name matches current group for section.
2023-07-26bpf: format not a string literalAlan Modra1-1/+1
* config/tc-bpf.c (md_assemble): Correct as_bad call.
2023-07-25bpf: Add atomic compare-and-exchange instructionsDavid Faust7-4/+65
This patch adds the two remaining BPF v3 atomic instructions: - BPF_INSN_ACMP{,32}: atomic compare-and-swap - BPF_INSN_AXCHG{,32}: atomic (non-conditional) exchange Tests and documentation are also updated. gas/ * doc/c-bpf.texi (BPF Instructions): Document atomic exchange and atomic compare-and-swap instructions. * testsuite/gas/bpf/atomic.s: Test ACMP, ACMP32, AXCHG, AXCGH32 instructions. * testsuite/gas/bpf/atomic.d: Likewise. * testsuite/gas/bpf/atomic-be.d: Likewise. * testsuite/gas/bpf/atomic-pseudoc.s: Likewise. * testsuite/gas/bpf/atomic-pseudoc.d: Likewise. * testsuite/gas/bpf/atomic-be-pseudoc.d: Likewise. include/ * opcode/bpf.h (BPF_IMM32_ACMP): Fix typo. (enum bpf_insn_id): New entries for BPF_INSN_ACMP{,32} and BPF_INSN_AXCHG{,32}. opcodes/ * bpf-opc.c (bpf_opcodes): Add entries for ACMP{,32} and AXCHG{,32} instructions.
2023-07-25bpf: Update atomic instruction pseudo-C syntaxDavid Faust11-36/+155
This patch updates the pseudo-C dialect templates for the BPF v3 atomic instructions. The templates match the strings emitted by clang -S for these instructions. The tests and documentation are updated accordingly. gas/ * doc/c-bpf.texi (BPF Instructions): Update entries for atomic and 32-bit atomic instructions. * testsuite/gas/bpf/atomic.s: Test AAND, AAND32, AOR, AOR32, AXOR, AXOR32, AFADD, AFADD32, AFAND, AFAND32, AFOR, AFOR32, AFXOR and AFXOR32 instructions. * testsuite/gas/bpf/atomic.d: Likewise. * testsuite/gas/bpf/atomic-be.d: Likewise. * testsuite/gas/bpf/atomic-pseudoc.s: Likewise. * testsuite/gas/bpf/atomic-pseudoc.d: Likewise. * testsuite/gas/bpf/atomic-be-pseudoc.d: Likewise. * testsuite/gas/bpf/atomic-v1.s: New test. * testsuite/gas/bpf/atomic-v1.d: Likewise. * testuiste/gas/bpf/atomic-v1-be.d: Likewise. * testuiste/gas/bpf/bpf.exp: Run new tests. opcodes/ * bpf-opc.c (bpf_opcodes): Update pseudo-C dialect templates for: BPF_INSN_AADD, BPF_INSN_AOR, BPF_INSN_AAND, BPF_INSN_AXOR, BPF_INSN_AFADD, BPF_INSN_AFOR, BPF_INSN_AFAND, BPF_INSN_AFXOR, BPF_INSN_AADD32, BPF_INSN_AOR32, BPF_INSN_AAND32, BPF_INSN_AXOR32, BPF_INSN_AFADD32, BPF_INSN_AFOR32, BPF_INSN_AFAND32, and BPF_INSN_AFXOR32 instructions.
2023-07-25RISC-V: Enable RVC on ".option arch, +zca" etc.Tsukasa OI1-1/+2
Since the 'Zca' extension is the new base of the compressed instructions, this commit enables RVC *also* when the 'Zca' extension is enabled via ".option arch" directive. gas/ChangeLog: * config/tc-riscv.c (s_riscv_option): Enable RVC also when the 'Zca' extension is enabled after an ".option arch" directive.
2023-07-24RISC-V: Implications from 'Zc[fd]' extensionsTsukasa OI2-0/+12
The version 1.0.4-1 of the code size reduction specification clarifies that 'Zcf' implies 'F' and 'Zcd' implies 'D'. cf: <https://github.com/riscv/riscv-code-size-reduction/releases/tag/v1.0.4-1> This commit adds those implications. bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Add two implications, 'Zcf' -> 'F' and 'Zcd' -> 'D'. gas/ChangeLog: * testsuite/gas/riscv/march-imply-zcd.d: New test. * testsuite/gas/riscv/march-imply-zcf.d: New test.
2023-07-24RISC-V: Prohibit the 'Zcf' extension on RV64Tsukasa OI2-0/+5
As per: <https://github.com/riscv/riscv-code-size-reduction/issues/221>, the 'Zcf' extension does not exist on RV64. This is reflected on the version 1.0.4-1 of the code size reduction specification: <https://github.com/riscv/riscv-code-size-reduction/releases/tag/v1.0.4-1>. This commit prohibits the combination: RV64 (or any ISA with XLEN > 32) and the 'Zcf' extension. bfd/ChangeLog: * elfxx-riscv.c (riscv_parse_check_conflicts): Prohibit combination of RV64 and 'Zcf'. gas/ChangeLog: * testsuite/gas/riscv/march-fail-rv64i_zcf.d: New test. * testsuite/gas/riscv/march-fail-rv64i_zcf.l: Likewise.
2023-07-24bpf: gas,include,opcode: add suppor for instructions BSWAP{16,32,64}Jose E. Marchesi8-0/+48
This patch adds support for the BPF V4 ISA byte swap instructions to opcodes, assembler and disassembler. Tested in bpf-unknown-none. include/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/bpf.h (BPF_IMM32_BSWAP16): Define. (BPF_IMM32_BSWAP32): Likewise. (BPF_IMM32_BSWAP64): Likewise. (enum bpf_insn_id): New entries BPF_INSN_BSWAP{16,32,64}. opcodes/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Add entries for the BSWAP* instructions. gas/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * doc/c-bpf.texi (BPF Instructions): Document BSWAP* instructions. * testsuite/gas/bpf/alu.s: Test BSWAP{16,32,64} instructions. * testsuite/gas/bpf/alu.d: Likewise. * testsuite/gas/bpf/alu-be.d: Likewise. * testsuite/gas/bpf/alu-pseudoc.s: Likewise. * testsuite/gas/bpf/alu-pseudoc.d: Likewise. * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
2023-07-24bpf: gas: fix in manual that MOVS* pseudoc syntax uses = instead of s=Jose E. Marchesi2-6/+11
gas/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * doc/c-bpf.texi (BPF Instructions): The pseudoc syntax for MOVS* doesn't use `s=' but `='.
2023-07-24bpf: gas,opcodes: fix pseudoc syntax for MOVS* and LDXS* insnsJose E. Marchesi11-40/+54
This patch fixes the pseudoc syntax of the V4 instructions MOVS* and LDXS* in order to reflect https://reviews.llvm.org/D144829. opcodes/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Fix pseudo-c syntax for MOVS* and LDXS* instructions. gas/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * doc/c-bpf.texi (BPF Instructions): Fix pseudoc syntax for MOVS* and LDXS* instructions. * testsuite/gas/bpf/mem-pseudoc.d: Likewise. * testsuite/gas/bpf/mem-be-pseudoc.d: Likewise. * testsuite/gas/bpf/mem-pseudoc.s: Likewise. * testsuite/gas/bpf/alu-pseudoc.s: Likewise. * testsuite/gas/bpf/alu-pseudoc.d: Likewise. * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-pseudoc.s: Likewise. * testsuite/gas/bpf/alu32-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
2023-07-24bpf: add support for jal/gotol jump instruction with 32-bit targetJose E. Marchesi9-23/+69
This patch adds support for the V4 BPF instruction jal/gotol, which is like ja/goto but it supports a signed 32-bit PC-relative (in number of 64-bit words minus one) target operand instead of the 16-bit signed operand of the other instruction. This greatly increases the jump range in BPF programs. Tested in bpf-unkown-none. bfd/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * reloc.c: New reloc BFD_RELOC_BPF_DISPCALL32. * elf64-bpf.c (bpf_reloc_type_lookup): Handle the new reloc. * libbfd.h (bfd_reloc_code_real_names): Regenerate. gas/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c (struct bpf_insn): New field `id'. (md_assemble): Save the ids of successfully parsed instructions and use the new BFD_RELOC_BPF_DISPCALL32 whenever appropriate. (md_apply_fix): Adapt to the new BFD reloc. * testsuite/gas/bpf/jump.s: Test JAL. * testsuite/gas/bpf/jump.d: Likewise. * testsuite/gas/bpf/jump-pseudoc.d: Likewise. * testsuite/gas/bpf/jump-be.d: Likewise. * testsuite/gas/bpf/jump-be-pseudoc.d: Likewise. * doc/c-bpf.texi (BPF Instructions): Document new instruction jal/gotol. Document new operand type disp32. include/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/bpf.h (enum bpf_insn_id): Add entry BPF_INSN_JAL. (enum bpf_insn_id): Remove spurious entry BPF_INSN_CALLI. opcodes/ChangeLog: 2023-07-23 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Add entry for jal.
2023-07-21bpf: disasemble offsets of value 0 as "+0"David Faust6-2/+14
This tiny patch makes the BPF disassembler to emit, e.g. ldxdw %r1, [%r0+0] instead of ldxdw %r1, [%r00] when the offset is 0, to avoid confusion. opcodes/ * bpf-dis.c (print_insn_bpf): Print offsets with value 0 as "+0". gas/ * testsuite/gas/bpf/mem.s: Add tests with offset 0. * testsuite/gas/bpf/mem-pseudoc.s: Likewise. * testsuite/gas/bpf/mem.d: Update accordingly. * testsuite/gas/bpf/mem-be.d: Likewise. * testsuite/gas/bpf/mem-pseudoc.d: Likewise. * testsuite/gas/bpf/mem-be-pseudoc.d: Likewise.
2023-07-21bpf: opcodes, gas: support for signed load V4 instructionsJose E. Marchesi8-0/+54
This commit adds the signed load to register (ldxs*) instructions introduced in the BPF ISA version 4, including opcodes and assembler tests. Tested in bpf-unknown-none. include/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/bpf.h (enum bpf_insn_id): Add entries for signed load instructions. (BPF_MODE_SMEM): Define. opcodes/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Add entries for LDXS{B,W,H,DW} instructions. gas/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/mem.s: Add signed load instructions. * testsuite/gas/bpf/mem-pseudoc.s: Likewise. * testsuite/gas/bpf/mem.d: Likewise. * testsuite/gas/bpf/mem-pseudoc.d: Likewise. * testsuite/gas/bpf/mem-be.d: Likewise. * doc/c-bpf.texi (BPF Instructions): Document the signed load instructions.
2023-07-21bpf: opcodes, gas: support for signed register move V4 instructionsJose E. Marchesi14-0/+75
This commit adds the signed register move (movs) instructions introduced in the BPF ISA version 4, including opcodes and assembler tests. Tested in bpf-unknown-none. include/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/bpf.h (BPF_OFFSET16_MOVS8): Define. (BPF_OFFSET16_MOVS16): Likewise. (BPF_OFFSET16_MOVS32): Likewise. (enum bpf_insn_id): Add entries for MOVS{8,16,32}R and MOVS32{8,16,32}R. opcodes/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Add entries for MOVS{8,16,32}R and MOVS32{8,16,32}R instructions. and MOVS32I instructions. gas/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/alu.s: Test movs instructions. * testsuite/gas/bpf/alu-pseudoc.s: Likewise. * testsuite/gas/bpf/alu32.s: Likewise for movs32 instruction. * testsuite/gas/bpf/alu32-pseudoc.s: Likewise. * testsuite/gas/bpf/alu.d: Add expected results. * testsuite/gas/bpf/alu32.d: Likewise. * testsuite/gas/bpf/alu-be.d: Likewise. * testsuite/gas/bpf/alu32-be.d: Likewise. * testsuite/gas/bpf/alu-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-pseudoc.d: Likewise. * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
2023-07-21DesCGENization of the BPF binutils portJose E. Marchesi75-3109/+2432
CGEN is cool, but the BPF architecture is simply too bizarre for it. The weird way of BPF to handle endianness in instruction encoding, the weird C-like alternative assembly syntax, the weird abuse of multi-byte (or infra-byte) instruction fields as opcodes, the unusual presence of opcodes beyond the first 32-bits of some instructions, are all examples of what makes it a PITA to continue using CGEN for this port. The bpf.cpu file is becoming so complex and so nested with p-macros that it is very difficult to read, and quite challenging to update. Also, every time we are forced to change something in CGEN to accommodate BPF requirements (which is often) we have to do extensive testing to make sure we do not break any other target using CGEN. This is getting un-maintenable. So I have decided to bite the bullet and revamp/rewrite the port so it no longer uses CGEN. Overall, this involved: * To remove the cpu/bpf.{cpu,opc} descriptions. * To remove the CGEN generated files. * To replace the CGEN generated opcodes table with a new hand-written opcodes table for BPF. * To replace the CGEN generated disassembler wih a new disassembler that uses the new opcodes. * To replace the CGEN generated assembler with a new assembler that uses the new opcodes. * To replace the CGEN generated simulator with a new simulator that uses the new opcodes. [This is pushed in GDB in another patch.] * To adapt the build systems to the new situation. Additionally, this patch introduces some extensions and improvements: * A new BPF relocation BPF_RELOC_BPF_DISP16 plus corresponding ELF relocation R_BPF_GNU_64_16 are added to the BPF BFD port. These relocations are used for section-relative 16-bit offsets used in load/store instructions. * The disassembler now has support for the "pseudo-c" assembly syntax of BPF. What dialect to use when disassembling is controlled by a command line option. * The disassembler now has support for dumping instruction immediates in either octal, hexadecimal or decimal. The used output base is controlled by a new command-line option. * The GAS BPF test suite has been re-structured and expanded in order to test the disassembler pseudoc syntax support. Minor bugs have been also fixed there. The assembler generic tests that were disabled for bpf-*-* targets due to the previous implementation of pseudoc syntax are now re-enabled. Additional tests have been added to test the new features of the assembler. .dump files are no longer used. * The linker BPF test suite has been adapted to the command line options used by the new disassembler. The result is very satisfactory. This patchs adds 3448 lines of code and removes 10542 lines of code. Tested in: * Target bpf-unknown-none with 64-bit little-endian host and 32-bit little-endian host. * Target x86-64-linux-gnu with --enable-targets=all Note that I have not tested in a big-endian host yet. I will do so once this lands upstream so I can use the GCC compiler farm. I have not included ChangeLog entries in this patch: these would be massive and not very useful, considering this is pretty much a rewrite of the port. I beg the indulgence of the global maintainers.
2023-07-21x86: adjust disassembly of insns operating on selector valuesJan Beulich12-118/+119
Bring disassembly back in line with what the assembler accepts, thus also making it self-consistent (with, in particular selector load/store insns). While there further add D to all affected insns except ARPL (where S is used, matching LAR/LSL), to also behave correctly in suffix- always mode. While there also hook up the Intel variant of the LKGS test.
2023-07-19gas 32-bit host compile warningsAlan Modra5-19/+26
* config/tc-d10v.c (find_opcode): Correct format specifier vs. arg mismatch. * config/tc-m68hc11.c (fixup8, fixup16, fixup24, fixup8_xg): Likewise. * config/tc-vax.c (md_assemble): Likewise. * config/tc-xtensa.c (dump_litpools): Likewise. * config/tc-z80.c (emit_data_val, emit_byte): Likewise.
2023-07-18RISC-V: Supports Zcb extension.Jiawei3-0/+110
This patch support Zcb extension, contains new compressed instructions, some instructions depend on other existed extension, like 'zba', 'zbb' and 'zmmul'. Zcb also imply Zca extension to enable the compressing features. Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com> Co-Authored by: Mary Bennett <mary.bennett@embecosm.com> Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com> Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com> Co-Authored by: Simon Cook <simon.cook@embecosm.com> Co-Authored by: Shihua Liao <shihua@iscas.ac.cn> Co-Authored by: Yulong Shi <yulong@iscas.ac.cn> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): New extension. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): New operators. (riscv_ip): Ditto. * testsuite/gas/riscv/zcb.d: New test. * testsuite/gas/riscv/zcb.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_C_LBU): New opcode. (MASK_C_LBU): New mask. (MATCH_C_LHU): New opcode. (MASK_C_LHU): New mask. (MATCH_C_LH): New opcode. (MASK_C_LH): New mask. (MATCH_C_SB): New opcode. (MASK_C_SB): New mask. (MATCH_C_SH): New opcode. (MASK_C_SH): New mask. (MATCH_C_ZEXT_B): New opcode. (MASK_C_ZEXT_B): New mask. (MATCH_C_SEXT_B): New opcode. (MASK_C_SEXT_B): New mask. (MATCH_C_ZEXT_H): New opcode. (MASK_C_ZEXT_H): New mask. (MATCH_C_SEXT_H): New opcode. (MASK_C_SEXT_H): New mask. (MATCH_C_ZEXT_W): New opcode. (MASK_C_ZEXT_W): New mask. (MATCH_C_NOT): New opcode. (MASK_C_NOT): New mask. (MATCH_C_MUL): New opcode. (MASK_C_MUL): New mask. (DECLARE_INSN): New opcode. * opcode/riscv.h (EXTRACT_ZCB_BYTE_UIMM): New inline func. (EXTRACT_ZCB_HALFWORD_UIMM): Ditto. (ENCODE_ZCB_BYTE_UIMM): Ditto. (ENCODE_ZCB_HALFWORD_UIMM): Ditto. (VALID_ZCB_BYTE_UIMM): Ditto. (VALID_ZCB_HALFWORD_UIMM): Ditto. (enum riscv_insn_class): New extension class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): New operators. * riscv-opc.c: New instructions.
2023-07-18RISC-V: Support Zca/f/d extensions.Jiawei7-1/+155
This patch add Zca/f/d extensions support, since all ZC* extensions will imply Zca extension, just enabled compress feature when Zca extension is available. Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com> Co-Authored by: Mary Bennett <mary.bennett@embecosm.com> Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com> Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com> Co-Authored by: Simon Cook <simon.cook@embecosm.com> Co-Authored by: Shihua Liao <shihua@iscas.ac.cn> Co-Authored by: Yulong Shi <yulong@iscas.ac.cn> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): New extensions. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * config/tc-riscv.c (riscv_set_arch): Extend compress check. * testsuite/gas/riscv/zca.d: New test. * testsuite/gas/riscv/zca.s: New test. * testsuite/gas/riscv/zcd.d: New test. * testsuite/gas/riscv/zcd.s: New test. * testsuite/gas/riscv/zcf.d: New test. * testsuite/gas/riscv/zcf.s: New test.
2023-07-14Make the default gas symbol hash table largerAlan Modra1-1/+1
We may as well start with the symbol table a little larger, saving time resizing. Even a simple C hello world compiled with -O2 -g will exceed 16 symbols (by well over 3 times with gcc-11). * symbols.c (symbol_begin): Create sy_hash with more entries.
2023-07-14AIX_WEAK_SUPPORTAlan Modra3-2/+13
Making target code depend on a host define like _AIX52 is never correct, so out it goes. Also, sort some config.bfd entries a little to make it more obvious there is a config difference between aix5.1 and aix5.2. These two changes should make no difference to anything in binutils. The gas define of AIX_WEAK_SUPPORT on the other hand was wrong, so fix that. Finally, fix some testsuite fails on aix < 5.2 by simply not running the tests. include/ * coff/internal.h (C_WEAKEXT): Don't depend on _AIX52. bfd/ * coffcode.h (coff_slurp_symbol_table): Don't depend on _AIX52. (coff_classify_symbol): Likewise. * config.bfd: Sort some entries. gas/ * configure.ac (AIX_WEAK_SUPPORT): Don't set for aix5.[01]. * configure: Regenerate. * testsuite/gas/ppc/aix.exp (xcoff-visibility-1*) Don't run for aix < 5.2.
2023-07-11x86: various operations on mask registers can avoid going through mod_table[]Jan Beulich4-414/+414
Now that we have OP_R(), use it here as well, while wiring memory-only operands to OP_M() at the same time. To keep the number of consumed opcode bytes similar to before, make BadOp() also account for VEX/XOP/ EVEX prefix bytes. To keep that change simple, convert need_vex to an actual count of prefix bytes (keeping intact all prior boolean uses of the field). Note how this improves disassembly of such bad encodings, by at least leaving a hint towards what a "nearby" instruction is. (For KSHIFT* change the immediates test testcases use, such that disassembly remains sufficiently in sync.) While there also use Ux for VPMOV{B,W,D,Q}2M, where decoding through mod_table[] was missing in the earlier scheme.
2023-07-11x86: misc further memory-only insns don't need to go through mod_table[]Jan Beulich2-4/+4
Several already use OP_M(), which rejects the register forms of insns, and a few others can easily be converted to do so as well. (Note that FXSAVE_Fixup() wires through to OP_M(). Note further that OP_IndirE(), which wasn't placed very well anyway, is moved down to avoid the need to forward-declare BadOp().) Also adjust formatting of and drop PREFIX_OPCODE from a few adjacent entries.
2023-07-07Udated Freach and Romainian translations for various sub-directoriesNick Clifton1-2537/+2826
2023-07-04x86: optimize 128-bit VPBROADCASTQ to VPUNPCKLQDQJan Beulich7-0/+38
The alternative is 1 byte shorter when the source is %xmm0-7, as a 2-byte VEX prefix can then be used.
2023-07-04x86: optimize pre-AVX512 {,V}PCMPGT* with identical sourcesJan Beulich14-0/+464
These are better expressed by the zeroing idiom {,V}PXOR. In some cases this also results in a shorter encoding.
2023-07-04x86: optimize pre-AVX512 {,V}PCMPEQQ with identical sourcesJan Beulich7-0/+47
The {,V}PCMPEQD alternative is 1 byte shorter in many cases.
2023-07-04x86: flag bad EVEX masking for miscellaneous insnsJan Beulich2-0/+4
Masking is not permitted for certain further insns, not falling in any of the earlier categories. Introduce the Y macro (not expanding to any output) to flag such cases. Note that in a few cases entries already covered otherwise are converted as well, to continue to allow sharing of the string literals.
2023-07-04x86: flag EVEX masking when destination is GPR(-like)Jan Beulich2-0/+8
Masking is not permitted in this case. See the code comment for how this is being dealt with. To avoid excess special casing of modes, have OP_M() call OP_E_memory() directly.
2023-07-04x86: flag EVEX.z set when destination is memoryJan Beulich2-0/+4
Zeroing-masking is not permitted in this case. See the code comment for how this is being dealt with.
2023-07-04x86: flag EVEX.z set when destination is a mask registerJan Beulich2-0/+4
While only zeroing-masking is possible in this case, this still requires EVEX.z to be clear. Introduce a "global" flag right here, to be re-used by checks which need to live in specific operand handlers.
2023-07-04x86: re-work EVEX-z-without-masking checkJan Beulich1-2/+1
Rather than corrupting disassmbly altogether, flag EVEX.z set as bad when masking isn't in effect in the first place at the time the destination operand is actually processed.
2023-07-04Updated Ukranian, Romanian and German translations for various sub-directoriesNick Clifton1-2537/+2826
2023-07-04arc: Update default target CPU to match GCC defaultsClaudiu Zissulescu1-1/+1
Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
2023-07-03IBM Z: Fix pcrel relocs for symA-symB expressionsAndreas Krebbel2-5/+11
The code in md_apply_fix which tries to deduce from the operand type which reloc to apply currently does the wrong thing for absolute relocs which have been re-written by fixup_segment as pc-relative to implement a subtraction of a local and an external symbol. In all these cases we wrongly emit an absolute reloc because we ignore the fx_pcrel flag in md_apply_fix. However, only for the last one we actually support a pc relative relocation of the proper size and can implement it accordingly. For the other 3 we have to issue an error. foo: cli 0(%r2),undef-foo la %r2,undef-foo(%r2) lay %r2,undef-foo(%r2) lhi %r2,undef-foo
2023-07-03Change version number to 2.41.50 and regenerate filesNick Clifton3-2493/+2681
2023-07-03Add markers for the 2.41 branchNick Clifton2-0/+6
2023-07-03gas: NEWS: Announce LoongArch changes in the 2.41 cycleWANG Xuerui1-0/+12
gas/ChangeLog: * NEWS: Mention LoongArch changes for 2.41. Signed-off-by: WANG Xuerui <git@xen0n.name>
2023-07-03LoongArch: gas: Fix shared buildsWANG Xuerui1-1/+0
Formerly an include of libbfd.h was added in commit 56576f4a722 ("LoongArch: gas: Add support for linker relaxation."), in order to allow calling _bfd_read_unsigned_leb128 from gas, but doing so broke shared builds. Commit d2fddb6d783 fixed this reference but did not remove the now unnecessary inclusion of libbfd.h. The gas_assert macro expands into a conditional call to abort(), but "abort" is re-defined to _bfd_abort in libbfd.h, so the extra include breaks any gas_assert usage, and should be removed. gas/ChangeLog: * config/tc-loongarch.c: Don't include libbfd.h. Fixes: d2fddb6d783 ("LoongArch: Fix ld "undefined reference" error with --enable-shared") Signed-off-by: WANG Xuerui <git@xen0n.name>
2023-07-01RISC-V: Add support for the Zvksc ISA extensionNathan Huckleberry2-0/+28
Zvksc is part of the vector crypto extensions. Zvksc is shorthand for the following set of extensions: - Zvks - Zvbc bfd/ChangeLog: * elfxx-riscv.c: Define Zvksc extension. gas/ChangeLog: * testsuite/gas/riscv/zvksc.d: New test. * testsuite/gas/riscv/zvksc.s: New test. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvknc ISA extensionNathan Huckleberry2-0/+28
Zvknc is part of the vector crypto extensions. Zvknc is shorthand for the following set of extensxions: - Zvkn - Zvbc bfd/ChangeLog: * elfxx-riscv.c: Define Zvknc extension. gas/ChangeLog: * testsuite/gas/riscv/zvknc.d: New test. * testsuite/gas/riscv/zvknc.s: New test. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvksg ISA extensionNathan Huckleberry2-0/+16
Zvksg is part of the vector crypto extensions. Zvksg is shorthand for the following set of extensions: - Zvks - Zvkg bfd/ChangeLog: * elfxx-riscv.c: Define Zvksg extension. gas/ChangeLog: * testsuite/gas/riscv/zvksg.d: New test. * testsuite/gas/riscv/zvksg.s: New test. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvks ISA extensionChristoph Müllner2-0/+81
Zvks is part of the vector crypto extensions. Zvks is shorthand for the following set of extensions: - Zvksed - Zvksh - Zvbb - Zvkt bfd/ChangeLog: * elfxx-riscv.c: Define Zvks extension. gas/ChangeLog: * testsuite/gas/riscv/zvks.d: New test. * testsuite/gas/riscv/zvks.s: New test. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvkng ISA extensionNathan Huckleberry2-0/+16
Zvkng is part of the vector crypto extensions. Zvkng is shorthand for the following set of extensions: - Zvkn - Zvkg bfd/ChangeLog: * elfxx-riscv.c: Define Zvkng extension. gas/ChangeLog: * testsuite/gas/riscv/zvkng.d: New test. * testsuite/gas/riscv/zvkng.s: New test. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvkn ISA extensionChristoph Müllner2-0/+81
Zvkn is part of the vector crypto extensions. Zvkn is shorthand for the following set of extensions: - Zvkned - Zvknhb - Zvbb - Zvkt bfd/ChangeLog: * elfxx-riscv.c: Define Zvkn extension. gas/ChangeLog: * testsuite/gas/riscv/zvkn.d: New test. * testsuite/gas/riscv/zvkn.s: New test. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvksh ISA extensionChristoph Müllner2-0/+14
Zvksh is part of the vector crypto extensions. This extension adds the following instructions: - vsm3me.vv - vsm3c.vi bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvksh. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zvksh.d: New test. * testsuite/gas/riscv/zvksh.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VSM3C_VI): New. (MASK_VSM3C_VI): New. (MATCH_VSM3ME_VV): New. (MASK_VSM3ME_VV): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction class support for Zvksh. opcodes/ChangeLog: * riscv-opc.c: Add Zvksh instructions. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvksed ISA extensionChristoph Müllner2-0/+16
Zvksed is part of the vector crypto extensions. This extension adds the following instructions: - vsm4k.vi - vsm4r.[vv,vs] bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvksed. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zvksed.d: New test. * testsuite/gas/riscv/zvksed.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VSM4K_VI): New. (MASK_VSM4K_VI): New. (MATCH_VSM4R_VS): New. (MASK_VSM4R_VS): New. (MATCH_VSM4R_VV): New. (MASK_VSM4R_VV): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction class support for Zvksed. opcodes/ChangeLog: * riscv-opc.c: Add Zvksed instructions. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvknh[a,b] ISA extensionsChristoph Müllner3-0/+27
Zvknh[a,b] are parts of the vector crypto extensions. This extension adds the following instructions: - vsha2ms.vv - vsha2c[hl].vv bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvknh[a,b]. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zvknha.d: New test. * testsuite/gas/riscv/zvknha_zvknhb.s: New test. * testsuite/gas/riscv/zvknhb.d: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VSHA2CH_VV): New. (MASK_VSHA2CH_VV): New. (MATCH_VSHA2CL_VV): New. (MASK_VSHA2CL_VV): New. (MATCH_VSHA2MS_VV): New. (MASK_VSHA2MS_VV): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction class support for Zvknh[a,b]. opcodes/ChangeLog: * riscv-opc.c: Add Zvknh[a,b] instructions. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvkned ISA extensionChristoph Müllner2-0/+34
Zvkned is part of the vector crypto extensions. This extension adds the following instructions: - vaesef.[vv,vs] - vaesem.[vv,vs] - vaesdf.[vv,vs] - vaesdm.[vv,vs] - vaeskf1.vi - vaeskf2.vi - vaesz.vs bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvkned. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zvkned.d: New test. * testsuite/gas/riscv/zvkned.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VAESDF_VS): New. (MASK_VAESDF_VS): New. (MATCH_VAESDF_VV): New. (MASK_VAESDF_VV): New. (MATCH_VAESDM_VS): New. (MASK_VAESDM_VS): New. (MATCH_VAESDM_VV): New. (MASK_VAESDM_VV): New. (MATCH_VAESEF_VS): New. (MASK_VAESEF_VS): New. (MATCH_VAESEF_VV): New. (MASK_VAESEF_VV): New. (MATCH_VAESEM_VS): New. (MASK_VAESEM_VS): New. (MATCH_VAESEM_VV): New. (MASK_VAESEM_VV): New. (MATCH_VAESKF1_VI): New. (MASK_VAESKF1_VI): New. (MATCH_VAESKF2_VI): New. (MASK_VAESKF2_VI): New. (MATCH_VAESZ_VS): New. (MASK_VAESZ_VS): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction class support for Zvkned. opcodes/ChangeLog: * riscv-opc.c: Add Zvkned instructions. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
generated by cgit v1.1 at 2024-11-17 09:54:42 +0000