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author | Jose E. Marchesi <jose.marchesi@oracle.com> | 2023-07-21 17:22:58 +0200 |
---|---|---|
committer | Jose E. Marchesi <jose.marchesi@oracle.com> | 2023-07-21 20:00:30 +0200 |
commit | 2f3dbc5fb5e781fc17d8f68f9c960a993f06d801 (patch) | |
tree | ca0207b2bc57f92ca9a581c4e00faad20f9e7a0e /gas | |
parent | 01deb24db99ea7909a30679ddb3cd4cba7b14fc7 (diff) | |
download | gdb-2f3dbc5fb5e781fc17d8f68f9c960a993f06d801.zip gdb-2f3dbc5fb5e781fc17d8f68f9c960a993f06d801.tar.gz gdb-2f3dbc5fb5e781fc17d8f68f9c960a993f06d801.tar.bz2 |
bpf: opcodes, gas: support for signed register move V4 instructions
This commit adds the signed register move (movs) instructions
introduced in the BPF ISA version 4, including opcodes and assembler
tests.
Tested in bpf-unknown-none.
include/ChangeLog:
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/bpf.h (BPF_OFFSET16_MOVS8): Define.
(BPF_OFFSET16_MOVS16): Likewise.
(BPF_OFFSET16_MOVS32): Likewise.
(enum bpf_insn_id): Add entries for MOVS{8,16,32}R and
MOVS32{8,16,32}R.
opcodes/ChangeLog:
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-opc.c (bpf_opcodes): Add entries for MOVS{8,16,32}R and
MOVS32{8,16,32}R instructions. and MOVS32I instructions.
gas/ChangeLog:
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/bpf/alu.s: Test movs instructions.
* testsuite/gas/bpf/alu-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu32.s: Likewise for movs32 instruction.
* testsuite/gas/bpf/alu32-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu.d: Add expected results.
* testsuite/gas/bpf/alu32.d: Likewise.
* testsuite/gas/bpf/alu-be.d: Likewise.
* testsuite/gas/bpf/alu32-be.d: Likewise.
* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu32-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
Diffstat (limited to 'gas')
-rw-r--r-- | gas/ChangeLog | 15 | ||||
-rw-r--r-- | gas/doc/c-bpf.texi | 24 | ||||
-rw-r--r-- | gas/testsuite/gas/bpf/alu-be-pseudoc.d | 3 | ||||
-rw-r--r-- | gas/testsuite/gas/bpf/alu-be.d | 3 | ||||
-rw-r--r-- | gas/testsuite/gas/bpf/alu-pseudoc.d | 3 | ||||
-rw-r--r-- | gas/testsuite/gas/bpf/alu-pseudoc.s | 3 | ||||
-rw-r--r-- | gas/testsuite/gas/bpf/alu.d | 3 | ||||
-rw-r--r-- | gas/testsuite/gas/bpf/alu.s | 3 | ||||
-rw-r--r-- | gas/testsuite/gas/bpf/alu32-be-pseudoc.d | 3 | ||||
-rw-r--r-- | gas/testsuite/gas/bpf/alu32-be.d | 3 | ||||
-rw-r--r-- | gas/testsuite/gas/bpf/alu32-pseudoc.d | 3 | ||||
-rw-r--r-- | gas/testsuite/gas/bpf/alu32-pseudoc.s | 3 | ||||
-rw-r--r-- | gas/testsuite/gas/bpf/alu32.d | 3 | ||||
-rw-r--r-- | gas/testsuite/gas/bpf/alu32.s | 3 |
14 files changed, 75 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 3d22461..66c95a1 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,18 @@ +2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> + + * testsuite/gas/bpf/alu.s: Test movs instructions. + * testsuite/gas/bpf/alu-pseudoc.s: Likewise. + * testsuite/gas/bpf/alu32.s: Likewise for movs32 instruction. + * testsuite/gas/bpf/alu32-pseudoc.s: Likewise. + * testsuite/gas/bpf/alu.d: Add expected results. + * testsuite/gas/bpf/alu32.d: Likewise. + * testsuite/gas/bpf/alu-be.d: Likewise. + * testsuite/gas/bpf/alu32-be.d: Likewise. + * testsuite/gas/bpf/alu-pseudoc.d: Likewise. + * testsuite/gas/bpf/alu32-pseudoc.d: Likewise. + * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise. + * testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise. + 2023-07-03 Nick Clifton <nickc@redhat.com> * configure: Regenerate. diff --git a/gas/doc/c-bpf.texi b/gas/doc/c-bpf.texi index 4742f89..a3814e9 100644 --- a/gas/doc/c-bpf.texi +++ b/gas/doc/c-bpf.texi @@ -259,6 +259,18 @@ ambiguity in the pseudoc syntax. @itemx rd = imm32 Move the 64-bit value of @code{rs} in @code{rd}, or load @code{imm32} in @code{rd}. + +@item movs rd, rs, 8 +@itemx rd s= (i8) rs +Move the sign-extended 8-bit value in @code{rs} to @code{rd}. + +@item movs rd, rs, 16 +@itemx rd s= (i16) rs +Move the sign-extended 16-bit value in @code{rs} to @code{rd}. + +@item movs rd, rs, 32 +@itemx rd s= (i32) rs +Move the sign-extended 32-bit value in @code{rs} to @code{rd}. @end table @subsection 32-bit arithmetic instructions @@ -354,6 +366,18 @@ ambiguity in the pseudoc syntax. @itemx rd = imm32 Move the 32-bit value of @code{rs} in @code{rd}, or load @code{imm32} in @code{rd}. + +@item mov32s rd, rs, 8 +@itemx rd s= (i8) rs +Move the sign-extended 8-bit value in @code{rs} to @code{rd}. + +@item mov32s rd, rs, 16 +@itemx rd s= (i16) rs +Move the sign-extended 16-bit value in @code{rs} to @code{rd}. + +@item mov32s rd, rs, 32 +@itemx rd s= (i32) rs +Move the sign-extended 32-bit value in @code{rs} to @code{rd}. @end table @subsection Endianness conversion instructions diff --git a/gas/testsuite/gas/bpf/alu-be-pseudoc.d b/gas/testsuite/gas/bpf/alu-be-pseudoc.d index 8d8c29e..486d792 100644 --- a/gas/testsuite/gas/bpf/alu-be-pseudoc.d +++ b/gas/testsuite/gas/bpf/alu-be-pseudoc.d @@ -63,3 +63,6 @@ Disassembly of section .text: 1a0: dc 60 00 00 00 00 00 10 r6=be16 r6 1a8: dc 50 00 00 00 00 00 20 r5=be32 r5 1b0: dc 40 00 00 00 00 00 40 r4=be64 r4 + 1b8: bf 12 00 08 00 00 00 00 r1 s= \(i8\) r2 + 1c0: bf 12 00 10 00 00 00 00 r1 s= \(i16\) r2 + 1c8: bf 12 00 20 00 00 00 00 r1 s= \(i32\) r2 diff --git a/gas/testsuite/gas/bpf/alu-be.d b/gas/testsuite/gas/bpf/alu-be.d index 170db4b..a082c46 100644 --- a/gas/testsuite/gas/bpf/alu-be.d +++ b/gas/testsuite/gas/bpf/alu-be.d @@ -63,3 +63,6 @@ Disassembly of section .text: 1a0: dc 60 00 00 00 00 00 10 endbe %r6,16 1a8: dc 50 00 00 00 00 00 20 endbe %r5,32 1b0: dc 40 00 00 00 00 00 40 endbe %r4,64 + 1b8: bf 12 00 08 00 00 00 00 movs %r1,%r2,8 + 1c0: bf 12 00 10 00 00 00 00 movs %r1,%r2,16 + 1c8: bf 12 00 20 00 00 00 00 movs %r1,%r2,32 diff --git a/gas/testsuite/gas/bpf/alu-pseudoc.d b/gas/testsuite/gas/bpf/alu-pseudoc.d index 5d69e68..cf1ef2a 100644 --- a/gas/testsuite/gas/bpf/alu-pseudoc.d +++ b/gas/testsuite/gas/bpf/alu-pseudoc.d @@ -63,3 +63,6 @@ Disassembly of section .text: 1a0: dc 06 00 00 10 00 00 00 r6=be16 r6 1a8: dc 05 00 00 20 00 00 00 r5=be32 r5 1b0: dc 04 00 00 40 00 00 00 r4=be64 r4 + 1b8: bf 21 08 00 00 00 00 00 r1 s= \(i8\) r2 + 1c0: bf 21 10 00 00 00 00 00 r1 s= \(i16\) r2 + 1c8: bf 21 20 00 00 00 00 00 r1 s= \(i32\) r2 diff --git a/gas/testsuite/gas/bpf/alu-pseudoc.s b/gas/testsuite/gas/bpf/alu-pseudoc.s index a271bef..513c8b8 100644 --- a/gas/testsuite/gas/bpf/alu-pseudoc.s +++ b/gas/testsuite/gas/bpf/alu-pseudoc.s @@ -55,3 +55,6 @@ r6 = be16 r6 r5 = be32 r5 r4 = be64 r4 + r1 s= (i8) r2 + r1 s= (i16) r2 + r1 s= (i32) r2 diff --git a/gas/testsuite/gas/bpf/alu.d b/gas/testsuite/gas/bpf/alu.d index 476891b..409018d 100644 --- a/gas/testsuite/gas/bpf/alu.d +++ b/gas/testsuite/gas/bpf/alu.d @@ -63,3 +63,6 @@ Disassembly of section .text: 1a0: dc 06 00 00 10 00 00 00 endbe %r6,16 1a8: dc 05 00 00 20 00 00 00 endbe %r5,32 1b0: dc 04 00 00 40 00 00 00 endbe %r4,64 + 1b8: bf 21 08 00 00 00 00 00 movs %r1,%r2,8 + 1c0: bf 21 10 00 00 00 00 00 movs %r1,%r2,16 + 1c8: bf 21 20 00 00 00 00 00 movs %r1,%r2,32 diff --git a/gas/testsuite/gas/bpf/alu.s b/gas/testsuite/gas/bpf/alu.s index bb3f926..6f8c30f 100644 --- a/gas/testsuite/gas/bpf/alu.s +++ b/gas/testsuite/gas/bpf/alu.s @@ -55,3 +55,6 @@ endbe %r6,16 endbe %r5,32 endbe %r4,64 + movs %r1,%r2,8 + movs %r1,%r2,16 + movs %r1,%r2,32 diff --git a/gas/testsuite/gas/bpf/alu32-be-pseudoc.d b/gas/testsuite/gas/bpf/alu32-be-pseudoc.d index 6daad3b..79a638f 100644 --- a/gas/testsuite/gas/bpf/alu32-be-pseudoc.d +++ b/gas/testsuite/gas/bpf/alu32-be-pseudoc.d @@ -57,3 +57,6 @@ Disassembly of section .text: 170: c4 40 00 00 7e ad be ef w4 s>>=0x7eadbeef 178: cc 56 00 00 00 00 00 00 w5 s>>=w6 180: 8c 23 00 00 00 00 00 00 w2=-w3 + 188: bc 12 00 08 00 00 00 00 w1 s= \(i8\) w2 + 190: bc 12 00 10 00 00 00 00 w1 s= \(i16\) w2 + 198: bc 12 00 20 00 00 00 00 w1 s= \(i32\) w2 diff --git a/gas/testsuite/gas/bpf/alu32-be.d b/gas/testsuite/gas/bpf/alu32-be.d index 6de8f06..0549bf2 100644 --- a/gas/testsuite/gas/bpf/alu32-be.d +++ b/gas/testsuite/gas/bpf/alu32-be.d @@ -57,3 +57,6 @@ Disassembly of section .text: 170: c4 40 00 00 7e ad be ef arsh32 %r4,0x7eadbeef 178: cc 56 00 00 00 00 00 00 arsh32 %r5,%r6 180: 8c 23 00 00 00 00 00 00 neg32 %r2,%r3 + 188: bc 12 00 08 00 00 00 00 movs32 %r1,%r2,8 + 190: bc 12 00 10 00 00 00 00 movs32 %r1,%r2,16 + 198: bc 12 00 20 00 00 00 00 movs32 %r1,%r2,32 diff --git a/gas/testsuite/gas/bpf/alu32-pseudoc.d b/gas/testsuite/gas/bpf/alu32-pseudoc.d index f339c80..175dd1f 100644 --- a/gas/testsuite/gas/bpf/alu32-pseudoc.d +++ b/gas/testsuite/gas/bpf/alu32-pseudoc.d @@ -57,3 +57,6 @@ Disassembly of section .text: 170: c4 04 00 00 ef be ad 7e w4 s>>=0x7eadbeef 178: cc 65 00 00 00 00 00 00 w5 s>>=w6 180: 8c 32 00 00 00 00 00 00 w2=-w3 + 188: bc 21 08 00 00 00 00 00 w1 s= \(i8\) w2 + 190: bc 21 10 00 00 00 00 00 w1 s= \(i16\) w2 + 198: bc 21 20 00 00 00 00 00 w1 s= \(i32\) w2 diff --git a/gas/testsuite/gas/bpf/alu32-pseudoc.s b/gas/testsuite/gas/bpf/alu32-pseudoc.s index 0a0d41f..5a0e442 100644 --- a/gas/testsuite/gas/bpf/alu32-pseudoc.s +++ b/gas/testsuite/gas/bpf/alu32-pseudoc.s @@ -49,3 +49,6 @@ w4 s>>= 2125315823 w5 s>>= w6 w2 = - w3 + w1 s= (i8) w2 + w1 s= (i16) w2 + w1 s= (i32) w2 diff --git a/gas/testsuite/gas/bpf/alu32.d b/gas/testsuite/gas/bpf/alu32.d index 712d1c7..68aa86f 100644 --- a/gas/testsuite/gas/bpf/alu32.d +++ b/gas/testsuite/gas/bpf/alu32.d @@ -57,3 +57,6 @@ Disassembly of section .text: 170: c4 04 00 00 ef be ad 7e arsh32 %r4,0x7eadbeef 178: cc 65 00 00 00 00 00 00 arsh32 %r5,%r6 180: 8c 32 00 00 00 00 00 00 neg32 %r2,%r3 + 188: bc 21 08 00 00 00 00 00 movs32 %r1,%r2,8 + 190: bc 21 10 00 00 00 00 00 movs32 %r1,%r2,16 + 198: bc 21 20 00 00 00 00 00 movs32 %r1,%r2,32 diff --git a/gas/testsuite/gas/bpf/alu32.s b/gas/testsuite/gas/bpf/alu32.s index f43ea4a..14f0a12 100644 --- a/gas/testsuite/gas/bpf/alu32.s +++ b/gas/testsuite/gas/bpf/alu32.s @@ -49,3 +49,6 @@ arsh32 %r4, 0x7eadbeef arsh32 %r5, %r6 neg32 %r2, %r3 + movs32 %r1,%r2,8 + movs32 %r1,%r2,16 + movs32 %r1,%r2,32 |