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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2023-06-30 22:43:55 +0200 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro> | 2023-07-01 07:28:40 -0600 |
| commit | 62edb233ef5fff5356c46570b3ba19dcbe6ceb35 (patch) | |
| tree | 96fdd45a48f4d3e2f6d94e5b7833760b82afe60a /gas | |
| parent | fce8fef965904dc16ffba2388ba44003e61cd908 (diff) | |
| download | gdb-62edb233ef5fff5356c46570b3ba19dcbe6ceb35.zip gdb-62edb233ef5fff5356c46570b3ba19dcbe6ceb35.tar.gz gdb-62edb233ef5fff5356c46570b3ba19dcbe6ceb35.tar.bz2 | |
RISC-V: Add support for the Zvknh[a,b] ISA extensions
Zvknh[a,b] are parts of the vector crypto extensions.
This extension adds the following instructions:
- vsha2ms.vv
- vsha2c[hl].vv
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
class support for Zvknh[a,b].
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* testsuite/gas/riscv/zvknha.d: New test.
* testsuite/gas/riscv/zvknha_zvknhb.s: New test.
* testsuite/gas/riscv/zvknhb.d: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VSHA2CH_VV): New.
(MASK_VSHA2CH_VV): New.
(MATCH_VSHA2CL_VV): New.
(MASK_VSHA2CL_VV): New.
(MATCH_VSHA2MS_VV): New.
(MASK_VSHA2MS_VV): New.
(DECLARE_INSN): New.
* opcode/riscv.h (enum riscv_insn_class): Add instruction class
support for Zvknh[a,b].
opcodes/ChangeLog:
* riscv-opc.c: Add Zvknh[a,b] instructions.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/testsuite/gas/riscv/zvknha.d | 12 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/zvknha_zvknhb.s | 3 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/zvknhb.d | 12 |
3 files changed, 27 insertions, 0 deletions
diff --git a/gas/testsuite/gas/riscv/zvknha.d b/gas/testsuite/gas/riscv/zvknha.d new file mode 100644 index 0000000..36d660f --- /dev/null +++ b/gas/testsuite/gas/riscv/zvknha.d @@ -0,0 +1,12 @@ +#as: -march=rv64gc_zvknha +#source: zvknha_zvknhb.s +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+ba862277[ ]+vsha2ch.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+be862277[ ]+vsha2cl.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+b6862277[ ]+vsha2ms.vv[ ]+v4,v8,v12 diff --git a/gas/testsuite/gas/riscv/zvknha_zvknhb.s b/gas/testsuite/gas/riscv/zvknha_zvknhb.s new file mode 100644 index 0000000..d20e631 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvknha_zvknhb.s @@ -0,0 +1,3 @@ + vsha2ch.vv v4, v8, v12 + vsha2cl.vv v4, v8, v12 + vsha2ms.vv v4, v8, v12 diff --git a/gas/testsuite/gas/riscv/zvknhb.d b/gas/testsuite/gas/riscv/zvknhb.d new file mode 100644 index 0000000..ab0f035 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvknhb.d @@ -0,0 +1,12 @@ +#as: -march=rv64gc_zvknhb +#source: zvknha_zvknhb.s +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+ba862277[ ]+vsha2ch.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+be862277[ ]+vsha2cl.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+b6862277[ ]+vsha2ms.vv[ ]+v4,v8,v12 |