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2016-01-01New 2016 binutils ChangeLog filesAlan Modra1-0/+14
Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01binutils ChangeLog rotationAlan Modra2-0/+0
2015-12-30Fix assorted ChangeLog errorsAlan Modra2-23/+23
2015-12-24Add assembler support for ARMv8-M BaselineThomas Preud'homme7-20/+194
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> bfd/ (tag_cpu_arch_combine): Adjust comment in v4t_plus_v6_m with regards to merging with ARMv8-M Baseline. binutils/ * readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Baseline Tag_CPU_arch value. gas/ * config/tc-arm.c (arm_ext_v6t2_v8m): New feature for instructions shared between ARMv6T2 and ARMv8-M. (move_or_literal_pool): Check mov.w/mvn and movw availability against arm_ext_v6t2 and arm_ext_v6t2_v8m respectively instead of checking arm_arch_t2. (do_t_branch): Error out for wide conditional branch instructions if targetting ARMv8-M Baseline. (non_v6t2_wide_only_insn): Add the logic for new wide-only instructions in ARMv8-M Baseline. (wide_insn_ok): New function. (md_assemble): Use wide_insn_ok instead of non_v6t2_wide_only_insn and adapt error message for unsupported wide instruction to ARMv8-M Baseline. (insns): Reorganize instructions shared by ARMv8-M Baseline and ARMv6t2 architecture. (arm_cpus): Set feature bit ARM_EXT2_V6T2_V8M for marvell-pj4 and marvell-whitney cores. (arm_archs): Define armv8-m.base architecture. (cpu_arch_ver): Define ARM_ARCH_V8M_BASE architecture version. (aeabi_set_public_attributes): Add logic to set Tag_CPU_arch to 17 for ARMv8-M Mainline. Set Tag_DIV_use for ARMv8-M Baseline as well. gas/testsuite/ * gas/arm/archv8m-base.d: New file. * gas/arm/attr-march-armv8m.base.d: Likewise. * gas/arm/armv8m.base-idiv.d: Likewise. * gas/arm/any-armv8m.d: Adapt to deal with ARMv8-M Baseline. include/elf/ * arm.h (TAG_CPU_ARCH_V8M_BASE): Declare. include/opcode/ * arm.h (ARM_EXT2_V6T2_V8M): New extension bit. (ARM_AEXT2_V8A): New architecture extension bitfield. (ARM_AEXT2_V8_1A): Use ARM_AEXT2_V8A instead of ARM_EXT2_ATOMICS. (ARM_AEXT_V8M_BASE): New architecture extension bitfield. (ARM_AEXT2_V8M): Add extension bit ARM_EXT2_V6T2_V8M. (ARM_ARCH_V6T2): Use ARM_EXT2_V6T2_V8M for the second extension bitfield. (ARM_ARCH_V6KT2): Likewise. (ARM_ARCH_V6ZT2): Likewise. (ARM_ARCH_V6KZT2): Likewise. (ARM_ARCH_V7): Likewise. (ARM_ARCH_V7A): Likewise. (ARM_ARCH_V7VE): Likewise. (ARM_ARCH_V7R): Likewise. (ARM_ARCH_V7M): Likewise. (ARM_ARCH_V7EM): Likewise. (ARM_ARCH_V8A): Likewise. (ARM_ARCH_V8M_BASE): New architecture bitfield. (ARM_ARCH_THUMB2): Include instructions shared by ARMv6t2 and ARMv8-M. (ARM_ARCH_V7A_SEC): Use ARM_EXT2_V6T2_V8M for the second extension bitfield and reindent. (ARM_ARCH_V7A_MP_SEC): Likewise. (ARM_ARCH_V7R_IDIV): Likewise. (ARM_ARCH_V8A_FP): Use ARM_AEXT2_V8A instead of ARM_EXT2_ATOMICS. (ARM_ARCH_V8A_SIMD): Likewise. (ARM_ARCH_V8A_CRYPTOV1): Likewise. opcodes/ * arm-dis.c (arm_opcodes): Guard movw, movt cbz, cbnz, clrex, ldrex, ldrexb, ldrexh, strex, strexb, strexh shared by ARMv6T2 and ARMv8-M by ARM_EXT2_V6T2_V8M instead of ARM_EXT_V6T2.
2015-12-24Add assembler support for ARMv8-M MainlineThomas Preud'homme8-25/+217
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> bfd/ (tag_cpu_arch_combine): Adjust v4t_plus_v6_m and comb array to account for new TAG_CPU_ARCH_V4T_PLUS_V6_M value. Deal with NULL values in comb array. binutils/ * readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Mainline Tag_CPU_arch value. (arm_attr_tag_THUMB_ISA_use): Add ARMv8-M Mainline Tag_THUMB_ISA_use value. gas/ * config/tc-arm.c (arm_ext_m): Include ARMv8-M. (arm_ext_v8m): New feature for ARMv8-M. (arm_ext_atomics): New feature for ARMv8 atomics. (do_tt): New encoding function for TT* instructions. (insns): Add new entries for ARMv8-M specific instructions and reorganize the ones shared by ARMv8-M Mainline and ARMv8-A. (arm_archs): Define armv8-m.main architecture. (cpu_arch_ver): Define ARM_ARCH_V8M_MAIN architecture version and clarify the ordering rule. (aeabi_set_public_attributes): Use TAG_CPU_ARCH_* macro to refer to Tag_CPU_arch values for ARMv7e-M detection. Add logic to keep setting Tag_CPU_arch to ARMv8-A for -march=all. Also set Tag_CPU_arch_profile to 'A' if extension bit for atomic instructions is set, unless it is ARMv8-M. Set Tag_THUMB_ISA_use to 3 for ARMv8-M. Set Tag_DIV_use to 0 for ARMv8-M Mainline. gas/testsuite/ * gas/arm/archv8m.s: New file. * gas/arm/archv8m-main.d: Likewise. * gas/arm/attr-march-armv8m.main.d: Likewise. * gas/arm/any-armv8m.s: Likewise. * gas/arm/any-armv8m.d: Likewise. include/elf/ * arm.h (TAG_CPU_ARCH_V8M_MAIN): Declare. (MAX_TAG_CPU_ARCH): Define to TAG_CPU_ARCH_V8M_MAIN. (TAG_CPU_ARCH_V4T_PLUS_V6_M): Define to unused value 15. include/opcode/ * arm.h (ARM_EXT2_ATOMICS): New extension bit. (ARM_EXT2_V8M): Likewise. (ARM_EXT_V8): Adjust comment with regards to atomics and remove mention of legacy use for that bit. (ARM_AEXT2_V8_1A): New architecture extension bitfield. (ARM_AEXT2_V8_2A): Likewise. (ARM_AEXT_V8M_MAIN): Likewise. (ARM_AEXT2_V8M): Likewise. (ARM_ARCH_V8A): Use ARM_EXT2_ATOMICS for features in second bitfield. (ARM_ARCH_V8_1A): Likewise with ARM_AEXT2_V8_1A. (ARM_ARCH_V8_2A): Likewise with ARM_AEXT2_V8_2A. (ARM_ARCH_V8M_MAIN): New architecture feature bitfield. (ARM_ARCH_V8A_FP): Use ARM_EXT2_ATOMICS for features in second bitfield and reindent. (ARM_ARCH_V8A_SIMD): Likewise. (ARM_ARCH_V8A_CRYPTOV1): Likewise. (ARM_ARCH_V8_1A_FP): Use ARM_AEXT2_V8_1A to set second bitfield of feature bits. (ARM_ARCH_V8_1A_SIMD): Likewise. (ARM_ARCH_V8_1A_CRYPTOV1): Likewise. opcodes/ * arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl, stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of ARM_EXT_V8. (thumb32_opcodes): Add entries for wide ARMv8-M instructions.
2015-12-24Consolidate Thumb-1/Thumb-2 ISA detectionThomas Preud'homme2-30/+60
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (move_or_literal_pool): Check mov.w, mvm and movw availability against arm_ext_v6t2 instead of checking arm_arch_t2, fixing comments along the way. (handle_it_state): Check arm_ext_v6t2 instead of arm_arch_t2 to generate IT instruction. (t1_isa_t32_only_insn): New function. (md_assemble): Use above new function to check for invalid wide instruction for CPU Thumb ISA and to determine what Thumb extension bit is necessary for that instruction. (md_apply_fix): Use arm_ext_v6t2 instead of arm_arch_t2 to decide if branch is out of range. include/opcode/ * arm.h (ARM_ARCH_THUMB2): Add comment explaining its meaning and remove extension bit not including any Thumb-2 instruction.
2015-12-24Add tests for gas arch autodetection on ARMThomas Preud'homme23-0/+152
2015-12-09 Andre Vieira <andre.simoesdiasvieira@arm.com> gas/testsuite/ * gas/arm/automatic-bw.d: New. * gas/arm/automatic-bw.s: New. * gas/arm/automatic-cbz.d: New. * gas/arm/automatic-cbz.s: New. * gas/arm/automatic-clrex.d: New. * gas/arm/automatic-clrex.s: New. * gas/arm/automatic-lda.d: New. * gas/arm/automatic-lda.s: New. * gas/arm/automatic-ldaex.d: New. * gas/arm/automatic-ldaex.s: New. * gas/arm/automatic-ldaexb.d: New. * gas/arm/automatic-ldaexb.s: New. * gas/arm/automatic-ldrex.d: New. * gas/arm/automatic-ldrex.s: New. * gas/arm/automatic-ldrexd.d: New. * gas/arm/automatic-ldrexd.s: New. * gas/arm/automatic-movw.d: New. * gas/arm/automatic-movw.s: New. * gas/arm/automatic-sdiv.d: New. * gas/arm/automatic-sdiv.s: New. * gas/arm/automatic-strexb.d: New. * gas/arm/automatic-strexb.s: New.
2015-12-21Fix building pdfs of assembler documentation.Nick Clifton2-11/+26
PR gas/19386 * doc/as.texinfo (Strings): Prepend a space to index entries that start with a backslash. This works around a problem in the pdf generator.
2015-12-18Process 64-bit imm/disp only for 64-bit BFDH.J. Lu2-0/+13
We only need to store 32-bit immediate in 64-bit and optimize 64-bit displacement to 32-bit only for 64-bit BFD. * config/tc-i386.c (optimize_imm): Store 32-bit immediate in 64-bit only for 64-bit BFD (optimize_disp): Optimize 64-bit displacement to 32-bit only for 64-bit BFD.
2015-12-17[Patch ARM] Fix build attributes for armv8-a in case of assembler files that ↵Ramana Radhakrishnan1-0/+9
contain no directives. Add missing ChangeLog entry.
2015-12-17[Patch ARM] Fix build attributes for armv8-a in case of assembler files that ↵Ramana Radhakrishnan5-1/+28
contain no directives. There is currently a problem in the way in which we produce build attributes for simple assembler files that have armv8-a instructions. In these case we need to generate TAG_ISA_THUMB_Use to be Thumb-2 and set the architecture profile to be 'A' rather than not setting architecture profile to be 'A' and setting TAG_ISA_THUMB_Use to be Thumb-1. This is a pre-requisite for any v8-m patches that have been posted. arm-none-eabi gas testsuite run. no regressions. 2015-12-17 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * gas/config/tc-arm.c (aeabi_set_public_attributes): Adjust TAG_ARCH_profile for armv8-a. * gas/testsuite/gas/arm/armv8a-automatic-hlt.d: New test. * gas/testsuite/gas/arm/armv8a-automatic-hlt.s: New test. * gas/testsuite/gas/arm/armv8a-automatic-lda.d: New test. * gas/testsuite/gas/arm/armv8a-automatic-lda.s: New test.
2015-12-17Add forgotten ChangeLog updates for 72d98d16ed09584660d0cbb759d90f8dfeef2343:Christophe Lyon2-0/+22
2015-12-16 Mickael Guene <mickael.guene@st.com> bfd/ * bfd-in2.h: Regenerate. * reloc.c: Add new relocations. * libbfd.h (bfd_reloc_code_real_names): Add new relocations display names. * elf32-arm.c (elf32_arm_howto_table_1): Add HOWTO for new relocations. (elf32_arm_reloc_map): Add bfd/arm mapping for new relocations. (elf32_arm_final_link_relocate): Implement new relocations resolution. gas/ * doc/c-arm.texi: Add documentation about new directives * config/tc-arm.c (group_reloc_table): Add mapping between gas syntax and new relocations. (do_t_add_sub): Keep new relocations for add operand. (do_t_mov_cmp): Keep new relocations for mov operand. (insns): Use 'shifter operand with possible group relocation' operand parse code for movs operand. (md_apply_fix): Implement mov and add encoding when new relocations on them. (tc_gen_reloc): Add new relocations. (arm_fix_adjustable): Since offset has a limited range ([0:255]) we disable adjust_reloc_syms() for new relocations. gas/testsuite/ * gas/arm/adds-thumb1-reloc-local.d: New * gas/arm/adds-thumb1-reloc-local.s: New * gas/arm/movs-thumb1-reloc-local.d: New * gas/arm/movs-thumb1-reloc-local.s: New include/ * elf/arm.h: Add new arm relocations. ld/testsuite/ * ld-arm/arm-elf.exp (armelftests_common): Add new relocations tests. * ld-arm/thumb1-adds.d: New * ld-arm/thumb1-adds.s: New * ld-arm/thumb1-movs.d: New * ld-arm/thumb1-movs.s: New
2015-12-16[ARM] Add support for thumb1 pcrop relocations.Mickael Guene6-5/+178
To support thumb1 execute-only code we need to support four new relocations (R_ARM_THM_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G2_NC and R_ARM_THM_ALU_ABS_G3_NC). These relocations allow the static linker to finalize construction of symbol address. Typical sequence of code to get address of the symbol foo is then the following : movs r3, #:upper8_15:#foo lsls r3, #8 adds r3, #:upper0_7:#foo lsls r3, #8 adds r3, #:lower8_15:#foo lsls r3, #8 adds r3, #:lower0_7:#foo This will give following sequence of text and relocations after assembly : 4: 2300 movs r3, #0 4: R_ARM_THM_ALU_ABS_G3_NC foo 6: 021b lsls r3, r3, #8 8: 3300 adds r3, #0 8: R_ARM_THM_ALU_ABS_G2_NC foo a: 021b lsls r3, r3, #8 c: 3300 adds r3, #0 c: R_ARM_THM_ALU_ABS_G1_NC foo e: 021b lsls r3, r3, #8 10: 3300 adds r3, #0 10: R_ARM_THM_ALU_ABS_G0_NC foo
2015-12-15Remove refernces to a non-existent silicon errata.Nick Clifton3-14/+9
* doc/c-msp430.texi (MSP430 Options): Remove references to a non-existent silicon errata. * config/tc-msp430.c: Likewise.
2015-12-15Add support for RX V2 Instruction SetYoshinori Sato82-87/+904
binutils * readelf.c(get_machine_flags): Add v2 flag. gas * config/rx-defs.h(rx_cpu_type): Add RXV2 type. * config/tc-rx.c(cpu_type_list): New type lookup table. (md_parse_option): Use lookup table for choose cpu. (md_show_usage): Add rxv2 for mcpu option. * doc/c-rx.texi: Likewise. * config/rx-parse.y: Add v2 instructions and ACC register. (rx_check_v2): check v2 type. include/elf * rx.h(E_FLAG_RX_V2): New RXv2 type. include/opcode * rx.h: Add new instructions. opcoes * rx-deocde.opc(rx_decode_opcode): Add new instructions pattern. * rx-dis.c(register_name): Add new register. gas/testsuite * gas/rx/emaca.d: New. * gas/rx/emaca.sm: New. * gas/rx/emsba.d: New. * gas/rx/emsba.sm: New. * gas/rx/emula.d: New. * gas/rx/emula.sm: New. * gas/rx/fadd.d: Add new pattern. * gas/rx/fadd.sm: Add new pattern. * gas/rx/fmul.d: Add new pattern. * gas/rx/fmul.sm: Add new pattern. * gas/rx/fsqrt.d: New. * gas/rx/fsqrt.sm: New. * gas/rx/fsub.d: Add new pattern. * gas/rx/fsub.sm: Add new pattern. * gas/rx/ftou.d: New. * gas/rx/ftou.sm: New. * gas/rx/maclh.d: New. * gas/rx/maclh.sm: New. * gas/rx/maclo.d: Add new pattern. * gas/rx/maclo.sm: Add new pattern. * gas/rx/macros.inc: Add new register. * gas/rx/movco.d: New. * gas/rx/movco.sm: New. * gas/rx/movli.d: New. * gas/rx/movli.sm: New. * gas/rx/msbhi.d: New. * gas/rx/msbhi.sm: New. * gas/rx/msblh.d: New. * gas/rx/msblh.sm: New. * gas/rx/msblo.d: New. * gas/rx/msblo.sm: New. * gas/rx/mullh.d: New. * gas/rx/mullh.sm: New. * gas/rx/mvfacgu.d: New. * gas/rx/mvfacgu.sm: New. * gas/rx/mvfachi.d: Add new pattern. * gas/rx/mvfachi.sm: Add new pattern. * gas/rx/mvfaclo.d: Add new pattern. * gas/rx/mvfaclo.sm: Add new pattern. * gas/rx/mvfacmi.d: Add new pattern. * gas/rx/mvfacmi.sm: Add new pattern. * gas/rx/mvfc.d: Add new pattern. * gas/rx/mvtacgu.d: New. * gas/rx/mvtacgu.sm: New. * gas/rx/mvtc.d: Add new pattern. * gas/rx/popc.d: Add new pattern. * gas/rx/pushc.d: Add new pattern. * gas/rx/racl.d: New. * gas/rx/racl.sm: New. * gas/rx/racw.d: Add new pattern. * gas/rx/racw.sm: Add new pattern. * gas/rx/rdacl.d: New. * gas/rx/rdacl.sm: New. * gas/rx/rdacw.d: New. * gas/rx/rdacw.sm: New. * gas/rx/rx.exp: Add option. * gas/rx/stnz.d: Add new pattern. * gas/rx/stnz.sm: Add new pattern. * gas/rx/stz.d: Add new pattern. * gas/rx/stz.sm: Add new pattern. * gas/rx/utof.d: New. * gas/rx/utof.sm: New.
2015-12-14[AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar Shift By Immediate ↵Matthew Wahab3-0/+36
instructions. ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch extends instructions in the group Adv.SIMD Scalar Shift By Immediate to support FP16, making this support available when +simd+fp16 is enabled. The extended instructions are: SCVTF, FCVTZS, UCVTF and FCVTZU. The general form for these instructions is <OP> <Hd>, <Hs>, #<imm> gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16: Add tests for Adv.SIMD scalar shift by immediate instructions. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_SSHIFT_H): New. (aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf and fcvtzu to the Adv.SIMD scalar shift by immediate group. Change-Id: I40506496f52dd96909e7344f243b38a1870df7ff
2015-12-14[AArch64][PATCH 13/14] Support FP16 Adv.SIMD Shift By Immediate instructions.Matthew Wahab5-3/+56
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch extends instructions in the group Adv.SIMD Shift By Immediate to support FP16, making this support available when +simd+fp16 is enabled. The new instructions legal make some uses of the 4h vector type that had been invalid. This patch adjusts a test that checks for these uses. The extended instructions are: SCVTF, FCVTZS, UCVTF and FCVTZU. The general form for these instructions is <OP> <Vd>.<T>, <Vs>.<T>, #<imm> where T is 4h or 8h. gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD across lanes instructions. * gas/aarch64/illegal.d: Update expected output. * gas/aarch64/illegal.s: Replace tests for illegal use of 'h' specifier. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_VSHIFT_H): New. (aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf and fcvtzu to the Adv.SIMD shift by immediate group. Change-Id: I3480f63883d54db46562573185da6982f2365ee8
2015-12-14[AArch64][PATCH 12/14] Support FP16 Adv.SIMD Scalar Pairwise instructions.Matthew Wahab3-0/+42
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch adds FP16 instructions to the group Adv.SIMD Scalar Pairwise, making them available when +simd+fp16 is enabled. The instructions added are: FMAXNMP, FADDP, FMAXP, FMINNMP and FMINP The general form for these instructions is <OP> <Hd>, <V>.<T> where T is 4h or 8h. gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD Scalar Pairwise instructions. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_SISD_PAIR_H): New. (aarch64_opcode_table): Add fp16 versions of fmaxnmp, faddp, fmaxp, fminnmp, fminp to the Adv.SIMD scalar pairwise group. Change-Id: I19937ede3441b66dd0f940269ece895b17d3c345
2015-12-14[AArch64][PATCH 11/14] Add support for the 2H vector type.Matthew Wahab2-7/+12
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. The FP16 additions to the scalar pairwise group introduce a new vector type, 2H. This patch adds support for this vector type to binutils. The patch adds a new operand qualifier to the enum aarch64.h:aarch64_opnd_qualifier. This interferes with the calculation used by aarch64-dis.c:get_vreg_qualifier_from_value, called when decoding an instruction. Since the new vector type is only used in FP16 scalar pairwise instructions which do not require the function, this patch adjusts the function to ignore the new qualifier. gas/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (parse_neon_type_for_operand): Adjust to take into account new vector type 2H. (vectype_to_qualifier): Likewise. include/opcode/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (enum aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_V_2H. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.coM> * aarch64-dis.c (get_vreg_qualifier_from_value): Update comment and adjust calculation to ignore qualifier for type 2H. * aarch64-opc.c (aarch64_opnd_qualifier): Add "2H". Change-Id: Idf9a3694732962c80fde04f08c7304de9164f126
2015-12-14[AArch64][PATCH 10/14] Rework code mapping vector types to operand qualifiers.Matthew Wahab2-6/+35
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. The FP16 additions to the scalar pairwise group introduce a new vector type. This patch reworks code in the assembler to allow the addition of the new type. The new vector type requires the addtion of a new operand qualifier to the enum aarch64_opnd_qualifier which is defined include/opcodes/aarch64.h, in the group prefixed by AARCH64_OPN_QLF_V_. The correctness of the GAS utility function tc-aarch64.c:vectype_to_qualifier is heavily dependent on the number and ordering of this group. In particular, it makes assumptions about the positions of the members of the group that are not true if a qualifier for type 2H is added before the qualifier for 4H. This patch reworks the function to weaken its assumptions, making it calculate positions in the group from the type (B, H, S, D, Q) and register width. gas/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (vectype_to_qualifier): Calculate operand qualifier from per-type base and offet. Change-Id: I95535864e342a6dec46f69d2696b3900a008f0b1
2015-12-14[AArch64][PATCH 9/14] Support FP16 Adv.SIMD Modified Immediate instructions.Matthew Wahab3-0/+22
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch adds an FP16 instruction to the group Adv.SIMD Modified Immediate, making it available when +simd+fp16 is enabled. The instruction added is: FMOV. The form of this instructions is <OP> <Hd>, #<imm> gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD modified immediate instructions. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_SIMD_IMM_H): New. (aarch64_opcode_table): Add fp16 version of fmov to the Adv.SIMD modified immediate group. Change-Id: Ic66af44c494e6a53fb1cf01c372cdc62d12643e2
2015-12-14[AArch64][PATCH 8/14] Support FP16 Adv.SIMD Across Lanes instructions.Matthew Wahab5-4/+48
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch adds FP16 instructions to the group Adv.SIMD Across Lanes, making them available when +simd+fp16 is enabled. The instructions added are: FMAXNMV, FMAXV, FMINNMV and FMINV. The general form for these instructions is <OP> <Hd>, <V>.<T> where T is 4h or 8h. The new instructions valid make uses of the 8H and 4H that were previously illegal. The patch adjusts a test for illegal uses of vector types to take this into account. gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD across lanes instructions. * gas/aarch64/illegal.d: Update expected output. * gas/aarch64/illegal.s: Replace test for illegal use of 'h' specifier. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_XLANES_FP_H): New. (aarch64_opcode_table): Add fp16 versions of fmaxnmv, fmaxv, fminnmv, fminv to the Adv.SIMD across lanes group. Change-Id: Ib9a47e867f55e0272c2446eb7e16837503d2f94c
2015-12-14[AArch64][PATCH 7/14] Support FP16 Scalar Indexed Element instructions.Matthew Wahab3-0/+37
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch adds FP16 instructions to the group Scalar Indexed Element, making them available when +simd+fp16 is enabled. The instructions added are: FMLA, FMLS, FMUL and FMULX. The general form for these instructions is <OP> <Hd>, <Hs>, <V>.h[<idx>] gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for scalar indexed element instructions. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and fmulx to the scalar indexed element group. Change-Id: I6a4ee20a9ae1019b89d0fd05da55222f267c5627
2015-12-14[AArch64][PATCH 6/14] Support FP16 Vector Indexed Element instructions.Matthew Wahab3-0/+52
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch adds FP16 instructions to the group Vector Indexed Element, making them available when +simd+fp16 is enabled. The instructions added are: FMLA, FMLS, FMUL and FMULX. The general form for these instructions is <OP> <V>.<T>, <V>.<T>, <V>.h[<idx>] where T is 4h or 8h gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for vector indexed element instructions. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_ELEMENT_FP_H): New. (aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and fmulx to the vector indexed element group. Change-Id: Ib70cd4eaa6ea2938f84ac41f31d72644dbb0ceb4
2015-12-14[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.Matthew Wahab3-0/+128
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch adds FP16 instructions to the group Scalar Two Register Misc, making them available when +simd+fp16 is enabled. The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS, FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU, SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX. The general form for these instructions is <OP> <Hd>, <Hs> or <OP> <Hd>, <Hs>, #0.0 Tested the series for aarch64-none-linux-gnu with cross-compiled check-binutils and check-gas. gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc. instructions. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_SISD_FCMP_H_0): new. (QL_S_2SAMEH): New. (aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe, frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu, fcvtzu and frsqrte to the scalar two register misc. group. Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.Matthew Wahab4-3/+208
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch adds FP16 instructions to the group Vector Two Register Misc, making them available when +simd+fp16 is enabled. The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS, FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS, FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU, SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT. The general form for these instructions is <OP> <Vd>.<T>, <Vs>.<T> where T is 4h or 8h. gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc. instructions. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_V2SAMEH): New. (aarch64_opcode_table): Add fp16 versions of frintn, frintm, fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp, frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte and fsqrt to the vector register misc. group. Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.Matthew Wahab3-0/+61
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch adds FP16 instructions to the group Scalar Three Register Same, making them available when +simd+fp16 is enabled. The instructions added are: FABD, FMULX, FCMEQ, FCMGE, FCMGT, FACGE, FACGT, FRECPS and FRSQRTS. The general form for these instructions is <OP> <Hd>, <Hs>, <Hm> gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for scalar three register same instructions. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and facgt to the scalar three same group. Change-Id: I155eb8d7c1e9a7c89d691d7e4aae83be51ff1238
2015-12-14[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.Matthew Wahab3-0/+214
ARMv8.2 adds 16-bit floating point operations as an optional extension to floating point and Adv.SIMD support. This patch adds FP16 instructions to the group Vector Three Register Same, making them available when +simd+fp16 is enabled. The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA, FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE, FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS. The general form for these instructions is <OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T> where T is 4h or 8h. gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: New. * gas/aarch64/advsimd-fp16.s: New. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_V3SAMEH): New. (aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd, fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts, fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd, fcmgt, facgt and fminp to the vector three same group. Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14gas: free allocated symbol name in .cfi_label handlingJan Beulich2-0/+5
I've just noticed this further oversights of the original commit.
2015-12-12Fix SH gas testsuite invalid assembly exposed by ec9ab52cAlan Modra3-2/+7
* gas/sh/tlsd.s: Use .tdata not .tbss. * gas/sh/tlsnopic.s: Likewise.
2015-12-11[AArch64][Patch 5/5] Add instruction PSB CSYNCMatthew Wahab6-3/+77
The Statistical Profile Extension adds the instruction PSB CSYNC as an alias for the HINT #17 instruction. This patch adds the instruction to binutils as a HINT alias that takes an operand. A new operand type, AARCH64_OPND_BARRIER_PSB, is added to represent the operand to PSB. A parser for the operand type is added to the assembler and a printer to the disassembler. The operand name "csync" is added to the list of HINT options with HINT number #17. Encoding and decoding of the operand is handled by the ins_hint/ext_hint functions added in the preceding patches. gas/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (aarch64_hint_opt_hsh): New. (parse_barrier_psb): New. (parse_operands): Add case for AARCH64_OPND_BARRIER_PSB. (md_begin): Set up aarch64_hint_opt_hsh. gas/testsuite/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/system-2.d: Enable the statistical profiling extension. Update the expected output. * gas/aarch64/system-2.s: Add tests for PSB CSYNC. * gas/aarch64/system.d: Update the expected output. include/opcode/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (aarch64_opnd): Add AARCH64_OPND_BARRIER_PSB. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-opc.c (aarch64_hint_options): Add "csync". (aarch64_print_operands): Handle AARCH64_OPND_BARRIER_PSB. * aarch64-tbl.h (aarch64_feature_stat_profile): New. (STAT_PROFILE): New. (aarch64_opcode_table): Add "psb". (AARCH64_OPERANDS): Add "BARRIER_PSB". Change-Id: I5ffb672d26a8b15b48785478d359350a9b70ca09
2015-12-11[AArch64][Patch 2/5] Add Statistical Profiling Extension system registers.Matthew Wahab3-1/+52
The Statistical Profile extension included in the ARMv8.2 architecture adds a number of system registers. This patch adds the registers to binutils, making them available when the architecture extension "+profile" is enabled. opcodes/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1, pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1, pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and pmscr_el2. (aarch64_sys_reg_supported_p): Add architecture feature tests for the new registers. gas/testsuite/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/sysreg-2.s: Add tests for the statistical profiling system registers. * gas/aarch64/sysreg-2.d: Enable the statistical profiling extension and update the expected output. Change-Id: Ibf23ad34db7c33f0fcd30010b796748b38be6efb
2015-12-11[AArch64][Patch 1/5] Support the ARMv8.2 Statistical Profiling Extension.Matthew Wahab3-0/+8
The Statistical Profile extension included in the ARMv8.2 architecture adds a number of system registers and a new instruction. This patch set adds support for the extension to binutils, enabled when -march=armv8.2-a+profile is given. The patches in this series: - Add the new command line option and feature flags. - Add the new system registers. - Adjust the maximum number of aliases permitted for an instruction. - Add support for HINT aliases which take operands. - Add the new instruction, an alias of the HINT instruction. This patch adds the option "profile" to the permitted architecture extensions, disabling it by default. gas/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (aarch64_features): Add "profile". * doc/c-aarch64.texi (AArch64 Extensions): Add "profile". include/opcode/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (AARCH64_FEATURE_PROFILE): New. Change-Id: If9bb4a9b69a264180f96f8ffaf10b15ced273699
2015-12-10[Aarch64] Support ARMv8.2 AT instructionsMatthew Wahab3-0/+13
ARMv8.2 adds new instructions AT S1E1RP and AT S1E1WP to Aarch64. This patch adds support for the instructions, making them available when -march=armv8.2-a is selected. gas/testsuite/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/sysreg-2.d: Update for new tests for AT S1E1RP and AT S1E1WP. * gas/aarch64/sysreg-2.s: Add tests for AT S1E1RP and AT S1E1WP. opcodes/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp". (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register feature test for "s1e1rp" and "s1e1wp". Change-Id: I09e1044b629ab0a34b03c423e8d4e71ff92daad4
2015-12-10[AArch64][PATCH 2/2] Support ARMv8.2 DC CVAP instruction.Matthew Wahab5-0/+23
ARMv8.2 adds the new system instruction DC CVAP. This patch adds support for the instruction to binutils, enabled when -march=armv8.2-a is selected. gas/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (parse_sys_ins_reg): Add check of architectural support for system register. gas/testsuite/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/sysreg-2.d: Add tests for dc instruction. * gas/aarch64/sysreg-2.s: Add uses of dc instruction. include/opcode/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (aarch64_sys_ins_reg_supported_p): Declare. opcodes/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap". (aarch64_sys_ins_reg_supported_p): New. Change-Id: I3158b97d9bbee9644c2d0e2986db807412ef1053
2015-12-10[AArch64][binutils] Add support for ARMv8.2 PSTATE.UAO.Matthew Wahab4-0/+63
ARMv8.2 adds a new control bit PSTATE.UAO. This patch adds support for this bit to binutils, following the same basic pattern as for PSTATE.PAN. The new control bit is only available when -march=armv8.2-a is specified. gas/testsuite/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/uao-directive.d: New. * gas/aarch64/uao.d: New. * gas/aarch64/uao.s: New. opcodes/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64-opc.c (aarch64_sys_regs): Add "uao". (aarch64_sys_reg_supported_p): Add comment. Add checks for "uao". (aarch64_pstatefields): Add "uao". (aarch64_pstatefield_supported_p): Add checks for "uao". Change-Id: Id571628ac5227b78aaf1876e85d15d7b6c0a2896
2015-12-10gas: documentation for the SPARC %dN and %qN fp registers notationJose E. Marchesi2-0/+13
gas/ChangeLog: 2015-12-10 Jose E. Marchesi <jose.marchesi@oracle.com> * doc/c-sparc.texi (Sparc-Regs): Document the %dN and %qN notation for floating-point registers.
2015-12-10[AArch64][PATCH 2/2] Add RAS system registers.Matthew Wahab3-0/+41
The ARMv8.2 RAS extension adds a number of new registers. This patch adds the registers and makes them available whenever the RAS extension is enabled, as it is when -march=armv8.2-a is selected. The new registers are: erridr_el1, errselr_el1, erxfr_el1, erxctlr, erxaddr_el1, erxmisc0_el1, erxmisc1_el1, vsesr_el2, disr_el1 and vdisr_el2. gas/testsuite/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/sysreg-2.d: Add tests for new registers. * gas/aarch64/sysreg-2.s: Likewise. Also replace some spaces with tabs. opcodes/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1", "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1", "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2". (aarch64_sys_reg_supported_p): Add architecture feature tests for new registers. Change-Id: I8a01a0f0ee7987f89eead32650f6afcc749b3c74
2015-12-10[AArch64][PATCH 1/2] Add support for RAS instruction ESB.Matthew Wahab4-1/+23
The ARMv8.2 RAS extension adds a new barrier instruction ESB as an alias and the preferred form of HINT 16. This patch adds an architectural feature flag for the RAS extension and includes it in the features selected enabled by -march=armv8.2-a. It also adds the ESB instruction, making it available whenever the RAS feature is enabled. Because ESB is the preferred form and because the target architecture isn't available to the disassembler, HINT 16 will be disassembled as ESB even when the target has no support for the RAS extension. gas/testsuite/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/system-2.d: New. * gas/aarch64/system-2.s: New. * gas/aarch64/system.d: Adjust expected output for HINT 16. include/opcode/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (AARCH64_FEATURE_RAS): New. (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_RAS. opcodes/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-tbl.h (aarch64_feature_ras): New. (RAS): New. (aarch64_opcode_table): Add "esb". Change-Id: Id4713917da15cca3b977284f43febd1c9b3d9faf
2015-12-10[AArch64] Fix ARMv8.1 and ARMv8.2 feature settings.Matthew Wahab2-1/+5
ARMv8.1 includes CRC as a required extension but this isn't reflected in the features enabled by -march=armv8.1-a. The FP16 feature modifier also clashes with AARCH64_FEATURE_V8_1 and the list of features for ARMv8.2 is missing ARMv8.1 features. This patch enables +crc for -march values of armv8.1-a and later. It also fixes the values for AARCH64_FEATURE_F16 and makes AARCH64_ARCH_V8_2 and superset of AARCH64_ARCH_V8_2. gas/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * doc/c-aarch64.texi (AArch64 Extensions): Update entry for crc. include/opcode 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (AARCH64_FEATURE_F16): Fix clash with AARCH64_FEATURE_V8_1. (AARCH64_ARCH_V8_1): Add AARCH64_FEATURE_CRC. (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_CRC and AARCH64_FEATURE_V8_1. Change-Id: I8af5369f6df2430b28f6cec92870d2a4d14a7431
2015-12-10arc/gas: Accept, but ignore, dummy arguments.Andrew Burgess2-1/+7
There's a set of legacy command line arguments that the arc assembler still accepts, however, these arguments not longer have any effect on the assembler. Currently we return false from md_parse_option for all of these arguments, with the result that the assembler terminates with an error message. We should return true indicating that the argument has been accepted, even though we ignore it. gas/ChangeLog: * config/tc-arc.c (md_parse_option): Return 1 in order to accept dummy arguments.
2015-12-09Implement Intel OSPKE instructionsH.J. Lu6-0/+42
This patch implements Intel OSPKE instructions documented in Intel64 and IA-32 Architectures Software Developer’s Manual Volume 2, September 2015. gas/testsuite/ * gas/i386/i386.exp: Run ospke and x86-64-ospke. * gas/i386/ospke.d: New file. * gas/i386/ospke.s: Likewise. * gas/i386/x86-64-ospke.d: Likewise. opcodes/ * i386-dis.c (MOD_0F01_REG_5): New. (RM_0F01_REG_5): Likewise. (reg_table): Use MOD_0F01_REG_5. (mod_table): Add MOD_0F01_REG_5. (rm_table): Add RM_0F01_REG_5. * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS. (cpu_flags): Add CpuOSPKE. * i386-opc.h (CpuOSPKE): New. (i386_cpu_flags): Add cpuospke. * i386-opc.tbl: Add rdpkru and wrpkru instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2015-12-09gas/ELF: slightly relax elf/file*.d expectationsJan Beulich3-0/+8
Despite the re-ordering done for the file symbols, some targets manage to put section symbols ahead of it.
2015-12-09sparc: support %dN and %qN syntax for FP registers.Jose E. Marchesi2-5/+16
The SPARC Refence Manual documents the %dN and %qN syntax to refer to double and quad-precision floating-point registers, respectively. See OSA2015 Appendix C, Assembly Language Syntax, C1.1 Register Names. This patch adds support for these names to GAS. This eases the porting of software from Solaris to GNU/Linux, as these register names have been supported by the Solaris linker for a long time and many assembler require that support. gas/ChangeLog: 2015-12-09 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-sparc.c (sparc_ip): Support %dN and %qN notation for double and quad-precision floating-point registers.
2015-12-09Fix compile time warning building RX target.Nick Clifton2-1/+5
2015-12-08gas: consistently emit diagnostics for non-zero data emission to .bss/.structJan Beulich8-16/+256
2015-12-08gas: don't get confused by .asci{i,z} after .structJan Beulich2-8/+14
While not allowed, this certainly shouldn't result in confusing the programmer (by skipping lines in unexpected ways): Without returning, demand_empty_rest_of_line() (at the end of the function) will demand the _next_ line to be empty, and without the conditional we would ignore the next line.
2015-12-08ELF: don't re-order SHF_FILE symbolsJan Beulich8-21/+58
.file directives may be used to identify the scope of local symbols, the purpose of which gets subverted when re-ordering them. Only allow the first of them to be moved to the first position.
2015-12-08rl78: relaxation fixesDJ Delorie5-26/+106
Various fixes to linker relaxation. In general, we need to support relaxing every branch, even if we don't relax it in the assembler, so we can optionally defer relaxation to the linker. * elf32-rl78.c (rl78_offset_for_reloc): Add more relocs. (rl78_elf_relax_section): Add bc/bz/bnc/bnz/bh/bnh. Fix reloc choices. * config/rl78-parse.y: Make all branches relaxable via rl78_linkrelax_branch(). * config/tc-rl78.c (rl78_linkrelax_branch): Mark all relaxable branches with relocs. (options): Add OPTION_NORELAX. (md_longopts): Add -mnorelax. (md_parse_option): Support OPTION_NORELAX. (op_type_T): Add bh, sk, call, and br. (rl78_opcode_type): Likewise. (rl78_relax_frag): Fix not-relaxing logic. Add sk. (md_convert_frag): Fix relocation handling. (tc_gen_reloc): Strip relax relocs when not linker relaxing. (md_apply_fix): Defer overflow handling for anything that needs a PLT, to the linker. * config/tc-rl78.h (TC_FORCE_RELOCATION): Force all relocations to the linker when linker relaxing. * doc/c-rl78.texi (norelax): Add.
2015-12-07tc-ppc.c md_apply_fix tidyAlan Modra2-12/+16
* config/tc-ppc.c (md_apply_fix): Localize variables. Reduce casts.
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