[AArch64][PATCH 13/14] Support FP16 Adv.SIMD Shift By Immediate instructions.

ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch extends
instructions in the group Adv.SIMD Shift By Immediate to support FP16,
making this support available when +simd+fp16 is enabled.

The new instructions legal make some uses of the 4h vector type that had
been invalid. This patch adjusts a test that checks for these uses.

The extended instructions are: SCVTF, FCVTZS, UCVTF and FCVTZU.

The general form for these instructions is
   <OP> <Vd>.<T>, <Vs>.<T>, #<imm>
   where T is 4h or 8h.

gas/testsuite/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/advsimd-fp16.d: Update expected output.
	* gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD across lanes
	instructions.
	* gas/aarch64/illegal.d: Update expected output.
	* gas/aarch64/illegal.s: Replace tests for illegal use of 'h'
	specifier.

opcodes/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-tbl.h (QL_VSHIFT_H): New.
	(aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
	and fcvtzu to the Adv.SIMD shift by immediate group.

Change-Id: I3480f63883d54db46562573185da6982f2365ee8

5 files changed, 56 insertions, 3 deletions

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index d8a7e18..62a7030 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,6 +1,15 @@
 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
 
 	* gas/aarch64/advsimd-fp16.d: Update expected output.
+	* gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD across lanes
+	instructions.
+	* gas/aarch64/illegal.d: Update expected output.
+	* gas/aarch64/illegal.s: Replace tests for illegal use of 'h'
+	specifier.
+
+2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
+
+	* gas/aarch64/advsimd-fp16.d: Update expected output.
 	* gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD Scalar
 	Pairwise instructions.
 
diff --git a/gas/testsuite/gas/aarch64/advsimd-fp16.d b/gas/testsuite/gas/aarch64/advsimd-fp16.d
index 3b8506b..a6792ee 100644
--- a/gas/testsuite/gas/aarch64/advsimd-fp16.d
+++ b/gas/testsuite/gas/aarch64/advsimd-fp16.d
@@ -519,3 +519,31 @@ Disassembly of section \.text:
  [0-9a-f]+:	7eb0f841 	fminp	s1, v2.2s
  [0-9a-f]+:	5eb0f841 	fminp	h1, v2.2h
  [0-9a-f]+:	5eb0f800 	fminp	h0, v0.2h
+ [0-9a-f]+:	4f7de441 	scvtf	v1.2d, v2.2d, #3
+ [0-9a-f]+:	0f3de441 	scvtf	v1.2s, v2.2s, #3
+ [0-9a-f]+:	4f3de441 	scvtf	v1.4s, v2.4s, #3
+ [0-9a-f]+:	0f1de441 	scvtf	v1.4h, v2.4h, #3
+ [0-9a-f]+:	4f1de441 	scvtf	v1.8h, v2.8h, #3
+ [0-9a-f]+:	0f1fe400 	scvtf	v0.4h, v0.4h, #1
+ [0-9a-f]+:	4f1fe400 	scvtf	v0.8h, v0.8h, #1
+ [0-9a-f]+:	4f7dfc41 	fcvtzs	v1.2d, v2.2d, #3
+ [0-9a-f]+:	0f3dfc41 	fcvtzs	v1.2s, v2.2s, #3
+ [0-9a-f]+:	4f3dfc41 	fcvtzs	v1.4s, v2.4s, #3
+ [0-9a-f]+:	0f1dfc41 	fcvtzs	v1.4h, v2.4h, #3
+ [0-9a-f]+:	4f1dfc41 	fcvtzs	v1.8h, v2.8h, #3
+ [0-9a-f]+:	0f1ffc00 	fcvtzs	v0.4h, v0.4h, #1
+ [0-9a-f]+:	4f1ffc00 	fcvtzs	v0.8h, v0.8h, #1
+ [0-9a-f]+:	6f7de441 	ucvtf	v1.2d, v2.2d, #3
+ [0-9a-f]+:	2f3de441 	ucvtf	v1.2s, v2.2s, #3
+ [0-9a-f]+:	6f3de441 	ucvtf	v1.4s, v2.4s, #3
+ [0-9a-f]+:	2f1de441 	ucvtf	v1.4h, v2.4h, #3
+ [0-9a-f]+:	6f1de441 	ucvtf	v1.8h, v2.8h, #3
+ [0-9a-f]+:	2f1fe400 	ucvtf	v0.4h, v0.4h, #1
+ [0-9a-f]+:	6f1fe400 	ucvtf	v0.8h, v0.8h, #1
+ [0-9a-f]+:	6f7dfc41 	fcvtzu	v1.2d, v2.2d, #3
+ [0-9a-f]+:	2f3dfc41 	fcvtzu	v1.2s, v2.2s, #3
+ [0-9a-f]+:	6f3dfc41 	fcvtzu	v1.4s, v2.4s, #3
+ [0-9a-f]+:	2f1dfc41 	fcvtzu	v1.4h, v2.4h, #3
+ [0-9a-f]+:	6f1dfc41 	fcvtzu	v1.8h, v2.8h, #3
+ [0-9a-f]+:	2f1ffc00 	fcvtzu	v0.4h, v0.4h, #1
+ [0-9a-f]+:	6f1ffc00 	fcvtzu	v0.8h, v0.8h, #1
diff --git a/gas/testsuite/gas/aarch64/advsimd-fp16.s b/gas/testsuite/gas/aarch64/advsimd-fp16.s
index c0ea786..1eb7418 100644
--- a/gas/testsuite/gas/aarch64/advsimd-fp16.s
+++ b/gas/testsuite/gas/aarch64/advsimd-fp16.s
@@ -213,7 +213,7 @@
 	fmov	v0.4h, #1.0
 	fmov	v0.8h, #1.0
 
-	/* Adv.SIMD modified immediate.  */
+	/* Adv.SIMD scalar pairwise.  */
 
 	.macro scalar_pairwise, op
 	\op	d1, v2.2d
@@ -228,3 +228,19 @@
 	scalar_pairwise fminnmp
 	scalar_pairwise fminp
 
+	/* Adv.SIMD shift by immediate.  */
+
+	.macro shift_imm, op
+	\op v1.2d, v2.2d, #3
+	\op v1.2s, v2.2s, #3
+	\op v1.4s, v2.4s, #3
+	\op v1.4h, v2.4h, #3
+	\op v1.8h, v2.8h, #3
+	\op v0.4h, v0.4h, #1
+	\op v0.8h, v0.8h, #1
+	.endm
+
+	shift_imm scvtf
+	shift_imm fcvtzs
+	shift_imm ucvtf
+	shift_imm fcvtzu
diff --git a/gas/testsuite/gas/aarch64/illegal.l b/gas/testsuite/gas/aarch64/illegal.l
index 7482bc7..6119065 100644
--- a/gas/testsuite/gas/aarch64/illegal.l
+++ b/gas/testsuite/gas/aarch64/illegal.l
@@ -111,7 +111,7 @@
 [^:]*:160: Error: .*`sshr v0.4s,v1.4s,#33'
 [^:]*:161: Error: .*`sshr v0.4h,v1.4h,#20'
 [^:]*:163: Error: .*`shl v0.4s,v1.4s,#32'
-[^:]*:164: Error: .*`fcvtzs v0.4h,v1.4h,#2'
+[^:]*:164: Error: .*`fcvtzs v0.2h,v1.2h,#2'
 [^:]*:165: Error: .*`uqshrn v0.2s,v1.2d,33'
 [^:]*:166: Error: .*`uqrshrn v0.2s,v1.2s,32'
 [^:]*:167: Error: .*`sshll v8.8h,v2.8b,#8'
diff --git a/gas/testsuite/gas/aarch64/illegal.s b/gas/testsuite/gas/aarch64/illegal.s
index 0960b7e..ee75aff 100644
--- a/gas/testsuite/gas/aarch64/illegal.s
+++ b/gas/testsuite/gas/aarch64/illegal.s
@@ -161,7 +161,7 @@
 	sshr	v0.4h, v1.4h, #20
 
 	shl	v0.4s, v1.4s, #32
-	fcvtzs	v0.4h, v1.4h, #2
+	fcvtzs	v0.2h, v1.2h, #2
 	uqshrn	v0.2s, v1.2d, 33
 	uqrshrn	v0.2s, v1.2s, 32
 	sshll	v8.8h, v2.8b, #8