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| author | Matthew Wahab <matthew.wahab@arm.com> | 2015-12-10 14:09:03 +0000 |
|---|---|---|
| committer | Matthew Wahab <matthew.wahab@arm.com> | 2015-12-10 14:10:24 +0000 |
| commit | 47f8114261a50dcb44bd3be355b705e37d920944 (patch) | |
| tree | 8d5a8e4eb8b0646e02183ca8ce8ffa9fb175c039 /gas | |
| parent | c8a6db6fa0b06b978e5b63593a6b0cb3300ad259 (diff) | |
| download | gdb-47f8114261a50dcb44bd3be355b705e37d920944.zip gdb-47f8114261a50dcb44bd3be355b705e37d920944.tar.gz gdb-47f8114261a50dcb44bd3be355b705e37d920944.tar.bz2 | |
[AArch64][PATCH 2/2] Add RAS system registers.
The ARMv8.2 RAS extension adds a number of new registers. This patch
adds the registers and makes them available whenever the RAS extension
is enabled, as it is when -march=armv8.2-a is selected.
The new registers are:
erridr_el1, errselr_el1, erxfr_el1, erxctlr, erxaddr_el1,
erxmisc0_el1, erxmisc1_el1, vsesr_el2, disr_el1 and
vdisr_el2.
gas/testsuite/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/sysreg-2.d: Add tests for new registers.
* gas/aarch64/sysreg-2.s: Likewise. Also replace some spaces with
tabs.
opcodes/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
"errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
"erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
(aarch64_sys_reg_supported_p): Add architecture feature tests for
new registers.
Change-Id: I8a01a0f0ee7987f89eead32650f6afcc749b3c74
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/testsuite/ChangeLog | 6 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sysreg-2.d | 18 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sysreg-2.s | 17 |
3 files changed, 41 insertions, 0 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 7fd79a8..dd4a44a 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,5 +1,11 @@ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> + * gas/aarch64/sysreg-2.d: Add tests for new registers. + * gas/aarch64/sysreg-2.s: Likewise. Also replace some spaces with + tabs. + +2015-12-10 Matthew Wahab <matthew.wahab@arm.com> + * gas/aarch64/system-2.d: New. * gas/aarch64/system-2.s: New. * gas/aarch64/system.d: Adjust expected output for HINT 16. diff --git a/gas/testsuite/gas/aarch64/sysreg-2.d b/gas/testsuite/gas/aarch64/sysreg-2.d index f0fe533..31b9f33 100644 --- a/gas/testsuite/gas/aarch64/sysreg-2.d +++ b/gas/testsuite/gas/aarch64/sysreg-2.d @@ -9,3 +9,21 @@ Disassembly of section .text: 0000000000000000 <.*>: [0-9a-f]+: d5380725 mrs x5, id_aa64mmfr1_el1 [0-9a-f]+: d5380747 mrs x7, id_aa64mmfr2_el1 + [0-9a-f]+: d5385305 mrs x5, erridr_el1 + [0-9a-f]+: d5185327 msr errselr_el1, x7 + [0-9a-f]+: d5385327 mrs x7, errselr_el1 + [0-9a-f]+: d5385405 mrs x5, erxfr_el1 + [0-9a-f]+: d5185425 msr erxctlr_el1, x5 + [0-9a-f]+: d5385425 mrs x5, erxctlr_el1 + [0-9a-f]+: d5185445 msr erxstatus_el1, x5 + [0-9a-f]+: d5385445 mrs x5, erxstatus_el1 + [0-9a-f]+: d5185465 msr erxaddr_el1, x5 + [0-9a-f]+: d5385465 mrs x5, erxaddr_el1 + [0-9a-f]+: d5185505 msr erxmisc0_el1, x5 + [0-9a-f]+: d5385505 mrs x5, erxmisc0_el1 + [0-9a-f]+: d5185525 msr erxmisc1_el1, x5 + [0-9a-f]+: d5385525 mrs x5, erxmisc1_el1 + [0-9a-f]+: d53c5265 mrs x5, vsesr_el2 + [0-9a-f]+: d518c125 msr disr_el1, x5 + [0-9a-f]+: d538c125 mrs x5, disr_el1 + [0-9a-f]+: d53cc125 mrs x5, vdisr_el2 diff --git a/gas/testsuite/gas/aarch64/sysreg-2.s b/gas/testsuite/gas/aarch64/sysreg-2.s index f519682..2a6b06c 100644 --- a/gas/testsuite/gas/aarch64/sysreg-2.s +++ b/gas/testsuite/gas/aarch64/sysreg-2.s @@ -13,3 +13,20 @@ rw_sys_reg sys_reg=id_aa64mmfr1_el1 xreg=x5 r=1 w=0 rw_sys_reg sys_reg=id_aa64mmfr2_el1 xreg=x7 r=1 w=0 + + /* RAS extension. */ + + rw_sys_reg sys_reg=erridr_el1 xreg=x5 r=1 w=0 + rw_sys_reg sys_reg=errselr_el1 xreg=x7 r=1 w=1 + + rw_sys_reg sys_reg=erxfr_el1 xreg=x5 r=1 w=0 + rw_sys_reg sys_reg=erxctlr_el1 xreg=x5 r=1 w=1 + rw_sys_reg sys_reg=erxstatus_el1 xreg=x5 r=1 w=1 + rw_sys_reg sys_reg=erxaddr_el1 xreg=x5 r=1 w=1 + + rw_sys_reg sys_reg=erxmisc0_el1 xreg=x5 r=1 w=1 + rw_sys_reg sys_reg=erxmisc1_el1 xreg=x5 r=1 w=1 + + rw_sys_reg sys_reg=vsesr_el2 xreg=x5 r=1 w=0 + rw_sys_reg sys_reg=disr_el1 xreg=x5 r=1 w=1 + rw_sys_reg sys_reg=vdisr_el2 xreg=x5 r=1 w=0 |