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2019-10-25PR25125, relaxation chooses wrong branch sizeAlan Modra2-4/+13
The patch I made for PR12049 didn't test for a "negative" branch properly. "if (target < address)" ought to have been "if (target < address + fragP->fr_fix)". Rather than making that change, this patch adds fragP->fr_fix into address earlier. The patch also avoids running into a bad interaction with the m68k md_prepare_relax_scan by returning zero growth immediately, since the adjusted target expression would result in a zero "aim". PR gas/25125 PR gas/12049 * write.c (relax_frag): Correct calculation of delta for positive branches where "stretch" would make the branch negative. Return zero immediately in that case. Correct TC_PCREL_ADJUST comment.
2019-10-16qsort: tc-xtensa.c tidyAlan Modra2-22/+33
Not much to see here, just reduce the number of calls to S_GET_VALUE and symbol_symbolS in the comparison functions. * config/tc-xtensa.c (xg_order_trampoline_chain_entry): Don't call S_GET_VALUE multiple times for a symbol. Rearrange code so it is obvious what is the primary sort key. (xg_order_trampoline_chain): Similarly.
2019-10-15remove more xmalloc in bfdAlan Modra2-6/+12
Also fixes m68hc1x printf arguments which would have bombed when compiling on a 32-bit host with --enable-64-bit-bfd. bfd/ PR 24955 * elf32-arm.c (set_cmse_veneer_addr_from_implib): Use bfd_malloc rather than xmalloc. * elf32-m68hc1x.c (reloc_warning): New function. (elf32_m68hc11_relocate_section): Use it here. Cast bfd_vma values corresponding to %lx in format strings. * elf32-nds32.c (nds32_insertion_sort): Use a stack temporary. gas/ * config/tc-nds32.c (nds32_set_section_relocs): Use relocs and n parameters rather than equivalent sec->orelocation and sec->reloc_count. Don't sort for n <= 1. Tidy.
2019-10-09Fix the disassembly of the LDS and STS instructions of the AVR architecture.Nick Clifton3-0/+19
PR 25041 opcodes * avr-dis.c (avr_operand): Fix construction of address for lds/sts instructions. gas * testsuite/gas/avr/pr25041.s: New test. * testsuite/gas/avr/pr25041.d: New test driver.
2019-10-08S/390: Add support for z15 as CPU name.Andreas Krebbel3-4/+5
So far z15 was identified as arch13. After the machine has been announced we can now add the real name. gas/ChangeLog: 2019-10-08 Andreas Krebbel <krebbel@linux.ibm.com> * config/tc-s390.c (s390_parse_cpu): Add z15 as alternate CPU name. * doc/as.texi: Add z15 to CPU string list. * doc/c-s390.texi: Likewise. opcodes/ChangeLog: 2019-10-08 Andreas Krebbel <krebbel@linux.ibm.com> * s390-mkopc.c (main): Enable z15 as CPU string in the opcode table.
2019-10-07Add support for new functionality in the msp430 backend of GCC.Jozef Lawrynowicz17-4/+252
This functionality will generate a new GNU object attribute for the "data region" has been added. This object attribute is used mark whether the compiler has generated code assuming that data could be in the upper or lower memory regions. Code which assumes data is always in the lower memory region is incompatible with code which uses the full memory range for data. The patch also adds a new assembler directive ".mspabi_attribute" to handle the existing MSPABI object attributes. GCC will now emit both .gnu_attribute and .mspabi_attribute directives to indicate what options the source file was compiled with. The assembler will now check the values set in these directives against the options that the it has been invoked with. If there is a discrepancy, the assembler will exit with an error. bfd * elf32-msp430.c (elf32_msp430_merge_mspabi_attributes): Rename to.. (elf32_msp430_merge_msp430_attributes): Add support for merging the GNU object attribute for data region. binutils* readelf.c (display_msp430_gnu_attribute): New. (process_arch_specific): Use msp430 specific handler for GNU attributes. gas * config/tc-msp430.c (md_parse_option): Set lower_data_region_only to FALSE if the data region is set to "upper", "either" or "none". (msp430_object_attribute): New. (md_pseudo_table): Handle .mspabi_attribute and .gnu_attribute. (msp430_md_end): Replace hard-coded attribute values with enums. Handle data region object attribute. * doc/as.texi: Document MSP430 Data Region object attribute. * doc/c-msp430.texi: Document the .mspabi_attribute directive. * testsuite/gas/msp430/attr-430-small-bad.d: New test. * testsuite/gas/msp430/attr-430-small-bad.l: New test. * testsuite/gas/msp430/attr-430-small-good.d: New test. * testsuite/gas/msp430/attr-430-small.s: New test. * testsuite/gas/msp430/attr-430x-large-any-bad.d: New test. * testsuite/gas/msp430/attr-430x-large-any-bad.l: New test. * testsuite/gas/msp430/attr-430x-large-any-good.d: New test. * testsuite/gas/msp430/attr-430x-large-any.s: New test. * testsuite/gas/msp430/attr-430x-large-lower-bad.d: New test. * testsuite/gas/msp430/attr-430x-large-lower-bad.l: New test. * testsuite/gas/msp430/attr-430x-large-lower-good.d: New test. * testsuite/gas/msp430/attr-430x-large-lower.s: New test. * testsuite/gas/msp430/msp430.exp: Run new tests. include * elf/msp430.h: Add enums for MSPABI and GNU object attribute tag names and values. ld * testsuite/ld-msp430-elf/attr-gnu-main.s: New test. * testsuite/ld-msp430-elf/attr-gnu-obj.s: New test. * testsuite/ld-msp430-elf/attr-gnu-region-lower-upper.d: New test. * testsuite/ld-msp430-elf/attr-gnu-region-lower.d: New test. * testsuite/ld-msp430-elf/attr-gnu-region-upper.d: New test. * testsuite/ld-msp430-elf/msp430-elf.exp: Run new tests.
2019-10-07add missing ChangeLog entry for d241b91073Jan Beulich1-0/+13
2019-10-07x86/Intel: correct MOVSD and CMPSD handlingJan Beulich9-12/+233
First and foremost the EsSeg attribute was misplaced for CMPSD. Then both it and MOVSD were lacking Dword on both of their operands. Finally string insns with multiple operands and requiring use of ES: had the wrong operand number reported in the diagnostic.
2019-09-24Arm: Fix out of range conditional branch (PR/24991)Tamar Christina5-7/+38
The fix for PR12848 introduced an off by one error in the mask, this corrected the negative overflows but not the positive overflows. As a result the conditional branch instructions accepted a too wide positive immediate which resulted in it corrupting the instruction during encoding. The relocation I believe has been incorrectly named, to be consistent with the other relocations it should have been named BRANCH21 which is why the masks for it are confusing. I've replaced the masks with a function out_of_range_p which should make it harder to make such mistakes. The mask for BL/BLX on Armv6t+ is also wrong, the extended range is 25-bits and so the mask should be checking for 24-bits for positive overflow. gas/ChangeLog: PR gas/24991 * config/tc-arm.c (out_of_range_p): New. (md_apply_fix): Use it in BFD_RELOC_THUMB_PCREL_BRANCH9, BFD_RELOC_THUMB_PCREL_BRANCH12, BFD_RELOC_THUMB_PCREL_BRANCH20, BFD_RELOC_THUMB_PCREL_BRANCH23, BFD_RELOC_THUMB_PCREL_BRANCH25 * testsuite/gas/arm/pr24991.d: New test. * testsuite/gas/arm/pr24991.l: New test. * testsuite/gas/arm/pr24991.s: New test.
2019-09-24[ARM]: Modify assembler to accept floating and signless datatypes for MVE ↵Srinath Parvathaneni5-6/+81
instruction VLDR. This patch modifies assembler to accept the equivalent sized floating and signless datatypes for VLDR instruction but as alias for the unsigned version. gas/ChangeLog: 2019-09-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/tc-arm.c (do_mve_vstr_vldr_RQ): Modify function to allow float * and signless datatypes for few cases of VLDR instruction. * testsuite/gas/arm/mve-vldr-bad-3.l: Modify. * testsuite/gas/arm/mve-vldr-bad-3.s: Likewise. * testsuite/gas/arm/mve-vstrldr-1.d: Likewise. * testsuite/gas/arm/mve-vstrldr-1.s: Likewise.
2019-09-23ecoff bfd.h tidyAlan Modra3-0/+7
bfd/ * bfd-in.h: Move ecoff function declarations.. * ecoff-bfd.h: ..to here, new file. * ecoff.c: Include ecoff-bfd.h. * ecofflink.c: Likewise. * elf64-alpha.c: Likewise. * elfxx-mips.c: Likewise. * bfd-in2.h: Regenerate. gas/ * config/obj-ecoff.c: Include ecoff-bfd.h. * config/obj-elf.c: Likewise.
2019-09-23arm bfd.h tidyAlan Modra2-0/+5
bfd/ * bfd-in.h: Move arm declaraions.. * cpu-arm.h: ..to here, new file.. * coff-arm.h: ..and here, new file.. * elf32-arm.h: ..and here, new file. * cpu-arm.c: Include cpu-arm.h. * coff-arm.c: Include cpu-arm.h and coff-arm.h. * elf32-arm.c: Include cpu-arm.h and elf32-arm.h. * pe-arm.c: Move function rename defines later. * pe-arm-wince.c: Likewise and include sysdep.h and bfd.h early. * bfd-in2.h: Regenerate. gas/ * config/tc-arm.c: Include cpu-arm.h. ld/ * emultempl/armelf.em: Include elf32-arm.h. * emultempl/pe.em: Move func defines later and include coff-arm.h.
2019-09-21tc-i386.c gcc10 warning fixAlan Modra2-2/+6
.../gas/config/tc-i386.c: In function ‘md_parse_option’: .../gas/config/tc-i386.c:11441:9: error: implicit conversion from ‘enum <anonymous>’ to ‘enum <anonymous>’ [-Werror=enum-conversion] 11441 | vexwig = evexw0; | ^ .../gas/config/tc-i386.c:11443:9: error: implicit conversion from ‘enum <anonymous>’ to ‘enum <anonymous>’ [-Werror=enum-conversion] 11443 | vexwig = evexw1; | ^ * config/tc-i386.c (md_parse_option): Fix warning on vexwig assignment.
2019-09-20bfd macro conversion to inline functions, sectionAlan Modra2-1/+5
This one exposed a bug in tic6x gas, found with inline function parameter type checking. struct bfd_section and struct bfd_symbol both have a flags field, so bfd_is_com_section (symbol) compiled OK when bfd_is_com_section was a macro but didn't special case common symbols. bfd/ * bfd-in.h (bfd_section_name, bfd_section_size, bfd_section_vma), (bfd_section_lma, bfd_section_alignment, bfd_section_flags), (bfd_section_userdata, bfd_is_com_section, discarded_section), (bfd_get_section_limit_octets, bfd_get_section_limit): Delete macros. * bfd.c (bfd_get_section_limit_octets, bfd_get_section_limit), (bfd_section_list_remove, bfd_section_list_append), (bfd_section_list_prepend, bfd_section_list_insert_after), (bfd_section_list_insert_before, bfd_section_removed_from_list): New inline functions. * section.c (bfd_is_und_section, bfd_is_abs_section), (bfd_is_ind_section, bfd_is_const_section, bfd_section_list_remove), (bfd_section_list_append, bfd_section_list_prepend), (bfd_section_list_insert_after, bfd_section_list_insert_before), (bfd_section_removed_from_list): Delete macros. (bfd_section_name, bfd_section_size, bfd_section_vma), (bfd_section_lma, bfd_section_alignment, bfd_section_flags), (bfd_section_userdata, bfd_is_com_section, bfd_is_und_section), (bfd_is_abs_section, bfd_is_ind_section, bfd_is_const_section), (discarded_section): New inline functions. * bfd-in2.h: Regenerate. gas/ * config/tc-tic6x.c (tc_gen_reloc): Correct common symbol check. ld/ * emultempl/xtensaelf.em (xtensa_get_section_deps): Comment. Use bfd_section_userdata. (xtensa_set_section_deps): Use bfd_set_section_userdata. * ldlang.c (lang_output_section_get): Use bfd_section_userdata. (sort_def_symbol): Likewise, and bfd_set_section_userdata. (init_os): Use bfd_set_section_userdata. (print_all_symbols): Use bfd_section_userdata. * ldlang.h (get_userdata): Delete.
2019-09-20x86-64: fix handling of PUSH/POP of segment registerJan Beulich4-4/+25
Commit 21df382b91 ("x86: fold SReg{2,3}") went too far: Folding 64-bit PUSH/POP templates into non-64-bit ones isn't correct, due to the different operand widths, and hence suffixes permitted. Restore the separate templates. Add tests of PUSH/POP with q suffix and %fs/%gs operands to the testsuite. While doing so also add PUSHF/POPF ones _without_ suffix.
2019-09-19[gas][news] NEWS (2.33) note new SVE2 and TME instructions for AArch64Matthew Malcomson2-0/+10
These NEWS entries had been missed when the instructions were added. gas/ChangeLog: 2019-09-19 Matthew Malcomson <matthew.malcomson@arm.com> * NEWS: Add SVE2 and TME entries.
2019-09-19bfd_section_* macrosAlan Modra73-370/+358
This large patch removes the unnecessary bfd parameter from various bfd section macros and functions. The bfd is hardly ever used and if needed for the bfd_set_section_* or bfd_rename_section functions can be found via section->owner except for the com, und, abs, and ind std_section special sections. Those sections shouldn't be modified anyway. The patch also removes various bfd_get_section_<field> macros, replacing their use with bfd_section_<field>, and adds bfd_set_section_lma. I've also fixed a minor bug in gas where compressed section renaming was done directly rather than calling bfd_rename_section. This would have broken bfd_get_section_by_name and similar functions, but that hardly mattered at such a late stage in gas processing. bfd/ * bfd-in.h (bfd_get_section_name, bfd_get_section_vma), (bfd_get_section_lma, bfd_get_section_alignment), (bfd_get_section_size, bfd_get_section_flags), (bfd_get_section_userdata): Delete. (bfd_section_name, bfd_section_size, bfd_section_vma), (bfd_section_lma, bfd_section_alignment): Lose bfd parameter. (bfd_section_flags, bfd_section_userdata): New. (bfd_is_com_section): Rename parameter. * section.c (bfd_set_section_userdata, bfd_set_section_vma), (bfd_set_section_alignment, bfd_set_section_flags, bfd_rename_section), (bfd_set_section_size): Delete bfd parameter, rename section parameter. (bfd_set_section_lma): New. * bfd-in2.h: Regenerate. * mach-o.c (bfd_mach_o_init_section_from_mach_o): Delete bfd param, update callers. * aoutx.h, * bfd.c, * coff-alpha.c, * coff-arm.c, * coff-mips.c, * coff64-rs6000.c, * coffcode.h, * coffgen.c, * cofflink.c, * compress.c, * ecoff.c, * elf-eh-frame.c, * elf-hppa.h, * elf-ifunc.c, * elf-m10200.c, * elf-m10300.c, * elf-properties.c, * elf-s390-common.c, * elf-vxworks.c, * elf.c, * elf32-arc.c, * elf32-arm.c, * elf32-avr.c, * elf32-bfin.c, * elf32-cr16.c, * elf32-cr16c.c, * elf32-cris.c, * elf32-crx.c, * elf32-csky.c, * elf32-d10v.c, * elf32-epiphany.c, * elf32-fr30.c, * elf32-frv.c, * elf32-ft32.c, * elf32-h8300.c, * elf32-hppa.c, * elf32-i386.c, * elf32-ip2k.c, * elf32-iq2000.c, * elf32-lm32.c, * elf32-m32c.c, * elf32-m32r.c, * elf32-m68hc1x.c, * elf32-m68k.c, * elf32-mcore.c, * elf32-mep.c, * elf32-metag.c, * elf32-microblaze.c, * elf32-moxie.c, * elf32-msp430.c, * elf32-mt.c, * elf32-nds32.c, * elf32-nios2.c, * elf32-or1k.c, * elf32-ppc.c, * elf32-pru.c, * elf32-rl78.c, * elf32-rx.c, * elf32-s390.c, * elf32-score.c, * elf32-score7.c, * elf32-sh.c, * elf32-spu.c, * elf32-tic6x.c, * elf32-tilepro.c, * elf32-v850.c, * elf32-vax.c, * elf32-visium.c, * elf32-xstormy16.c, * elf32-xtensa.c, * elf64-alpha.c, * elf64-bpf.c, * elf64-hppa.c, * elf64-ia64-vms.c, * elf64-mmix.c, * elf64-ppc.c, * elf64-s390.c, * elf64-sparc.c, * elf64-x86-64.c, * elflink.c, * elfnn-aarch64.c, * elfnn-ia64.c, * elfnn-riscv.c, * elfxx-aarch64.c, * elfxx-mips.c, * elfxx-sparc.c, * elfxx-tilegx.c, * elfxx-x86.c, * i386msdos.c, * linker.c, * mach-o.c, * mmo.c, * opncls.c, * pdp11.c, * pei-x86_64.c, * peicode.h, * reloc.c, * section.c, * syms.c, * vms-alpha.c, * xcofflink.c: Update throughout for bfd section macro and function changes. binutils/ * addr2line.c, * bucomm.c, * coffgrok.c, * dlltool.c, * nm.c, * objcopy.c, * objdump.c, * od-elf32_avr.c, * od-macho.c, * od-xcoff.c, * prdbg.c, * rdcoff.c, * rddbg.c, * rescoff.c, * resres.c, * size.c, * srconv.c, * strings.c, * windmc.c: Update throughout for bfd section macro and function changes. gas/ * as.c, * as.h, * dw2gencfi.c, * dwarf2dbg.c, * ecoff.c, * read.c, * stabs.c, * subsegs.c, * subsegs.h, * write.c, * config/obj-coff-seh.c, * config/obj-coff.c, * config/obj-ecoff.c, * config/obj-elf.c, * config/obj-macho.c, * config/obj-som.c, * config/tc-aarch64.c, * config/tc-alpha.c, * config/tc-arc.c, * config/tc-arm.c, * config/tc-avr.c, * config/tc-bfin.c, * config/tc-bpf.c, * config/tc-d10v.c, * config/tc-d30v.c, * config/tc-epiphany.c, * config/tc-fr30.c, * config/tc-frv.c, * config/tc-h8300.c, * config/tc-hppa.c, * config/tc-i386.c, * config/tc-ia64.c, * config/tc-ip2k.c, * config/tc-iq2000.c, * config/tc-lm32.c, * config/tc-m32c.c, * config/tc-m32r.c, * config/tc-m68hc11.c, * config/tc-mep.c, * config/tc-microblaze.c, * config/tc-mips.c, * config/tc-mmix.c, * config/tc-mn10200.c, * config/tc-mn10300.c, * config/tc-msp430.c, * config/tc-mt.c, * config/tc-nds32.c, * config/tc-or1k.c, * config/tc-ppc.c, * config/tc-pru.c, * config/tc-rl78.c, * config/tc-rx.c, * config/tc-s12z.c, * config/tc-s390.c, * config/tc-score.c, * config/tc-score7.c, * config/tc-sh.c, * config/tc-sparc.c, * config/tc-spu.c, * config/tc-tic4x.c, * config/tc-tic54x.c, * config/tc-tic6x.c, * config/tc-tilegx.c, * config/tc-tilepro.c, * config/tc-v850.c, * config/tc-visium.c, * config/tc-wasm32.c, * config/tc-xc16x.c, * config/tc-xgate.c, * config/tc-xstormy16.c, * config/tc-xtensa.c, * config/tc-z8k.c: Update throughout for bfd section macro and function changes. * write.c (compress_debug): Use bfd_rename_section. gdb/ * aarch64-linux-tdep.c, * arm-tdep.c, * auto-load.c, * coff-pe-read.c, * coffread.c, * corelow.c, * dbxread.c, * dicos-tdep.c, * dwarf2-frame.c, * dwarf2read.c, * elfread.c, * exec.c, * fbsd-tdep.c, * gcore.c, * gdb_bfd.c, * gdb_bfd.h, * hppa-tdep.c, * i386-cygwin-tdep.c, * i386-fbsd-tdep.c, * i386-linux-tdep.c, * jit.c, * linux-tdep.c, * machoread.c, * maint.c, * mdebugread.c, * minidebug.c, * mips-linux-tdep.c, * mips-sde-tdep.c, * mips-tdep.c, * mipsread.c, * nto-tdep.c, * objfiles.c, * objfiles.h, * osabi.c, * ppc-linux-tdep.c, * ppc64-tdep.c, * record-btrace.c, * record-full.c, * remote.c, * rs6000-aix-tdep.c, * rs6000-tdep.c, * s390-linux-tdep.c, * s390-tdep.c, * solib-aix.c, * solib-dsbt.c, * solib-frv.c, * solib-spu.c, * solib-svr4.c, * solib-target.c, * spu-linux-nat.c, * spu-tdep.c, * symfile-mem.c, * symfile.c, * symmisc.c, * symtab.c, * target.c, * windows-nat.c, * xcoffread.c, * cli/cli-dump.c, * compile/compile-object-load.c, * mi/mi-interp.c: Update throughout for bfd section macro and function changes. * gcore (gcore_create_callback): Use bfd_set_section_lma. * spu-tdep.c (spu_overlay_new_objfile): Likewise. gprof/ * corefile.c, * symtab.c: Update throughout for bfd section macro and function changes. ld/ * ldcref.c, * ldctor.c, * ldelf.c, * ldlang.c, * pe-dll.c, * emultempl/aarch64elf.em, * emultempl/aix.em, * emultempl/armcoff.em, * emultempl/armelf.em, * emultempl/cr16elf.em, * emultempl/cskyelf.em, * emultempl/m68hc1xelf.em, * emultempl/m68kelf.em, * emultempl/mipself.em, * emultempl/mmix-elfnmmo.em, * emultempl/mmo.em, * emultempl/msp430.em, * emultempl/nios2elf.em, * emultempl/pe.em, * emultempl/pep.em, * emultempl/ppc64elf.em, * emultempl/xtensaelf.em: Update throughout for bfd section macro and function changes. libctf/ * ctf-open-bfd.c: Update throughout for bfd section macro changes. opcodes/ * arc-ext.c: Update throughout for bfd section macro changes. sim/ * common/sim-load.c, * common/sim-utils.c, * cris/sim-if.c, * erc32/func.c, * lm32/sim-if.c, * m32c/load.c, * m32c/trace.c, * m68hc11/interp.c, * ppc/hw_htab.c, * ppc/hw_init.c, * rl78/load.c, * rl78/trace.c, * rx/gdb-if.c, * rx/load.c, * rx/trace.c: Update throughout for bfd section macro changes.
2019-09-18bfd_asymbol_* macrosAlan Modra2-2/+7
The main point of this patch is to give bfd_get_section a better name, bfd_asymbol_section. bfd/ * bfd-in.h (bfd_asymbol_section): Rename from bfd_get_section. (bfd_get_output_section): Delete. (bfd_asymbol_base): Delete. (bfd_asymbol_section, bfd_asymbol_value, bfd_asymbol_name), (bfd_asymbol_bfd, bfd_asymbol_flavour): Tidy. (bfd_set_asymbol_name): New macro. * bfd-in2.h: Regenerate. * aout-cris.c: Update throughout to use bfd_asymbol_section. * aoutx.h: Likewise. * cofflink.c: Likewise. * dwarf2.c: Likewise. * ecoff.c: Likewise. * elf.c: Likewise. * elf32-arm.c: Likewise. * elf32-mips.c: Likewise. * elf32-score.c: Likewise. * elf32-score7.c: Likewise. * elfn32-mips.c: Likewise. * elfnn-aarch64.c: Likewise. * elfxx-mips.c: Likewise. * linker.c: Likewise. * pdp11.c: Likewise. * elf64-mmix.c (mmix_elf_reloc): Expand bfd_get_output_section. binutils/ * nm.c: Update bfd_get_section to bfd_asymbol_section throughout. * objcopy.c: Likewise. * objdump.c: Likewise. * rdcoff.c: Likewise. * objcopy.c (create_new_symbol): Use bfd_set_asymbol_name. (filter_symbols): Likewise. gas/ * symbols.c (S_IS_LOCAL): Update bfd_get_section to bfd_asymbol_section. gdb/ * arm-tdep.c (arm_record_special_symbol): Update bfd_get_section to bfd_asymbol_section. ld/ * ldcref.c (check_reloc_refs): Update bfd_get_section to bfd_asymbol_section.
2019-09-18Re-generate many configure and Makefile.in filesSimon Marchi4-22/+14
I get some spurious changes when running autoconf/automake for various projects in the tree. This is likely because they were generated using distro-patched tools last time. I ran `autoreconf -f` in the various automake projects of the binutils-gdb tree, and this is the result. The tools I am using have been compiled from source, from the upstream release. bfd/ChangeLog: * Makefile.in: Re-generate. * configure: Re-generate. * doc/Makefile.in: Re-generate. binutils/ChangeLog: * Makefile.in: Re-generate. * configure: Re-generate. * doc/Makefile.in: Re-generate. gas/ChangeLog: * Makefile.in: Re-generate. * configure: Re-generate. * doc/Makefile.in: Re-generate. gold/ChangeLog: * testsuite/Makefile.in: Re-generate. gprof/ChangeLog: * Makefile.in: Re-generate. * configure: Re-generate. ld/ChangeLog: * Makefile.in: Re-generate. * configure: Re-generate. opcodes/ChangeLog: * Makefile.in: Re-generate. * configure: Re-generate.
2019-09-17RISC-V: Gate opcode tables by enum rather than string.Jim Wilson2-7/+26
Generalize opcode arch dependencies so that we can support the overlapping B extension Zb* subsets. 2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com> gas/ * config/tc-riscv.c (riscv_multi_subset_supports): Handle insn_class enum rather than subset char string. (riscv_ip): Update call to riscv_multi_subset_supports. include/ * opcode/riscv.h (riscv_insn_class): New enum. * opcode/riscv.h (struct riscv_opcode): Change subset field to insn_class field. opcodes/ * riscv-opc.c (riscv_opcodes): Change subset field to insn_class field for all instructions. (riscv_insn_types): Likewise.
2019-09-16Update version to 2.33.50 and regenerate configure scripts.Phil Blundell4-18/+36
2019-09-10Enhance the disassembler so that it will reliably determine whether a reloc ↵Nick Clifton3-0/+41
applies to the middle of the next insn. PR 24907 binutils* objdump.c (null_print): New function. (disassemble_bytes): Delete previous_octets local and replace with a test of the max_reloc_offset_into_insn field of the bfd_arch_info structure. If a reloc is a potential match for the next insn, then perform a dummy disassembly in order to calculate its real length. bfd * archures.c (bfd_arch_info_type): Add max_reloc_offset_into_insn field. (bfd_default_arch_struct): Initialise the new field. * bfd-in2.h: Regenerate. * cpu-aarch64.c: Initialise the new field. * cpu-alpha.c: Likewise. * cpu-arc.c: Likewise. * cpu-arm.c: Likewise. * cpu-avr.c: Likewise. * cpu-bfin.c: Likewise. * cpu-bpf.c: Likewise. * cpu-cr16.c: Likewise. * cpu-cr16c.c: Likewise. * cpu-cris.c: Likewise. * cpu-crx.c: Likewise. * cpu-csky.c: Likewise. * cpu-d10v.c: Likewise. * cpu-d30v.c: Likewise. * cpu-dlx.c: Likewise. * cpu-epiphany.c: Likewise. * cpu-fr30.c: Likewise. * cpu-frv.c: Likewise. * cpu-ft32.c: Likewise. * cpu-h8300.c: Likewise. * cpu-hppa.c: Likewise. * cpu-i386.c: Likewise. * cpu-ia64.c: Likewise. * cpu-iamcu.c: Likewise. * cpu-ip2k.c: Likewise. * cpu-iq2000.c: Likewise. * cpu-k1om.c: Likewise. * cpu-l1om.c: Likewise. * cpu-lm32.c: Likewise. * cpu-m10200.c: Likewise. * cpu-m10300.c: Likewise. * cpu-m32c.c: Likewise. * cpu-m32r.c: Likewise. * cpu-m68hc11.c: Likewise. * cpu-m68hc12.c: Likewise. * cpu-m68k.c: Likewise. * cpu-m9s12x.c: Likewise. * cpu-m9s12xg.c: Likewise. * cpu-mcore.c: Likewise. * cpu-mep.c: Likewise. * cpu-metag.c: Likewise. * cpu-microblaze.c: Likewise. * cpu-mips.c: Likewise. * cpu-mmix.c: Likewise. * cpu-moxie.c: Likewise. * cpu-msp430.c: Likewise. * cpu-mt.c: Likewise. * cpu-nds32.c: Likewise. * cpu-nfp.c: Likewise. * cpu-nios2.c: Likewise. * cpu-ns32k.c: Likewise. * cpu-or1k.c: Likewise. * cpu-pdp11.c: Likewise. * cpu-pj.c: Likewise. * cpu-plugin.c: Likewise. * cpu-powerpc.c: Likewise. * cpu-pru.c: Likewise. * cpu-riscv.c: Likewise. * cpu-rl78.c: Likewise. * cpu-rs6000.c: Likewise. * cpu-rx.c: Likewise. * cpu-s12z.c: Likewise. * cpu-s390.c: Likewise. * cpu-score.c: Likewise. * cpu-sh.c: Likewise. * cpu-sparc.c: Likewise. * cpu-spu.c: Likewise. * cpu-tic30.c: Likewise. * cpu-tic4x.c: Likewise. * cpu-tic54x.c: Likewise. * cpu-tic6x.c: Likewise. * cpu-tic80.c: Likewise. * cpu-tilegx.c: Likewise. * cpu-tilepro.c: Likewise. * cpu-v850.c: Likewise. * cpu-v850_rh850.c: Likewise. * cpu-vax.c: Likewise. * cpu-visium.c: Likewise. * cpu-wasm32.c: Likewise. * cpu-xc16x.c: Likewise. * cpu-xgate.c: Likewise. * cpu-xstormy16.c: Likewise. * cpu-xtensa.c: Likewise. * cpu-z80.c: Likewise. * cpu-z8k.c: Likewise. gas * testsuite/gas/arm/pr24907.s: New test. * testsuite/gas/arm/pr24907.d: Expected disassembly.
2019-09-10[PATCH][ARM][GAS]: Support to MVE VCTP instruction.Srinath Parvathaneni6-0/+177
This patch adds support for MVE VCTP instruction in assembler. gas ChangeLog: 2019-09-10 Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/tc-arm.c (M_MNEM_vctp): Add new Mnemonic. (do_mve_vctp): Add function to encode VCTP instruction. * testsuite/gas/arm/mve-vctp-bad.d: New test. * testsuite/gas/arm/mve-vctp-bad.l: Likewise. * testsuite/gas/arm/mve-vctp-bad.s: Likewise. * testsuite/gas/arm/mve-vctp.d: Likewise. * testsuite/gas/arm/mve-vctp.s: Likewise.
2019-09-09Add markers for 2.33 branch to NEWS and ChangeLog files.Phil Blundell2-0/+6
2019-09-05PowerPC warning on symbol+offset@gotAlan Modra2-3/+8
* config/tc-ppc.c (ppc_elf_suffix): Display the relocation operator on GOT reloc warnings/errors.
2019-08-30[PATCH][ARM][GAS]: Assembler support to interpret MVE VMOV instruction ↵Srinath Parvathaneni3-1/+86
correctly. This patch make changes to the assembler to encode MVE VMOV instruction "a" same as "b". a: VMOV<c><q> <Dd>, <Dm> b: VMOV<c><q>.F64 <Dd>, <Dm> gas/ChangeLog: 2019-08-30 Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/tc-arm.c (do_neon_mov): Modify "if" statement. * testsuite/gas/arm/mve-vmov-bad-3.d: New test. * testsuite/gas/arm/mve-vmov-bad-3.l: Likewise. * testsuite/gas/arm/mve-vmov-bad-3.s: Likewise.
2019-08-27Add support for the MVE VMOV instruction to the ARM assembler. This ↵Srinath Parvathaneni5-202/+243
instruction copies the value of one vector register to another vector register. The patch also modifies the decoding of VORR instruction which is effecting decoding of VMOV instruction. gas * config/tc-arm.c (parse_neon_mov): Add check to accept vector register to both the arguments in VMOV instruction. * testsuite/gas/arm/mve-vmov-1.d: Modify. * testsuite/gas/arm/mve-vmov-1.s: Likewise. * testsuite/gas/arm/mve-vorr.d: Likewise. opcodes * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC. (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC. (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
2019-08-25RISC-V: Improve li expansion for better code density.Kito Cheng5-5/+108
li is a pseudo instruction in RISC-V, it might expand to more than one instructions if the immediate value can't fit addi or lui, but the assembler will always using 4-byte instructions during expansion. For example: li a0, 0x12345001 will expand into 12345537 lui a0,0x12345 00150513 addi a0,a0,1 but addi could be compress into 0505 addi a0,a0,1 It because load_const use macro_build to emit instructions, and macro_build call append_insn, and expect it will compress it if possible, but the fact is append_insn never compress anything, So this patch redirect the li expansion flow to normal instruction emission flow via md_assemble, added md_assemblef as an wrapper for that for easier emit instruction with printf-style argument to build instruction. gas/ChangeLog: * tc-riscv.c (md_assemblef): New. (load_const) Use md_assemblef instead of macro_build to emit instructions. * testsuite/gas/riscv/li32.d: New. * testsuite/gas/riscv/li32.s: Ditto. * testsuite/gas/riscv/li64.d: Ditto. * testsuite/gas/riscv/li64.s: Ditto.
2019-08-23Updated Swedish translation for the gas sub-directory.Nick Clifton2-49/+26
2019-08-23 Nick Clifton <nickc@redhat.com> * po/sv.po: Updated Swedish translation.
2019-08-22Arm: Add support for missing CPUsDennis Zhang6-0/+39
This patch adds support for following CPUs: Cortex-M35P, Cortex-A77, Cortex-A76AE. Related specifications can be found at https://developer.arm.com/ip-products/processors. gas/ChangeLog: * config/tc-arm.c: New entries for Cortex-M35P, Cortex-A77, and Cortex-A76AE. * doc/c-arm.texi: Document new processors. * testsuite/gas/arm/cpu-cortex-a76ae.d: New test. * testsuite/gas/arm/cpu-cortex-a77.d: New test. * testsuite/gas/arm/cpu-cortex-m35p.d: New test. bfd/ChangeLog: * cpu-arm.c: New entries for Cortex-M35P, Cortex-A77, Cortex-A76AE.
2019-08-22Fix the assembler's floating point number parser so that it can correctly ↵Bosco Garc?a5-7/+49
handle numbers encoded as a leading decimal point, followed by zeroes, followed by a non-zero sequence. * atof-generic.c (atof_generic): Do not ignore leading zeros if they appear after a decimal point. * testsuite/gas/all/float.s: Extend test to include a number with a leading decimal point followed by several zeroes. * testsuite/gas/i386/fp.s: Likewise. * testsuite/gas/i386/fp.d: Update expected output.
2019-08-22Implement a float16 directive for assembling 16 bit IEEE 754 floating point ↵Barnaby Wilks7-5/+70
numbers for the AArch64 assembler. The syntax of the directive is: .float16 <0-n decimal numbers> e.g. .float16 0.5 .float16 10.2, NaN, 452.09 The floats will always be encoded using the binary16 format as described in the IEEE 754-2008 standard. There is no need to support Arm's alternative half-precision format since AArch64 only supports the IEEE format. gas * config/tc-aarch64.c: Add float16 directive and add "Hh" to acceptable float characters. * doc/c-aarch64.texi: Documentation for float16 directive. * testsuite/gas/aarch64/float16-be.d: New test. * testsuite/gas/aarch64/float16-le.d: New test. * testsuite/gas/aarch64/float16.s: New test. * NEWS: Add NEWS entry.
2019-08-22[AArch64][gas] Update MTE system register encodingsKyrylo Tkachov2-10/+15
The MTE specification adjusted the encoding of the TFSRE0_EL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12 system registers. This patch brings binutils up to date. The references for the encodings are at: https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsre0_el1 (also contains TFSR_EL12 description) https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsr_el1 https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsr_el2 https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsr_el3 Tested check-gas for aarch64-none-elf. opcodes/ * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1, tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12. (aarch64_sys_reg_supported_p): Update checks for the above. gas/ * testsuite/gas/aarch64/sysreg-4.d: Update expected disassembly for tfsre0_el1, tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12 system registers.
2019-08-20Remove test files for a different patch accidentally committed with patch ↵Nick Clifton2-35/+0
for ARM CPU additions.
2019-08-20Adds support for following CPUs to the ARM and Aarch64 assemblers: ↵Dennis Zhang12-0/+112
Cortex-A77, Cortex-A76AE, Cortex-A34, Cortex-A65, and Cortex-A65AE. Related specifications can be found at https://developer.arm.com/ip-products/processors. gas * NEWS: Mention the Arm and AArch64 new processors. * config/tc-aarch64.c: New entries for Cortex-A34, Cortex-A65, Cortex-A77, cortex-A65AE, and Cortex-A76AE. * doc/c-aarch64.texi: Document new CPUs. * testsuite/gas/aarch64/cpu-cortex-a34.d: New test. * testsuite/gas/aarch64/cpu-cortex-a65.d: New test. * testsuite/gas/aarch64/cpu-cortex-a65ae.d: New test. * testsuite/gas/aarch64/cpu-cortex-a76ae.d: New test. * testsuite/gas/aarch64/cpu-cortex-a77.d: New test. * testsuite/gas/aarch64/nop-asm.s: New test. bfd * cpu-aarch64.c: New entries for Cortex-A34, Cortex-A65, Cortex-A77, cortex-A65AE, and Cortex-A76AE.
2019-08-19MIPS/gas: Fix misaligned address errors to disregard ISA mode bitFaraz Shahbazker2-5/+32
gas/ * config/tc-mips.c (fix_bad_misaligned_address): New function. (fix_validate_branch): Call fix_bad_misaligned address_to calculate the target address. (md_apply_fix): Likewise. (md_convert_frag): Update misaligned address calculation to disregard ISA mode bit.
2019-08-19MIPS/gas: Retain ISA mode bit for labels with .insn annotationFaraz Shahbazker5-3/+45
gas/ * config/tc-mips.c (mips_move_labels): Retain ISA mode bit when moving labels in text segments. (mips_align): Indicate text mode when aligning labels in text segments. * gas/testsuite/gas/mips/insn-isa-mode.d: New test. * gas/testsuite/gas/mips/insn-isa-mode.s: New test source. * gas/testsuite/gas/mips/mips.exp: Run the new test.
2019-08-19Float16: Fix test failures for non ELF targetsBarnaby Wilks2-27/+26
The tests were failing due to md_atof trying to do word-wise endian switching on the float16 (for little-endian targets sometimes multi word values have their word order changed). However since a float16 is only 1 word wide, it would end up writing incorrect data, as you cannot switch the word order of just one word. * config/tc-arm.c (md_atof): Add precision check. Formatting.
2019-08-15Updatesd Swdish translation for the gas sub-directory.Nick Clifton2-872/+466
* po/sv.po: Updated Swedish translation.
2019-08-12Modify the ARM encoding and decoding of SQRSHRL and UQRSHLL MVE instructions.Srinath Parvathaneni6-8/+76
This is a change to the first published specifications [1][a] but since there is no hardware out there that uses the old instructions we do not want to support the old variant. This changes are done based on the latest published specifications [1][b]. [1] https://developer.arm.com/architectures/cpu-architecture/m-profile/docs/ddi0553/latest/armv81-m-architecture-reference-manual [a] version bf [b] version bh gas * config/tc-arm.c (enum operand_parse_code): Add the entry OP_I48_I64. (po_imm1_or_imm2_or_fail): Marco to check the immediate is either of 48 or 64. (parse_operands): Add case OP_I48_I64. (do_mve_scalar_shift1): Add function to encode the MVE shift instructions with 4 arguments. * testsuite/gas/arm/mve-shift-bad.l: Modify. * testsuite/gas/arm/mve-shift-bad.s: Likewise. * testsuite/gas/arm/mve-shift.d: Likewise. * testsuite/gas/arm/mve-shift.s: Likewise. opcodes * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for cases MVE_SQRSHRL and MVE_UQRSHLL. (print_insn_mve): Add case for specifier 'k' to check specific bit of the instruction.
2019-08-12Add generic and ARM specific support for half-precision IEEE 754 floating ↵Barnaby Wilks20-8/+324
point numbers to the assembler. Half precision floating point numbers will be encoded using the IEEE 754 half precision floating point format - 16 bits in total, 1 for sign, 5 for exponent and 10 bits of mantissa. This patch implements the float16 directive for both the IEEE 754 format and the Arm alternative format for the Arm backend. The syntax of the directive is: .float16 <0-n decimal numbers> e.g. .float16 12.0 .float16 0.23, 433.1, 0.06 The Arm alternative format is almost identical to the IEEE 754 format, except that it doesn't encode for NaNs or Infinity (instead an exponent of 0x1F represents a normalized number in the range 65536 to 131008). The alternative format is documented in the reference manual: https://static.docs.arm.com/ddi0487/db/DDI0487D_b_armv8_arm.pdf?_ga=2.72318806.49764181.1561632697-999473562.1560847439 Which format is used is controlled by the .float16_format <format> directive, where if <format> = ieee, then use the IEEE 754 half-precision format else if <format> = alternative, then use the Arm alternative format Or the format can be set on the command line via the -mfp16-format option that has a similar syntax. -mfp16-format=<ieee|alternative>. This also fixes the format and it cannot be changed by any directives. Once the format has been set (either by the command line option or a directive) it cannot be changed, and any attempts to change it (i.e. with the float16_format directive) will result in a warning and the line being ignored. For ELF targets the appropriate EABI attribute will be written out at the end of assembling if the format has been explicitly specified. If no format has been explicitly specified then no EABI attributes will be written. If the format is not explicitly specified then any float16 directives are encoding using the IEEE 754-2008 format by default until the format is fixed or changed with the float16_format directive. gas * config/tc-arm.c (enum fp_16bit_format): Add enum to represent the 2 float16 encodings. (md_atof): Set precision for float16 type. (arm_is_largest_exponent_ok): Check for whether to encode with the IEEE or alternative format. (set_fp16_format): Parse a float16_format directive. (arm_parse_fp16_opt): Parse the fp16-format command line option. (aeabi_set_public_attributes): For ELF encode the FP16 format EABI attribute. * config/tc-arm.h (TC_LARGEST_EXPONENT_IS_NORMAL): Macro that expands to arm_is_largest_exponent_ok. (arm_is_largest_exponent_ok): Add prototype for arm_is_largest_exponent_ok function. * doc/c-arm.texi: Add documentation for .float16, .float16_format and -mfp16-format= * testsuite/gas/arm/float16-bad.d: New test. * testsuite/gas/arm/float16-bad.l: New test. * testsuite/gas/arm/float16-bad.s: New test. * testsuite/gas/arm/float16-be.d: New test. * testsuite/gas/arm/float16-format-bad.d: New test. * testsuite/gas/arm/float16-format-bad.l: New test. * testsuite/gas/arm/float16-format-bad.s: New test. * testsuite/gas/arm/float16-format-opt-bad.d: New test. * testsuite/gas/arm/float16-format-opt-bad.l: New test. * testsuite/gas/arm/float16-le.d: New test. * testsuite/gas/arm/float16.s: New test. * testsuite/gas/arm/float16-eabi-alternative-format.d: New test. * testsuite/gas/arm/float16-eabi-ieee-format.d: New test. * testsuite/gas/arm/float16-eabi-no-format.d: New test. * testsuite/gas/arm/float16-eabi.s: New test. * config/atof-ieee.c (H_PRECISION): Macro for precision of float16 type. (atof_ieee): Set precision and exponent bits for encoding float16 types. (gen_to_words): NaN and Infinity encoding for float16. (ieee_md_atof): Set precision for encoding float16 type.
2019-08-12PR24851, gas/testsuite/gas/epiphany/badrelax.s failure with MALLOC_PERTURB_=1Alan Modra2-17/+28
PR 24851 * config/tc-epiphany.c (md_estimate_size_before_relax): Clear extra opcode bytes when changing from a 2-byte to a 4-byte insn.
2019-08-09x86-64: generalize SIMD test expectationsJan Beulich7-927/+212
In order to be able to add/remove insns to/from the middle of these tests, generalize the patterns for the symbol reference comments of RIP- relative operands.
2019-08-08Change the output of readelf's note display so that the "Data size" column ↵Nick Clifton5-4/+13
header is left justified. PR 24887 binutils* readelf.c (process_notes_at): Left justify the "Data size" column heading. * testsuite/binutils-all/i386/empty.d: Adjust for new output format. * testsuite/binutils-all/i386/ibt.d: Likewise. * testsuite/binutils-all/i386/pr21231a.d: Likewise. * testsuite/binutils-all/i386/pr21231b.d: Likewise. * testsuite/binutils-all/i386/shstk.d: Likewise. * testsuite/binutils-all/note-2-32.d: Likewise. * testsuite/binutils-all/note-2-64.d: Likewise. * testsuite/binutils-all/x86-64/empty-x32.d: Likewise. * testsuite/binutils-all/x86-64/empty.d: Likewise. * testsuite/binutils-all/x86-64/ibt-x32.d: Likewise. * testsuite/binutils-all/x86-64/ibt.d: Likewise. * testsuite/binutils-all/x86-64/pr21231a.d: Likewise. * testsuite/binutils-all/x86-64/pr21231b.d: Likewise. * testsuite/binutils-all/x86-64/pr23494a-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494a.d: Likewise. * testsuite/binutils-all/x86-64/pr23494c-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494c.d: Likewise. * testsuite/binutils-all/x86-64/pr23494d-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494d.d: Likewise. * testsuite/binutils-all/x86-64/pr23494e-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494e.d: Likewise. * testsuite/binutils-all/x86-64/shstk-x32.d: Likewise. * testsuite/binutils-all/x86-64/shstk.d: Likewise. ld * testsuite/ld-aarch64/bti-plt-2.d: Adjust for new output format from readelf. * testsuite/ld-aarch64/bti-plt-4.d: Likewise. * testsuite/ld-aarch64/bti-plt-6.d: Likewise. * testsuite/ld-aarch64/bti-plt-7.d: Likewise. * testsuite/ld-aarch64/bti-warn.d: Likewise. * testsuite/ld-aarch64/property-bti-pac1.d: Likewise. * testsuite/ld-aarch64/property-bti-pac2.d: Likewise. * testsuite/ld-aarch64/property-bti-pac3.d: Likewise. * testsuite/ld-elf/x86-feature-1a.rd: Likewise. * testsuite/ld-elf/x86-feature-1b.rd: Likewise. * testsuite/ld-elf/x86-feature-1c.rd: Likewise. * testsuite/ld-elf/x86-feature-1d.rd: Likewise. * testsuite/ld-elf/x86-feature-1e.rd: Likewise. * testsuite/ld-i386/ibt-plt-2d.d: Likewise. * testsuite/ld-i386/ibt-plt-3d.d: Likewise. * testsuite/ld-i386/pr23372a.d: Likewise. * testsuite/ld-i386/pr23372c.d: Likewise. * testsuite/ld-i386/pr23486a.d: Likewise. * testsuite/ld-i386/pr23486b.d: Likewise. * testsuite/ld-i386/pr23486c.d: Likewise. * testsuite/ld-i386/pr23486d.d: Likewise. * testsuite/ld-i386/pr24322a.d: Likewise. * testsuite/ld-i386/pr24322b.d: Likewise. * testsuite/ld-i386/property-x86-3.d: Likewise. * testsuite/ld-i386/property-x86-4a.d: Likewise. * testsuite/ld-i386/property-x86-5.d: Likewise. * testsuite/ld-i386/property-x86-cet1.d: Likewise. * testsuite/ld-i386/property-x86-cet2a.d: Likewise. * testsuite/ld-i386/property-x86-cet5a.d: Likewise. * testsuite/ld-i386/property-x86-cet5b.d: Likewise. * testsuite/ld-i386/property-x86-ibt1a.d: Likewise. * testsuite/ld-i386/property-x86-ibt1b.d: Likewise. * testsuite/ld-i386/property-x86-ibt2.d: Likewise. * testsuite/ld-i386/property-x86-ibt3a.d: Likewise. * testsuite/ld-i386/property-x86-ibt3b.d: Likewise. * testsuite/ld-i386/property-x86-ibt4.d: Likewise. * testsuite/ld-i386/property-x86-ibt5.d: Likewise. * testsuite/ld-i386/property-x86-shstk1a.d: Likewise. * testsuite/ld-i386/property-x86-shstk1b.d: Likewise. * testsuite/ld-i386/property-x86-shstk2.d: Likewise. * testsuite/ld-i386/property-x86-shstk3a.d: Likewise. * testsuite/ld-i386/property-x86-shstk3b.d: Likewise. * testsuite/ld-i386/property-x86-shstk4.d: Likewise. * testsuite/ld-i386/property-x86-shstk5.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2d-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2d.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3d-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3d.d: Likewise. * testsuite/ld-x86-64/pr23372a-x32.d: Likewise. * testsuite/ld-x86-64/pr23372a.d: Likewise. * testsuite/ld-x86-64/pr23372c-x32.d: Likewise. * testsuite/ld-x86-64/pr23372c.d: Likewise. * testsuite/ld-x86-64/pr23486a-x32.d: Likewise. * testsuite/ld-x86-64/pr23486a.d: Likewise. * testsuite/ld-x86-64/pr23486b-x32.d: Likewise. * testsuite/ld-x86-64/pr23486b.d: Likewise. * testsuite/ld-x86-64/pr23486c-x32.d: Likewise. * testsuite/ld-x86-64/pr23486c.d: Likewise. * testsuite/ld-x86-64/pr23486d-x32.d: Likewise. * testsuite/ld-x86-64/pr23486d.d: Likewise. * testsuite/ld-x86-64/pr24322a-x32.d: Likewise. * testsuite/ld-x86-64/pr24322a.d: Likewise. * testsuite/ld-x86-64/pr24322b-x32.d: Likewise. * testsuite/ld-x86-64/pr24322b.d: Likewise. * testsuite/ld-x86-64/pr24458a-x32.d: Likewise. * testsuite/ld-x86-64/pr24458a.d: Likewise. * testsuite/ld-x86-64/pr24458b-x32.d: Likewise. * testsuite/ld-x86-64/pr24458b.d: Likewise. * testsuite/ld-x86-64/pr24458c-x32.d: Likewise. * testsuite/ld-x86-64/pr24458c.d: Likewise. * testsuite/ld-x86-64/property-1.r: Likewise. * testsuite/ld-x86-64/property-1a.r: Likewise. * testsuite/ld-x86-64/property-2.r: Likewise. * testsuite/ld-x86-64/property-2a.r: Likewise. * testsuite/ld-x86-64/property-3.r: Likewise. * testsuite/ld-x86-64/property-3a.r: Likewise. * testsuite/ld-x86-64/property-4.r: Likewise. * testsuite/ld-x86-64/property-4a.r: Likewise. * testsuite/ld-x86-64/property-5.r: Likewise. * testsuite/ld-x86-64/property-5a.r: Likewise. * testsuite/ld-x86-64/property-6.r: Likewise. * testsuite/ld-x86-64/property-7.r: Likewise. * testsuite/ld-x86-64/property-7a.r: Likewise. * testsuite/ld-x86-64/property-x86-3-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-3.d: Likewise. * testsuite/ld-x86-64/property-x86-4a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-4a.d: Likewise. * testsuite/ld-x86-64/property-x86-5-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-5.d: Likewise. * testsuite/ld-x86-64/property-x86-cet1-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet1.d: Likewise. * testsuite/ld-x86-64/property-x86-cet2a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet2a.d: Likewise. * testsuite/ld-x86-64/property-x86-cet5a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet5a.d: Likewise. * testsuite/ld-x86-64/property-x86-cet5b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet5b.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1a.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1b.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt2-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt2.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3a.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3b.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt4-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt4.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt5-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt5.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk1a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk1a.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk1b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk1b.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk2-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk2.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3a.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3b.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk4-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk4.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk5-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk5.d: Likewise. gas * testsuite/gas/i386/property-1.d: Adjust for new output format from readelf. * testsuite/gas/i386/property-2.d: Likewise. * testsuite/gas/i386/x86-64-property-1.d: Likewise. * testsuite/gas/i386/x86-64-property-2.d: Likewise.
2019-08-08Update the handling of shift rotate and load/store multiple instructions in ↵Yoshinori Sato1-4/+4
the H8300 assembler. incldue * opcode/h8300.h (EXPAND_UNOP_EXTENDED_B): Add MODEL. (EXPAND_UNOP_EXTENDED_W): Likewise. (EXPAND_UNOP_EXTENDED_L): Likewise. (struct h8_opcode h8_opcodes): Likewise. (struct h8_opcode h8_opcodes): tas / ldm / stm supported H8S or later.
2019-08-08Move the h8300 assembler's MOVFPE and MOVTPE tests to the correct location.Yoshinori Sato5-50/+56
* gas/testsuite/gas/h8300/h8300.exp: Fix movfpe and movtpe tests. * gas/testsuite/gas/h8300/misc.s: Likewise. * gas/testsuite/gas/h8300/misch.s: Likewise. * gas/testsuite/gas/h8300/miscs.s: Likewise.
2019-08-05Removes support in the ARM assembler for the unsigned variants of the ↵Barnaby Wilks12-2712/+55
VQ(R)DMLAH and VQ(R)DMLASH MVE instructions. Previously GAS would accept .u32, .u16 and .u8 suffixes to the VQ(R)DMLAH and VQ(R)DMLASH instructions, however the Armv8.1-M Mainline specification states that these functions only have signed variations (.s32, .s16 and .s8 suffixes). This is documented here: https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf?_ga=2.143079093.1892401233.1563295591-999473562.1560847439#page=1183 gas * config/tc-arm.c (do_mve_vqdmlah): Use N_S_32 macro. (do_neon_qrdmlah): Use N_S_32 macro. * testsuite/gas/arm/mve-vqdmlah-bad.d: New test. * testsuite/gas/arm/mve-vqdmlah-bad.l: New test. * testsuite/gas/arm/mve-vqdmlah-bad.s: New test. * testsuite/gas/arm/mve-vqdmlah.d: Remove unsigned instruction tests. * testsuite/gas/arm/mve-vqdmlah.s: Remove unsigned instruction tests. * testsuite/gas/arm/mve-vqdmlash-bad.d: New test. * testsuite/gas/arm/mve-vqdmlash-bad.l: New test. * testsuite/gas/arm/mve-vqdmlash-bad.s: New test. * testsuite/gas/arm/mve-vqdmlash.d: Remove unsigned instruction tests. * testsuite/gas/arm/mve-vqdmlash.s: Remove unsigned instruction tests. opcodes * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH instructions.
2019-07-30RISC-V: Fix minor issues with FP csr instructions.Jim Wilson5-1/+71
Mel Chen <mel.chen@sifive.com> gas/ * testsuite/gas/riscv/alias-csr.s: Add testcase for CSR-access alias instructions. * testsuite/gas/riscv/no-aliases-csr.d: Run testcase alias-csr.s with -Mno-aliases. * testsuite/gas/riscv/alias-csr.d: Run testcase alias-csr.s. * testsuite/gas/riscv/priv-reg.d: Update. opcodes/ * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm, fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions. * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr, fscsr.
2019-07-24Update the Swedish translation for the gas sub-directory.Nick Clifton2-4191/+5083
2019-07-24[ARC] Update disassembler opcode selectionClaudiu Zissulescu2-1/+5
New instruction are added, and some of them are overlapping. Update disassembler to correctly recognize them. Introduce nps400 option. opcodes/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes, and MPY class instructions. (parse_option): Add nps400 option. (print_arc_disassembler_options): Add nps400 info. gas/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/nps400-6.d: Update test.
generated by cgit v1.1 at 2024-11-21 14:58:57 +0000