aboutsummaryrefslogtreecommitdiff
path: root/gas
AgeCommit message (Collapse)AuthorFilesLines
2024-04-07Support APX NFCui, Lili10-10/+4212
For the case when NDD and NF are both 0 in evex-promoted format, we will fully support and test it in another patch. gas/ChangeLog: * NEWS: Support Intel APX NF. * config/tc-i386.c (enum i386_error): Add unsupported_nf. (struct _i386_insn): Add has_nf. (is_apx_evex_encoding): Ditto. (build_apx_evex_prefix): Encode the NF bit. (md_assemble): Handle unsupported_nf. (parse_insn): Handle Prefix_NF and report bad for illegal combination. (can_convert_NDD_to_legacy): Replace i.tm.opcode_modifier.nf with i.has_nf. (match_template): Support D for APX_F insns and check NF support. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Add bad test for NF bit. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. * testsuite/gas/i386/x86-64-apx-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-inval.s: Ditto. * testsuite/gas/i386/x86-64.exp: Add apx nf tests. * testsuite/gas/i386/x86-64-apx-nf-intel.d: New test. * testsuite/gas/i386/x86-64-apx-nf.d: Ditto. * testsuite/gas/i386/x86-64-apx-nf.s: Ditto. opcodes/ChangeLog: * i386-dis-evex.h: Add %NF to the instructions that support APX NF and add new instruction imul, popcnt, tzcnt and lzcnt to EVEX table. * i386-dis-evex-reg.h: Ditto. * i386-dis.c (struct instr_info): Add nf. (struct dis386): Add "NF" for EVEX.NF. (get_valid_dis386): Set ins->vex.nf and report bad-nf for illegal case. (print_insn): Handle ins.vex.nf. (putop): Handle "%NF". * i386-opc.h (Prefix_NF): New. * i386-opc.tbl: Added new entries to support full APX NF instructions. * i386-mnem.h: Regenerated. * i386-tbl.h: Regenerated.
2024-04-06Revert "x86: Restore APX shift-double instructions with omitted shift count"H.J. Lu3-18/+0
This reverts commit c2d698fe03a6092d58a07de96068b87836daced0. GCC 14 has been changed to use explicit shift count in shift-double instructions by the commit: 06a7e7514af x86: Use explicit shift count in double-precision shifts gas/ PR gas/31606 * testsuite/gas/i386/x86-64-apx-ndd-wig.d: Updated. * testsuite/gas/i386/x86-64-apx-ndd.d: Likewise. * testsuite/gas/i386/x86-64-apx-ndd.s: Remove tests for APX shift-double instructions with omitted shift count. opcodes/ PR gas/31606 * i386-opc.tbl: Remove APX shift-double instructions with omitted shift count. * i386-tbl.h: Regenerated.
2024-04-05Add missing install-dvi and install-ps Makefie targets.Christophe Lyon1-0/+2
For some reason, these targets are missing although others from the same family are present. This looks like an oversight. This enables calling 'make install-dvi' from the top-level build directory.
2024-04-04x86: Restore APX shift-double instructions with omitted shift countH.J. Lu3-0/+18
Restore APX shift-double instructions with omitted shift count since they are generated by GCC as shown in: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114590 gas/ PR gas/31606 * testsuite/gas/i386/x86-64-apx-ndd-wig.d: Updated. * testsuite/gas/i386/x86-64-apx-ndd.d: Likewise. * testsuite/gas/i386/x86-64-apx-ndd.s: Add tests for APX shift-double instructions with omitted shift count. opcodes/ PR gas/31606 * i386-opc.tbl: Restore APX shift-double instructions with omitted shift count. * i386-tbl.h: Regenerated.
2024-04-03x86/APX: Remove KEYLOCKER and SHA promotions from EVEX MAP4Cui, Lili10-169/+9
APX spec removed KEYLOCKER and SHA promotions from EVEX MAP4. https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html gas/ChangeLog: * NEWS: Mention that remove KEYLOCKER and SHA promotions from EVEX * MAP4. * config/tc-i386.c (process_operands): Removed special handling of * KEYLOCKER and SHA. * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.l: Removed KEYLOCKER * and SHA instructions. * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-prefix.h: Removed KEYLOCKER and SHA instructions. * i386-dis-evex.h: Ditto. * i386-opc.tbl: Ditto. * i386-dis.c (print_vector_reg): Removed special handling of KEYLOCKER * and SHA.
2024-04-01LoongArch: gas: Ignore .align if it is at the start of a sectionmengqinggang3-25/+128
Ignore .align if it is at the start of a section and the alignment can be divided by the section alignment, the section alignment can ensure this .align has a correct alignment.
2024-03-31BFD: Fix the bug of R_LARCH_AGLIN caused by discard sectionmengqinggang2-7/+4
To represent the first and third expression of .align, R_LARCH_ALIGN need to associate with a symbol. We define a local symbol for R_LARCH_AGLIN. But if the section of the local symbol is discarded, it may result in a undefined symbol error. Instead, we use the section name symbols, and this does not need to add extra symbols. During partial linking (ld -r), if the symbol associated with a relocation is STT_SECTION type, the addend of relocation needs to add the section output offset. We prevent it for R_LARCH_ALIGN. The elf_backend_data.rela_normal only can set all relocations of a target to rela_normal. Add a new function is_rela_normal to elf_backend_data, it can set part of relocations to rela_normal.
2024-03-28gas: gcfg: fix handling of non-local direct jmps in gcfgIndu Bhagat5-19/+104
The ginsn infrastructure in GAS includes the ability to create a GCFG (ginsn CFG). A GCFG is currently used for SCFI passes. This patch fixes the following invalid assumptions / code blocks: - The function ginsn_direct_local_jump_p () was erroneously _not_ checking whether the symbol is locally defined (i.e., within the scope of the code block for which GCFG is desired). Fix the code to do so. - Similarly, the GCFG creation code, in gcfg_build () itself had an assumption that a GINSN_TYPE_JUMP to a non-local symbol will not be seen. The latter can indeed be seen, and in fact, needs to be treated the same way as an exit from the function in terms of control-flow. gas/ * ginsn.c (ginsn_direct_local_jump_p): Check if the symbol is local to the code block or function being assembled. (add_bb_at_ginsn): Remove buggy assumption. (frch_ginsn_data_append): Direct jmps do not disqualify a stream of ginsns from GCFG creation. gas/testsuite/ * gas/scfi/x86_64/scfi-cfg-3.d: New test. * gas/scfi/x86_64/scfi-cfg-3.l: New test. * gas/scfi/x86_64/scfi-cfg-3.s: New test. * gas/scfi/x86_64/scfi-x86-64.exp: Add new test.
2024-03-28x86/SSE2AVX: move checkingJan Beulich1-11/+10
It has always been looking a little odd to me that this was done deep in cpu_flags_match(). Move it to match_template() itself - there's no need to do anything complex when encountering such a template while it cannot possibly be used.
2024-03-28x86/SSE2AVX: respect prefixesJan Beulich3-2/+21
1) Without -msse2avx we unconditionally honor REX.W. Hence we ought to also do so with -msse2avx, converting to VEX.W. 2) {rex} doesn't prevent conversion to VEX encodings. Thus {rex2} shouldn't either.
2024-03-28gas: drop integer_constant()'s maxdigJan Beulich1-8/+4
Once properly set, it's only ever holding the same value as "radix". Even if there was some plan with it, that plan hasn't made it anywhere in over 20 years.
2024-03-28gas: drop dead check for double quoteJan Beulich1-3/+0
FB and dollar label definitions can't be enclosed in double quotes. In fact at that point nul_char is the same as next_char, which we know is a digit.
2024-03-28gas: sanitize FB- and dollar-label usesJan Beulich4-20/+31
I don't view it as sensible to be more lax when it comes to references to (uses of) such labels compared to their definition: The latter has been limited to decimal numerics, while the former permitted any radix. Beyond that leading zeroes on such labels aren't helpful either. Imo labels and their use sites would better match literally, to avoid confusion. As it turns out, one z80 testcase actually had such an odd use of labels where definition and use don't match in spelling. That testcase is being adjusted accordingly. While there also adjust a comment on a local variable in integer_constant().
2024-03-28RISC-V: Removed privileged spec 1.9.1 support in assembler.Nelson Chu17-2873/+22
Removed since it's may have lots of conflicts with the newer extensions, but still keep linker recognizes it in case of linking old objects. gas/ * NEWS: Updated. * config/tc-riscv.c (riscv_set_default_priv_spec): Regard 1.9.1 as an unknown version. (md_show_usage): Removed privileged spec 1.9.1 information. * testsuite/gas/riscv/attribute-05.s: Updated since privileged spec 1.9.1 is unsupported. * testsuite/gas/riscv/attribute-05.d: Likewise. * testsuite/gas/riscv/attribute-12.d: Likewise. * testsuite/gas/riscv/attribute-13.d: Likewise. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr-dw-regnums.s: Likewise. * testsuite/gas/riscv/csr.s: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.d: Removed. * testsuite/gas/riscv/csr-version-1p9p1.l: Removed. include/ * opcode/riscv-opc.h: Updated since privileged spec 1.9.1 is unsupported. ld/ * testsuite/ld-riscv-elf/attr-merge-priv-spec-01.d: Updated since privileged spec 1.9.1 is unsupported. * testsuite/ld-riscv-elf/attr-merge-priv-spec-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-04.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-05.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-06.d: Likewise.
2024-03-22x86: fix Solaris testsuite failuresJan Beulich2-7/+4
For one 0afc614c9938 ("x86: Warn .insn instruction with length > 15 bytes") introduced a .insn use involving a slash; such tests need to have --divide passed to gas. And then 5bc71c2a6b8e ("x86-64: Add R_X86_64_CODE_6_GOTTPOFF") broke BFD_RELOC_X86_64_GOTTPOFF conversion to R_X86_64_CODE_4_GOTTPOFF, by adding respective code in a section guarded by generate_relax_relocations (the case of that not being required there was limited to 32-bit object files). Re-arrange that block of code to check generate_relax_relocations later.
2024-03-21New Romanian translation for gas sub-directoryNick Clifton1-0/+23890
2024-03-19gas, aarch64: Add faminmax extensionSaurabh Jha23-0/+1119
2024-03-19LoongArch: Add relaxation for R_LARCH_CALL36mengqinggang5-147/+175
This relaxation is effective for both macro instructions (call36, tail36) and explicit relocation instructions (pcaddu18i + jirl). call36 f -> bl f R_LARCH_CALL36 -> R_LARCH_B26 tail36 $t0, f -> b f R_LARCH_CALL36 -> R_LARCH_B26
2024-03-18aarch64: Add support for SVE ADDPT, SUBPT, MADPT, MLAPT instructionsYury Khrustalev9-2/+311
The following instructions are added in this patch: - ADDPT (predicated): Add checked pointer vectors (predicated). - ADDPT (unpredicated): Add checked pointer vectors (unpredicated). - SUBPT (predicated): Subtract checked pointer vectors (predicated). - SUBPT (unpredicated): Subtract checked pointer vectors (unpredicated). - MADPT: Multiply-add checked pointer vectors, writing multiplicand - MLAPT: Multiply-add checked pointer vectors, writing addend These instructions are part of Checked Pointer Arithmetic extension and are enabled when both CPA and SVE are enabled. To achieve this, both flag "+sve" and "+cpa" should be active. This patch adds assembler and disassembler support for these instructions with relevant checks. Tests are included as well. Regression tested on the aarch64-none-linux-gnu target and no regressions have been found.
2024-03-18aarch64: Add support for (M)ADDPT and (M)SUBPT instructionsYury Khrustalev9-0/+232
The following instructions are added in this patch: - ADDPT and SUBPT - Add/Subtract checked pointer - MADDPT and MSUBPT - Multiply Add/Subtract checked pointer These instructions are part of Checked Pointer Arithmetic extension. This patch adds assembler and disassembler support for these instructions with relevant checks. Tests are included as well. A new flag "+cpa" added to documentation. This flag enables CPA extension. Regression tested on the aarch64-none-linux-gnu target and no regressions have been found.
2024-03-18Arm64: check matching operands for predicated B16B16 insnsJan Beulich6-36/+62
Except for bfml{a,s} their 1st and 3rd operands need to match - pass the TIED macro argument accordingly. While doing that also slightly re-arrange table entries, such that all predicated insns are close together. At the same time change the existing test source to actually use non- matching operands for the respective bfml{a,s} forms.
2024-03-18Arm64: correct B16B16 indexed bf{mla,mls,mul}Jan Beulich1-18/+18
Their index is in bits 19, 20, and 22. Bit 11 in particular is already set in the base opcode. Note also how disassembler output didn't match assembler input in the respective testcase.
2024-03-18RISC-V: Tidy smstateen and ssstateen testcases.Nelson Chu4-57/+6
gas/ * testsuite/gas/riscv/march-imply-smstateen.d: Added. * testsuite/gas/riscv/smstateen-csr-s.d: Removed. * testsuite/gas/riscv/ssstateen-csr.d: Likewise. * testsuite/gas/riscv/ssstateen-csr.s: Likewise.
2024-03-15gas/NEWS: Remove mention of AArch64 B16B16 extensionAndrew Carlotti1-3/+0
This aligns the 2.42 NEWS with the update backported to the 2.42 release branch.
2024-03-15x86/APX: legacy promoted insns can't access %xmm16-%xmm31Jan Beulich9-139/+119
Irrespective of the encoding being EVEX, the usable SIMD register range continues to be limited to %xmm0-%xmm15. Enforce this in gas (but continue to generate code, as in principle we know how to encode things) and recognize/flag the case in the disassembler. Oddly enough wrong forms were actually used in the testsuite (register- only forms are then really meaningless to test here, and are hence dropped instead of adjusted). Convert the POP2 test that needs touching anyway (due to a bad ModR/M byte having been chosen) to .insn.
2024-03-13RISC-V: Add -march=help for gasHau Hsu3-0/+126
Use -march=help for gas to print all supported extensions and versions. Here is part of the output of `as -march=help`: All available -march extensions for RISC-V: e 1.9 i 2.1, 2.0 m 2.0 a 2.1, 2.0 f 2.2, 2.0 d 2.2, 2.0 q 2.2, 2.0 c 2.0 v 1.0 h 1.0 zicbom 1.0 zicbop 1.0 ... This patch assumes that the supported extensions with the same versions are listed together. For example: static struct riscv_supported_ext riscv_supported_std_ext[] = { ... {"i", ISA_SPEC_CLASS_20191213, 2, 1, 0 }, {"i", ISA_SPEC_CLASS_20190608, 2, 1, 0 }, {"i", ISA_SPEC_CLASS_2P2, 2, 0, 0 }, ... }; For the "i" extension, 2.1.0 with different spec class are listed together. This patch records the previous printed extension and version. If the current extension and version are the same as the previous one, skip printing. bfd/ * elfxx-riscv.c (riscv_print_extensions): New function. Print available extensions and versions. * elfxx-riscv.h (riscv_print_extensions): New declaration. gas/ * gas/config/tc-riscv.c (md_parse_option): Parse 'help' keyword in -march option to print available extensions and versions. * testsuite/gas/riscv/march-help.l: New testcase for -march=help. * testsuite/gas/riscv/riscv.exp: Updated.
2024-03-12LoongArch: Scan all illegal operand instructions without interruptionLulu Cai8-7/+269
Currently, gas will exit immediately and report an error when it sees illegal operands, and will not process the remaining instructions. Replace as_fatal with as_bad to check for all illegal operands. Add test cases for illegal operands of some instructions.
2024-03-12LoongArch: Fix gas and ld test casesLulu Cai2-0/+6
* After adding the old LE relax, all old LE relocations will have an R_LARCH_RELAX relocation. Fix the gas test case failure caused by the implementation of the old LE relax. * loongarch64-elf does not support pie and -z norelro options, removed in test files.
2024-03-11x86: KeyLocker insn interaction with -msse-check / .sse_checkJan Beulich6-3/+49
Some of these have no explicit %xmm operand(s), yet they still act SSE- like (in leaveing bits 128 and up untouched). Hence they want similarly diagnosing, if that was asked for.
2024-03-11x86/APX: permit wider than 4-bit immediates with V{EXTRACT,INSERT}{F,I}128Jan Beulich1-1/+3
These aren't useful, but can be encoded for their AVX forms and hence should also be permitted for the APX surrogates. Extend the respective conditional by a base opcode check, to restrict it to VROUND{P,S}{S,D}.
2024-03-11x86: don't open-code REG_{SP,FP}Jan Beulich1-2/+2
Since we have the #define-s, we should also use them.
2024-03-08gas: Fix x86 build with GCC 6.4H.J. Lu1-1/+1
Add "()" to silence GCC 6.4: .../gas/config/tc-i386.c: In function ‘x86_ginsn_lea’: .../gas/config/tc-i386.c:5738:19: error: logical not is only applied to the left hand side of comparison [-Werror=logical-not-parentheses] if (!i.base_reg != (!i.index_reg || i.index_reg->reg_num == RegIZ)) ^~ cc1: all warnings being treated as errors PR gas/31464 * config/tc-i386.c (x86_ginsn_lea): Add "()" to silence GCC 6.4.
2024-03-08RISC-V: Support Zabha extension.Jiawei3-0/+235
The Zabha extension[1] supports for byte and halfword atomic memory operations. This patch add all instructions include in Zabha. Further work is waiting Zacas[2] merge. [1] https://github.com/riscv/riscv-zabha/tags [2] https://sourceware.org/pipermail/binutils/2023-May/127700.html Version log: Add new imply relation that Zabha extension implies A extension. bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): New imply. (riscv_multi_subset_supports): New extension. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * testsuite/gas/riscv/zabha-32.d: New test. * testsuite/gas/riscv/zabha.d: New test. * testsuite/gas/riscv/zabha.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_AMOADD_B): New opcodes. (MASK_AMOADD_B): Ditto. (MATCH_AMOXOR_B): Ditto. (MASK_AMOXOR_B): Ditto. (MATCH_AMOOR_B): Ditto. (MASK_AMOOR_B): Ditto. (MATCH_AMOAND_B): Ditto. (MASK_AMOAND_B): Ditto. (MATCH_AMOMIN_B): Ditto. (MASK_AMOMIN_B): Ditto. (MATCH_AMOMAX_B): Ditto. (MASK_AMOMAX_B): Ditto. (MATCH_AMOMINU_B): Ditto. (MASK_AMOMINU_B): Ditto. (MATCH_AMOMAXU_B): Ditto. (MASK_AMOMAXU_B): Ditto. (MATCH_AMOSWAP_B): Ditto. (MASK_AMOSWAP_B): Ditto. (MATCH_AMOADD_H): Ditto. (MASK_AMOADD_H): Ditto. (MATCH_AMOXOR_H): Ditto. (MASK_AMOXOR_H): Ditto. (MATCH_AMOOR_H): Ditto. (MASK_AMOOR_H): Ditto. (MATCH_AMOAND_H): Ditto. (MASK_AMOAND_H): Ditto. (MATCH_AMOMIN_H): Ditto. (MASK_AMOMIN_H): Ditto. (MATCH_AMOMAX_H): Ditto. (MASK_AMOMAX_H): Ditto. (MATCH_AMOMINU_H): Ditto. (MASK_AMOMINU_H): Ditto. (MATCH_AMOMAXU_H): Ditto. (MASK_AMOMAXU_H): Ditto. (MATCH_AMOSWAP_H): Ditto. (MASK_AMOSWAP_H): Ditto. (DECLARE_INSN): New declare. * opcode/riscv.h (enum riscv_insn_class): New class. opcodes/ChangeLog: * riscv-opc.c: New instructions.
2024-03-06LoongArch: Fix some test cases for TLS transition and relaxLulu Cai10-46/+41
2024-03-06LoongArch: Delete extra instructions when TLS type transitionLulu Cai1-5/+26
This modification mainly changes the timing of type transition, adds relaxation to the old LE instruction sequence, and fixes bugs in extreme code models. We strictly distinguish between type transition and relaxation. Type transition is from one type to another, while relaxation is the removal of instructions under the same TLS type. Detailed instructions are as follows: 1. For type transition, only the normal code model of DESC/IE does type transition, and each relocation is accompanied by a RELAX relocation. Neither abs nor extreme will do type transition, and no RELAX relocation will be generated. The extra instructions when DESC transitions to other TLS types will be deleted during the type transition. 2. Implemented relaxation for the old LE instruction sequence. The first two instructions of LE's 32-bit and 64-bit models use the same relocations and cannot be distinguished based on relocations. Therefore, for LE's instruction sequence, any code model will try to relax. 3. Some function names have been adjusted to facilitate understanding, parameters have been adjusted, and unused macros have been deleted.
2024-03-05LoongArch: Add gas testsuit for LA32 relocationsLulu Cai2-0/+136
Test the relocation of the LA32 instruction set.
2024-03-05LoongArch: Add gas testsuit for LA64 relocationsLulu Cai2-0/+253
Test the relocation of the LA64 instruction set.
2024-03-05LoongArch: Add gas testsuit for LA32 int/float instructionsLulu Cai4-0/+609
Test the int/float instructions of LA32.
2024-03-05LoongArch: Add gas testsuit for LA64 int/float instructionsLulu Cai4-0/+1192
Test the int/float instructions of LA64.
2024-03-05LoongArch: Add gas testsuit for lsx/lasx instructionsLulu Cai4-0/+2938
Test the LSX/LASX instructions. Only LA64 supports these instructions.
2024-03-05LoongArch: Add gas testsuit for lbt/lvz instructionsLulu Cai4-0/+382
Test the LBT/LVZ instructions. Only LA64 supports these instructions.
2024-03-05LoongArch: Add gas testsuit for alias instructionsLulu Cai4-0/+60
Test the alias instructions.
2024-03-01s390: Be more verbose about missing operand typeJens Remus3-18/+54
Provide expected operand type in s390-specific assembler operand parsing error message: "error: operand <operand-number>: missing <operand-type> operand" With <operand-type> being one of: - base register - displacement - [vector] index register - length - access register - control register - floating-point register - general-purpose register - vector register - [un]signed number gas/ * config/tc-s390.c: Provide missing operand type in error message. * testsuite/gas/s390/zarch-base-index-0-err.l: Update test case result validation patterns to operand number in operand syntax error messages. * testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Provide operand number in assembler warning and error messagesJens Remus6-165/+206
Prepend the operand number "operand %d:" to the s390-specific assembler operand parsing warning and error messages. While at it reword the custom operand out of range error message text to be closer to the one used by as_bad_value_out_of_range(). Additionally reword the invalid FPR pair warning message to make it nicer. gas/ * config/tc-s390.c: Print operand number in error messages. * testsuite/gas/s390/zarch-base-index-0-err.l: Update test case verification patterns to accept syntax error messages now containing the operand number. * testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise. * testsuite/gas/s390/zarch-warn-areg-zero.l: Likewise. * testsuite/gas/s390/zarch-z9-109-err.l: Likewise. * testsuite/gas/s390/zarch-z900-err.l: Likewise. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Allow to explicitly omit base register operand in assemblyJens Remus10-165/+120
The base register operand B may be omitted in D(B) by coding D and in D(L,B) by coding D(L). The index register operand X may be omitted in D(X,B) by coding D(B) or explicitly omitted by coding D(,B). In both cases the omitted base register operand value defaults to zero. Allow to explicitly omit the base register operand B in D(X,B) and D(L,B) by coding D(X,) and D(L,). Default the omitted base register operand value to zero. gas/ * config/tc-s390.c: Allow to explicitly omit the base register operand in assembly. * NEWS: Mention that the base register now may be omitted on s390. * gas/testsuite/gas/s390/zarch-base-index-0.s: Update test cases for change to allow to explicitly omit the base register operand in assembly. * gas/testsuite/gas/s390/zarch-base-index-0.d: Likewise. * gas/testsuite/gas/s390/zarch-base-index-0-err.s: Likewise. * gas/testsuite/gas/s390/zarch-base-index-0-err.l: Likewise. * gas/testsuite/gas/s390/zarch-omitted-base-index.s: Likewise. * gas/testsuite/gas/s390/zarch-omitted-base-index.d: Likewise. * gas/testsuite/gas/s390/zarch-omitted-base-index-err.s: Likewise. * gas/testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Print base register 0 as "0" in disassemblyJens Remus2-35/+35
Base and index register 0 have no effect in address computation: "A value of zero in the B [base] or X [index] field specifies that no base or index is to be applied, and, thus, general register 0 cannot be designated as containing a base address or index." IBM z/Architecture Principles of Operation [1], chapter "Organization", section "General Registers". Index register 0 is omitted in the s390 disassembly. Base register 0 is omitted in D(B), D(L,B) and D(X,B) - the latter only if the index register is zero. To make it more apparent print base register 0 as "0" instead of "%r0", whenever it would still be printed in the disassembly. [1]: IBM z/Architecture Principles of Operation, SA22-7832-13, https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf opcodes/ * s390-dis.c: Print base register 0 as "0" in disassembly. binutils/ * NEWS: Mention base register 0 now being printed as "0" in s390 disassembly. gas/ * testsuite/gas/s390/zarch-base-index-0.d: Update test case output verification patterns to accept "0" as base base register due to disassembler output format change. * gas/testsuite/gas/s390/zarch-omitted-base-index.d: Likewise. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Warn when register name type does not match operandJens Remus12-22/+204
Print a warning message when the register type of a specified register name does not match with the operand's register type: operand {#}: expected {access|control|floating-point|general|vector} register name [as {base|index} register] Introduce a s390-specific assembler option "warn-regtype-mismatch" with the values "strict", "relaxed", and "no" as well as an option "no-warn-regtype-mismatch" which control whether the assembler performs register name type checks and generates above warning messages. warn-regtype-mismatch=strict: Perform strict register name type checks. warn-regtype-mismatch=relaxed: Perform relaxed register name type checks, which allow floating-point register (FPR) names %f0 to %f15 to be specified as argument to vector register (VR) operands and vector register (VR) names %v0 to %v15 to be specified as argument to floating-point register (FPR) operands. This is acceptable as the FPRs are embedded into the lower halves of the VRs. Make "relaxed" the default, as GCC generates assembler code using FPR and VR interchangeably, which would cause assembler warnings to be generated with "strict". warn-regtype-mismatch=no: no-warn-regtype-mismatch: Disable any register name type checks. Tag .insn pseudo mnemonics as such, to skip register name type checks on those. They need to be skipped, as there do not exist .insn pseudo mnemonics for every possible operand register type combination. Keep track of the currently parsed operand number to provide it as reference in warning messages. To verify that the introduction of this change does not unnecessarily affect the compilation of existing code the GNU Binutils, GNU C Library, and Linux Kernel have been build with the new assembler, verifying that the assembler did not generate any of the new warning messages. gas/ * config/tc-s390.c: Handle new assembler options "[no]warn-regtype-mismatch[=strict|relaxed|no". Annotate parsed register expressions with register type. Keep track of operand number being parsed. Print warning message in case of register type mismatch between instruction operand and parsed register expression. * doc/as.texi: Document new s390-specific assembler options "[no-]warn-regtype-mismatch[=strict|relaxed|no]". * NEWS: Mention new s390-specific register name type checks and related assembler option "warn-regtype-mismatch=strict| relaxed|no". * testsuite/gas/s390/s390.exp: Add test cases for new assembler option "warn-regtype-mismatch={strict|relaxed}". * testsuite/gas/s390/esa-g5.s: Fix register types in tests for didbr, diebr, tbdr, and tbedr. * testsuite/gas/s390/zarch-z13.s: Fix register types in tests for vgef, vgeg, vscef, and vsceg. * testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.s: Tests for assembler option "warn-regtype-mismatch=strict". * testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.l: Likewise. * gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.s: Tests for assembler option "warn-regtype-mismatch=relaxed". * gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.l: Likewise. * gas/testsuite/gas/s390/zarch-omitted-base-index-err.s: Update test cases for assembler option "warn-regtype-mismatch" defaulting to "relaxed". * testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise. include/ * opcode/s390.h (S390_INSTR_FLAG_PSEUDO_MNEMONIC): Add instruction flag to tag .insn pseudo-mnemonics. opcodes/ * s390-opc.c (s390_opformats): Tag .insn pseudo-mnemonics as such. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Revise s390-specific assembler option descriptionsJens Remus1-10/+18
Reorder, reword, and complete the s390-specific option descriptions. Align the formatting of s390-specific assembler options to that of the general assembler options in "as --help". While at it change a warning message to use the term "z/Architecture" instead of the deprecated "esame" (ESA Modal Extensions or ESAME) one. gas/ * config/tc-s390.c: Revise s390-specific assembler option descriptions. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Add test case for disassembler option warn-areg-zeroJens Remus3-0/+182
gas/ * testsuite/gas/s390/s390.exp: Add test cases for s390-specific assembler option "warn-areg-zero". * testsuite/gas/s390/zarch-warn-areg-zero.s: Likewise. * testsuite/gas/s390/zarch-warn-areg-zero.l: Likewise. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Add test cases for base/index register 0Jens Remus5-0/+394
While at it add comments to logic to omit base and/or index register 0 in s390 disassembly. opcodes/ * s390-dis.c: Add comments related to omitting base and/or index register 0 in disassembly. gas/ * testsuite/gas/s390/s390.exp: Add test cases for base and/or index register 0. * testsuite/gas/s390/zarch-base-index-0.s: Add test cases for base and/or index register 0. * testsuite/gas/s390/zarch-base-index-0.d: Likewise. * testsuite/gas/s390/zarch-base-index-0-err.s: Add error test cases for base and/or index register 0. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
generated by cgit v1.1 at 2024-07-17 22:09:16 +0000