riscv-gnu-toolchain/gdb.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-12-14	RISC-V: Fix the wrong encoding and operand of the XTheadFmv extension.	Jin Ma	2	-3/+3
2023-12-13	Make const_1_mode print $1 in AT&T syntax	Cui, Lili	13	-128/+128
2023-12-13	Clean base_reg and assign correct values to regs for input_output_operand (%dx).	Cui, Lili	1	-0/+2
2023-12-12	Fix whitespace snafu in tc-riscv.c	Nick Clifton	1	-5/+5
2023-12-12	RISC-V: Emit R_RISCV_RELAX for the la/lga pseudo instruction	Rui Ueyama	3	-0/+26
2023-12-12	RISC-V: Resolve PCREL_HI20/LO12_I/S fixups with local symbols while `-mno-relax'	Lifang Xia	5	-0/+187
2023-12-11	LoongArch: Add support for <b ".L1"> and <beq, $t0, $t1, ".L1">	mengqinggang	2	-0/+15
2023-12-11	RISC-V/gas: Clarify the definition of `relaxable' in md_apply_fix	Nelson Chu	1	-1/+1
2023-12-01	gas: drop unused fields from struct segment_info_struct	Jan Beulich	2	-12/+1
2023-12-01	x86: adjust NOP generation after potential non-insn	Jan Beulich	2	-1/+13
2023-12-01	x86: i386_cons_align() badly affects diagnostics	Jan Beulich	3	-20/+3
2023-12-01	gas: no md_cons_align() for .nop{,s}	Jan Beulich	4	-9/+17
2023-12-01	x86: suppress optimization after potential non-insn	Jan Beulich	1	-0/+5
2023-12-01	x86: last-insn recording should be per-section	Jan Beulich	6	-58/+116
2023-12-01	x86: allow 32-bit reg to be used with U{RD,WR}MSR	Jan Beulich	1	-4/+4
2023-12-01	RISC-V: Update gas/NEWS for RISC-V vendor extension news.	Nelson Chu	1	-1/+3
2023-12-01	RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0	Nelson Chu	5	-0/+147
2023-12-01	RISC-V: Zv*: Add support for Zvkb ISA extension	Christoph Müllner	6	-58/+48
2023-11-30	MIPS/GAS: Add -march=loongson2f to loongson-2f-3 test	YunQiang Su	1	-1/+1
2023-11-30	MIPS: Set r6 as default arch if vendor is img	YunQiang Su	4	-2/+14
2023-11-30	gas: support double-slash line comments in BPF assembly	Jose E. Marchesi	9	-2/+57
2023-11-28	gas: add NEWS entry for change of comment syntax in BPF assembler	Jose E. Marchesi	2	-0/+9
2023-11-28	gas: change meaning of ; in the BPF assembler	Jose E. Marchesi	12	-35/+57
2023-11-28	testsuite: Clean up .allow_index_reg in i386 tests	Haochen Jiang	234	-574/+350
2023-11-28	testsuite: Clean up #as in dump file for i386 tests	Haochen Jiang	262	-262/+0
2023-11-27	as: Add new estimated reciprocal instructions in LoongArch v1.1	Jiajie Chen	4	-0/+24
2023-11-27	as: Add new atomic instructions in LoongArch v1.1	Jiajie Chen	3	-2/+88
2023-11-24	x86: shrink opcode sets table	Jan Beulich	2	-130/+130
2023-11-24	x86: also prefer VEX encoding over EVEX one for VCVTNEPS2BF16 when possible	Jan Beulich	3	-13/+62
2023-11-24	RISC-V: reduce redundancy in sign/zero extension macro insn handling	Jan Beulich	1	-16/+5
2023-11-24	RISC-V: disallow x0 with certain macro-insns	Jan Beulich	2	-3/+6
2023-11-23	s390: Add missing extended mnemonics	Jens Remus	13	-7/+68
2023-11-23	s390: Align optional operand definition to specs	Jens Remus	6	-10/+27
2023-11-23	s390: Add brasl edge test cases from ESA to z/Architecture	Jens Remus	2	-0/+12
2023-11-23	s390: Position independent verification of relative addressing	Jens Remus	6	-237/+237
2023-11-23	MIPS/GAS: Use addiu instead of addi in test elf-rel.	YunQiang Su	4	-30/+36
2023-11-23	MIPS/GAS: Fix test failures due to jr encoding changes on r6	YunQiang Su	6	-5/+14
2023-11-23	RISC-V: Add vector permutation instructions for T-Head VECTOR vendor extension	Jin Ma	2	-0/+68
2023-11-23	RISC-V: Add vector mask instructions for T-Head VECTOR vendor extension	Jin Ma	2	-0/+56
2023-11-23	RISC-V: Add reductions instructions for T-Head VECTOR vendor extension	Jin Ma	2	-0/+68
2023-11-23	RISC-V: Add floating-point arithmetic instructions for T-Head VECTOR vendor e...	Jin Ma	2	-0/+358
2023-11-23	RISC-V: Add fixed-point arithmetic instructions for T-Head VECTOR vendor exte...	Jin Ma	2	-0/+178
2023-11-23	RISC-V: Add integer arithmetic instructions for T-Head VECTOR vendor extension	Jin Ma	2	-0/+657
2023-11-23	RISC-V: Add sub-extension XTheadZvamo for T-Head VECTOR vendor extension	Jin Ma	3	-0/+161
2023-11-23	RISC-V: Add load/store segment instructions for T-Head VECTOR vendor extension	Jin Ma	2	-0/+1708
2023-11-23	RISC-V: Add load/store instructions for T-Head VECTOR vendor extension	Jin Ma	2	-0/+268
2023-11-23	RISC-V: Add configuration-setting instructions for T-Head VECTOR vendor exten...	Jin Ma	2	-0/+15
2023-11-23	RISC-V: Add CSRs for T-Head VECTOR vendor extension	Jin Ma	5	-0/+57
2023-11-23	RISC-V: Add T-Head VECTOR vendor extension.	Jin Ma	5	-0/+13
2023-11-22	LoongArch: fix internal error when as handling unsupported modifier.	Lulu Cai	4	-1/+13