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authorJin Ma <jinma@linux.alibaba.com>2023-11-18 15:08:12 +0800
committerNelson Chu <nelson@rivosinc.com>2023-11-23 09:32:07 +0800
commitb4cf88da83fbbceecdec7ad4e1addddfe2c2b76d (patch)
tree210753dcf6ad30e3fde5a5930f71cc9efaca11cc /gas
parent1ba39b6fe595d05bbfdf7abebaea2883ddb9d717 (diff)
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RISC-V: Add reductions instructions for T-Head VECTOR vendor extension
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds reductions instructions for the "XTheadVector" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: Add tests for reductions instructions. * testsuite/gas/riscv/x-thead-vector.s: Likewise. opcodes/ChangeLog: * riscv-opc.c: Likewise.
Diffstat (limited to 'gas')
-rw-r--r--gas/testsuite/gas/riscv/x-thead-vector.d32
-rw-r--r--gas/testsuite/gas/riscv/x-thead-vector.s36
2 files changed, 68 insertions, 0 deletions
diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d
index 178e246..2c80eeb 100644
--- a/gas/testsuite/gas/riscv/x-thead-vector.d
+++ b/gas/testsuite/gas/riscv/x-thead-vector.d
@@ -1560,3 +1560,35 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+88891257[ ]+th.vfncvt.f.xu.v[ ]+v4,v8,v0.t
[ ]+[0-9a-f]+:[ ]+88899257[ ]+th.vfncvt.f.x.v[ ]+v4,v8,v0.t
[ ]+[0-9a-f]+:[ ]+888a1257[ ]+th.vfncvt.f.f.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+02862257[ ]+th.vredsum.vs[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+1a842257[ ]+th.vredmaxu.vs[ ]+v4,v8,v8
+[ ]+[0-9a-f]+:[ ]+1e842257[ ]+th.vredmax.vs[ ]+v4,v8,v8
+[ ]+[0-9a-f]+:[ ]+12842257[ ]+th.vredminu.vs[ ]+v4,v8,v8
+[ ]+[0-9a-f]+:[ ]+16842257[ ]+th.vredmin.vs[ ]+v4,v8,v8
+[ ]+[0-9a-f]+:[ ]+06862257[ ]+th.vredand.vs[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+0a862257[ ]+th.vredor.vs[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+0e862257[ ]+th.vredxor.vs[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+00862257[ ]+th.vredsum.vs[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+18842257[ ]+th.vredmaxu.vs[ ]+v4,v8,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+1c842257[ ]+th.vredmax.vs[ ]+v4,v8,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+10842257[ ]+th.vredminu.vs[ ]+v4,v8,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+14842257[ ]+th.vredmin.vs[ ]+v4,v8,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+04862257[ ]+th.vredand.vs[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+08862257[ ]+th.vredor.vs[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+0c862257[ ]+th.vredxor.vs[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+c2860257[ ]+th.vwredsumu.vs[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+c6860257[ ]+th.vwredsum.vs[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+c0860257[ ]+th.vwredsumu.vs[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+c4860257[ ]+th.vwredsum.vs[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+0e861257[ ]+th.vfredosum.vs[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+06861257[ ]+th.vfredsum.vs[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+1e861257[ ]+th.vfredmax.vs[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+16861257[ ]+th.vfredmin.vs[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+0c861257[ ]+th.vfredosum.vs[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+04861257[ ]+th.vfredsum.vs[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+1c861257[ ]+th.vfredmax.vs[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+14861257[ ]+th.vfredmin.vs[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+ce861257[ ]+th.vfwredosum.vs[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+c6861257[ ]+th.vfwredsum.vs[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+cc861257[ ]+th.vfwredosum.vs[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+c4861257[ ]+th.vfwredsum.vs[ ]+v4,v8,v12,v0.t
diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s
index 92e9006..71f83a2 100644
--- a/gas/testsuite/gas/riscv/x-thead-vector.s
+++ b/gas/testsuite/gas/riscv/x-thead-vector.s
@@ -1620,3 +1620,39 @@
th.vfncvt.f.xu.v v4, v8, v0.t
th.vfncvt.f.x.v v4, v8, v0.t
th.vfncvt.f.f.v v4, v8, v0.t
+
+ th.vredsum.vs v4, v8, v12
+ th.vredmaxu.vs v4, v8, v8
+ th.vredmax.vs v4, v8, v8
+ th.vredminu.vs v4, v8, v8
+ th.vredmin.vs v4, v8, v8
+ th.vredand.vs v4, v8, v12
+ th.vredor.vs v4, v8, v12
+ th.vredxor.vs v4, v8, v12
+ th.vredsum.vs v4, v8, v12, v0.t
+ th.vredmaxu.vs v4, v8, v8, v0.t
+ th.vredmax.vs v4, v8, v8, v0.t
+ th.vredminu.vs v4, v8, v8, v0.t
+ th.vredmin.vs v4, v8, v8, v0.t
+ th.vredand.vs v4, v8, v12, v0.t
+ th.vredor.vs v4, v8, v12, v0.t
+ th.vredxor.vs v4, v8, v12, v0.t
+
+ th.vwredsumu.vs v4, v8, v12
+ th.vwredsum.vs v4, v8, v12
+ th.vwredsumu.vs v4, v8, v12, v0.t
+ th.vwredsum.vs v4, v8, v12, v0.t
+
+ th.vfredosum.vs v4, v8, v12
+ th.vfredsum.vs v4, v8, v12
+ th.vfredmax.vs v4, v8, v12
+ th.vfredmin.vs v4, v8, v12
+ th.vfredosum.vs v4, v8, v12, v0.t
+ th.vfredsum.vs v4, v8, v12, v0.t
+ th.vfredmax.vs v4, v8, v12, v0.t
+ th.vfredmin.vs v4, v8, v12, v0.t
+
+ th.vfwredosum.vs v4, v8, v12
+ th.vfwredsum.vs v4, v8, v12
+ th.vfwredosum.vs v4, v8, v12, v0.t
+ th.vfwredsum.vs v4, v8, v12, v0.t