Age | Commit message (Collapse) | Author | Files | Lines |
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gas/
2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/all/gas.exp: Don't xfail on ARC.
* testsuite/gas/elf/elf.exp: Likewise.
* testsuite/gas/all/redef3.d: Allow execution for ARC.
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gas/
2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/warn.exp: Fix matching pattern.
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gas/
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/ext2op.d: New file.
* testsuite/gas/arc/ext2op.s: Likewise.
* testsuite/gas/arc/ext3op.d: Likewise.
* testsuite/gas/arc/ext3op.s: Likewise.
opcodes/
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
* arc-tbl.h (invld07): Remove.
* arc-ext-tbl.h: New file.
* arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
* arc-opc.c (arc_opcodes): Add ext-tbl include.
include/
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (insn_subclass_t): Add QUARKSE subclass.
(FIELDA, FIELDB, FIELDC, FIELDF, FIELDQ, INSN3OP, INSN2OP)
(INSN2OP, INSN3OP_ABC, INSN3OP_ALC, INSN3OP_ABL, INSN3OP_ALL)
(INSN3OP_0BC, INSN3OP_0LC, INSN3OP_0BL, INSN3OP_0LL, INSN3OP_ABU)
(INSN3OP_ALU, INSN3OP_0BU, INSN3OP_0LU, INSN3OP_BBS, INSN3OP_0LS)
(INSN3OP_CBBC, INSN3OP_CBBL, INSN3OP_C0LC, INSN3OP_C0LL)
(INSN3OP_CBBU, INSN3OP_C0LU, MINSN3OP_ABC, MINSN3OP_ALC)
(MINSN3OP_ABL, MINSN3OP_ALL, MINSN3OP_0BC, MINSN3OP_0LC)
(MINSN3OP_0BL, MINSN3OP_0LL, MINSN3OP_ABU, MINSN3OP_ALU)
(MINSN3OP_0BU, MINSN3OP_0LU, MINSN3OP_BBS, MINSN3OP_0LS)
(MINSN3OP_CBBC, MINSN3OP_CBBL, MINSN3OP_C0LC, MINSN3OP_C0LL)
(MINSN3OP_CBBU, MINSN3OP_C0LU, INSN2OP_BC, INSN2OP_BL, INSN2OP_0C)
(INSN2OP_0L INSN2OP_BU, INSN2OP_0U, MINSN2OP_BC, MINSN2OP_BL)
(MINSN2OP_0C, MINSN2OP_0L, MINSN2OP_BU, MINSN2OP_0U): Define.
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Adds the first few nps400 instructions.
gas/ChangeLog:
* testsuite/gas/arc/nps400-0.d: New file.
* testsuite/gas/arc/nps400-0.s: New file.
* testsuite/gas/arc/nps400-1.d: New file.
* testsuite/gas/arc/nps400-1.s: New file.
include/ChangeLog:
* opcodes/arc.h (insn_class_t): Add BITOP type.
opcodes/ChangeLog:
* arc-nps400-tbl.h: New file.
* arc-opc.c: Add top level comment.
(insert_nps_3bit_dst): New function.
(extract_nps_3bit_dst): New function.
(insert_nps_3bit_src2): New function.
(extract_nps_3bit_src2): New function.
(insert_nps_bitop_size): New function.
(extract_nps_bitop_size): New function.
(arc_flag_operands): Add nps400 entries.
(arc_flag_classes): Add nps400 entries.
(arc_operands): Add nps400 entries.
(arc_opcodes): Add nps400 include.
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When parsing the operand instruction flags we don't currently detect the
case where multiple flags are provided from the same class set, these
will be accepted and the bit values merged together, resulting in the
wrong instruction being assembled. For example:
adc.n.eq r0,r0,r2
Will assemble without error, yet, upon disassembly, the instruction will
actually be:
adc.c r0,r0,r2
In a later commit the concept of required flags will be introduced.
Required flags are just like normal instruction flags, except that they
must be present for the instruction to match. Adding this will allow
for simpler instructions in the instruction table, and allow for more
sharing of operand extraction and insertion functions.
To solve both of the above issues (multiple flags being invalid, and
required flags), this commit reworks the flag class mechanism.
Currently the flag class is never used. Each instruction can reference
multiple flag classes, each flag class has a class type and a set of
flags. However, at present, the class type is never used. The current
values identify the type of instruction that the flag will be used in,
but this is not required information.
Instead, this commit discards the old flag classes, and introduces 3 new
classes. The first F_CLASS_NONE, is just a NULL marker value, and is
only used in the NULL marker flag class. The other two flag classes are
F_FLAG_OPTIONAL, and F_FLAG_REQUIRED.
The class F_FLAG_OPTIONAL has the property that at most one of the flags
in the flag set for that class must be present in the instruction. The
"at most" one means that no flags being present is fine.
The class F_FLAG_REQUIRED is not currently used, but will be soon. With
this class, exactly one of the flags from this class must be present in
the instruction. If the flag class contains a single flag, then of
course that flag must be present. However, if the flag class contained
two or more, then one, and only one of them must be present.
gas/ChangeLog:
* config/tc-arc.c (find_opcode_match): Move lnflg, and i
declarations to start of block. Reset code on all flags before
attempting to match them. Handle multiple hits on the same flag.
Handle flag class.
* testsuite/gas/arc/asm-errors.d: New file.
* testsuite/gas/arc/asm-errors.err: New file.
* testsuite/gas/arc/asm-errors.s: New file.
include/ChangeLog:
* opcode/arc.h (flag_class_t): Remove all old flag classes, add 3
new classes instead.
opcodes/ChangeLog:
* arc-opc.c (arc_flag_classes): Convert all flag classes to use
the new class enum values.
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The inline-data test checks the specific bytes laid down by the
assembler, and so relies on the endianness of the target. I could
change the expected results to be endian agnostic, however, I worried
that a bug in the assembler that gets the endianness wrong would then
slip through. Instead I add a new test for big-endian arc, and restrict
the existing test to little-endian arc.
gas/ChangeLog:
* testsuite/gas/arc/inline-data-1.d: Add target restriction.
* testsuite/gas/arc/inline-data-2.d: New file.
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PR target/19721
opcodes * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
of MOV insn that aliases an ORR insn.
gas * testsuite/gas/aarch64/pr19721.s: New test source file.
* testsuite/gas/aarch64/pr19721.d: New test driver file.
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move entries to main ChangeLog
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gas/
* config/tc-arm.c (N_S_32): New.
(N_F_16_32): Likewise.
(N_SUF_32): Support N_F16.
(N_IF_32): Likewise.
(neon_dyadic_misc): Likewise.
(do_neon_cmp): Likewise.
(do_neon_cmp_inv): Likewise.
(do_neon_mul): Likewise.
(do_neon_fcmp_absolute): Likewise.
(do_neon_step): Likewise.
(do_neon_abs_neg): Likewise.
(CVT_FLAVOR_VAR): Likewise.
(do_neon_cvt_1): Likewise.
(do_neon_recip_est): Likewise.
(do_vmaxnm): Likewise.
(do_vrint_1): Likewise.
(neon_check_type): Check architecture support for FP16 extension.
(insns): Update comments.
* testsuite/gas/arm/armv8-2-fp16-simd.s: New test source.
* testsuite/gas/arm/armv8-2-fp16-simd.d: New testcase for arm mode.
* testsuite/gas/arm/armv8-2-fp16-simd-thumb.d: Likewise for thumb mode.
* testsuite/gas/arm/armv8-2-fp16-simd-warning.d: New rejection test for
arm mode.
* testsuite/gas/arm/armv8-2-fp16-simd-warning-thumb.d: Likewise for
thumb mode.
* testsuite/gas/arm/armv8-2-fp16-simd-warning.l: New expected rejection
error file.
opcode/
* arm-dis.c (neon_opcodes): Support new FP16 instructions.
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* read.c (emit_expr_with_reloc): Add code check a bignum with
nbytes == 1.
* config/rx/rx-parse.y (rx_intop): Accept bignum values for sizes
other than 32-bits.
* testsuite/gas/elf/bignum.s: New test source file.
* testsuite/gas/elf/bignum.d: New test driver file.
* testsuite/gas/elf/elf.exp: Run the new test.
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gas/
* config/tc-arm.c (do_arit): Protect against bad relocations usage.
(do_mov): Likewise.
(do_t_add_sub): Allow pcrop relocations for Thumb-2 targets.
(do_t_mov_cmp): Likewise.
(do_t_add_sub): Protect against bad relocations usage.
(do_t_mov_cmp): Likewise.
gas/testsuite/
* gas/arm/adds-thumb1-reloc-local-armv7-m.s: New.
* gas/arm/adds-thumb1-reloc-local-armv7-m.d: New.
* gas/arm/movs-thumb1-reloc-local-armv7-m.s: New.
* gas/arm/movs-thumb1-reloc-local-armv7-m.d: New.
ld/
* testsuite/ld-arm/arm-elf.exp: New tests.
* testsuite/ld-arm/thumb1-adds-armv7-m.s: New.
* testsuite/ld-arm/thumb1-movs-armv7-m.s: New.
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bfd/
2016-03-08 Cupertino Miranda <Cupertino.Miranda@synopsys.com>
Andrew Burgess <andrew.burgess@embecosm.com>
* elf32-arc.c (arc_bfd_get_32): Becomes an alias for bfd_get_32.
(arc_bfd_put_32): Becomes an alias for bfd_put_32.
(arc_elf_howto_init): Added assert to validate relocations.
(get_middle_endian_relocation): Delete.
(middle_endian_convert): New function.
(ME): Redefine, now does nothing.
(IS_ME): New define.
(arc_do_relocation): Extend the attached 'ARC_RELOC_HOWTO'
definition to call middle_endian_convert. Add a new local
variable and make use of this throughout. Added call to
arc_bfd_get_8 and arc_bfd_put_8 for 8 bit relocations.
gas/
2016-03-08 Andrew Burgess <andrew.burgess@embecosm.com>
* testsuite/gas/arc/inline-data-1.d: New file.
* testsuite/gas/arc/inline-data-1.s: New file.
include/
2016-03-08 Cupertino Miranda <Cupertino.Miranda@synopsys.com>
Andrew Burgess <andrew.burgess@embecosm.com>
* elf/arc-reloc.def: Add a call to ME within the formula for each
relocation that requires middle-endian correction.
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binutils/
2016-03-04 Matthew Wahab <matthew.wahab@arm.com>
* readelf.c (arm_attry_tag_FP_arch): Add "NEON for ARMv8.1".
gas/
2016-03-04 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-arm.c (aeabi_set_public_attributes): Emit attribute
for ARMv8.1 AdvSIMD use.
* testsuite/gas/arm/attr-march-armv8-a+rdma.d: New.
* testsuite/gas/arm/attr-march-armv8_1-a+simd.d: New.
Change-Id: I3c356e0681b97df2f9c0dabd7c0fd1b441cc2755
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gas/
2016-03-04 Matthew Wahab <matthew.wahab@arm.com>
* config/gas/tc-arm.c (fpu_neon_ext_v8_1): Restrict to the ARMv8.1 RDMA
feature.
(record_feature_use): New.
(mark_feature_used): Use record_feature_use.
(do_neon_qrdmlah): New.
(insns): Use do_neon_qrdmlah for vqrdmlah and vqrdmlsh and
variants.
(arm_extensions): Put into alphabetical order. Re-indent "simd"
and "rdma" entries. Fix the incorrect merge value for "+rdma".
* testsuite/gas/arm/armv8-a+rdma-warning.d: New.
* testsuite/gas/arm/armv8-a+rdma.d: Add assembler command line options.
Make source file explicit.
* testsuite/gas/arm/armv8-a+rdma.l: New.
* testsuite/gas/arm/armv8-a+rdma.s: Remove .arch and .arch_extension
directives. Fix white-space.
* testsuite/gas/arm/armv8_1-a+simd.d: New.
include/opcode
2016-03-04 Matthew Wahab <matthew.wahab@arm.com>
* arm.h (ARM_ARCH_V8_1A): Add FPU_NEON_EXT_RDMA.
(ARM_CPU_HAS_FEATURE): Add comment.
Change-Id: Ie19250e8fa50aed44e44ab40ff30b04b38bc1a3d
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* testsuite/gas/i386/x86_64-intel.d: Adjusted for COFF.
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bfd/
2016-02-29 Cupertino Miranda <cmiranda@synopsys.com>
* elf32-arc.c (elf_arc_relocate_section): Added rules to fix the
relocation addend when sections get merged.
gas/
2016-02-29 Cupertino Miranda <cmiranda@synopsys.com>
Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com>
* config/tc-arc.c (arc_extra_reloc): Change size to 0.
(tc_arc_fix_adjustable): Changed default return value to 1.
* testsuite/gas/arc/j.d: Updated expected symbol
* testsuite/gas/arc/jl.d: Likewise
* testsuite/gas/arc/relax-avoid1.d: Likewise
* testsuite/gas/arc/st.d: Likewise
ld/
2016-02-29 Cupertino Miranda <cmiranda@synopsys.com>
* testsuite/ld-elf/merge.d: Removed xfail for ARC.
* testsuite/ld-elf/merge2.d: Likewise.
* testsuite/ld-elf/merge3.d: Likewise.
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The BFD configure option, --enable-elf-stt-common, can't be to used to
verify STT_COMMON implementation with the normal binutils build. Instead,
this patch removes it from BFD. It adds --elf-stt-common=[no|yes] to ELF
assembler/objcopy and adds -z common/-z nocommon to ld.
A configure option, --enable-elf-stt-common, is added to gas to specify
whether ELF assembler should generate common symbols with the STT_COMMON
type by default.
Since BSF_KEEP_G is never used, it is renamed to BSF_ELF_COMMON for ELF
common symbols.
bfd/
PR ld/19645
* bfd.c (bfd): Change flags to 20 bits.
(BFD_CONVERT_ELF_COMMON): New.
(BFD_USE_ELF_STT_COMMON): Likewise.
(BFD_FLAGS_SAVED): Add BFD_CONVERT_ELF_COMMON and
BFD_USE_ELF_STT_COMMON.
(BFD_FLAGS_FOR_BFD_USE_MASK): Likewise.
* configure.ac: Remove --enable-elf-stt-common.
* elf.c (swap_out_syms): Choose STT_COMMON or STT_OBJECT for
common symbol depending on BFD_CONVERT_ELF_COMMON and
BFD_USE_ELF_STT_COMMON.
* elfcode.h (elf_slurp_symbol_table): Set BSF_ELF_COMMON for
STT_COMMON.
* elflink.c (bfd_elf_link_mark_dynamic_symbol): Also check
STT_COMMON.
(elf_link_convert_common_type): New function.
(elf_link_output_extsym): Choose STT_COMMON or STT_OBJECT for
common symbol depending on BFD_CONVERT_ELF_COMMON and
BFD_USE_ELF_STT_COMMON. Set sym.st_info after sym.st_shndx.
* elfxx-target.h (TARGET_BIG_SYM): Add BFD_CONVERT_ELF_COMMON
and BFD_USE_ELF_STT_COMMON to object_flags.
(TARGET_LITTLE_SYM): Likewise.
* syms.c (BSF_KEEP_G): Renamed to ...
(BSF_ELF_COMMON): This.
* bfd-in2.h: Regenerated.
* config.in: Likewise.
* configure: Likewise.
binutils/
PR ld/19645
* NEWS: Mention --elf-stt-common= for objcopy.
* doc/binutils.texi: Document --elf-stt-common= for objcopy.
* objcopy.c (do_elf_stt_common): New.
(command_line_switch): Add OPTION_ELF_STT_COMMON.
(copy_options): Add --elf-stt-common=.
(copy_usage): Add --elf-stt-common=.
(copy_object): Also check do_elf_stt_common for ELF targets.
(copy_file): Handle do_elf_stt_common.
(copy_main): Handle OPTION_ELF_STT_COMMON.
* readelf.c (apply_relocations): Support STT_COMMON.
* testsuite/binutils-all/common-1.s: New file.
* testsuite/binutils-all/common-1a.d: Likewise.
* testsuite/binutils-all/common-1b.d: Likewise.
* testsuite/binutils-all/common-1c.d: Likewise.
* testsuite/binutils-all/common-1d.d: Likewise.
* testsuite/binutils-all/common-1e.d: Likewise.
* testsuite/binutils-all/common-1f.d: Likewise.
* testsuite/binutils-all/common-2.s: Likewise.
* testsuite/binutils-all/common-2a.d: Likewise.
* testsuite/binutils-all/common-2b.d: Likewise.
* testsuite/binutils-all/common-2c.d: Likewise.
* testsuite/binutils-all/common-2d.d: Likewise.
* testsuite/binutils-all/common-2e.d: Likewise.
* testsuite/binutils-all/common-2f.d: Likewise.
* testsuite/binutils-all/objcopy.exp
(objcopy_test_elf_common_symbols): New proc.
Run objcopy_test_elf_common_symbols for ELF targets
gas/
PR ld/19645
* NEWS: Mention --enable-elf-stt-common and --elf-stt-common=
for ELF assemblers.
* as.c (flag_use_elf_stt_common): New.
(show_usage): Add --elf-stt-common=.
(option_values): Add OPTION_ELF_STT_COMMON.
(std_longopts): Add --elf-stt-common=.
(parse_args): Handle --elf-stt-common=.
* as.h (flag_use_elf_stt_common): New.
* config.in: Regenerated.
* configure: Likewise.
* configure.ac: Add --enable-elf-stt-common and define
DEFAULT_GENERATE_ELF_STT_COMMON.
* gas/write.c (write_object_file): Set BFD_CONVERT_ELF_COMMON
and BFD_USE_ELF_STT_COMMON if flag_use_elf_stt_common is set.
* doc/as.texinfo: Document --elf-stt-common=.
* testsuite/gas/elf/common3.s: New file.
* testsuite/gas/elf/common3a.d: Likewise.
* testsuite/gas/elf/common3b.d: Likewise.
* testsuite/gas/elf/common4.s: Likewise.
* testsuite/gas/elf/common4a.d: Likewise.
* testsuite/gas/elf/common4b.d: Likewise.
* testsuite/gas/i386/dw2-compress-3b.d: Likewise.
* testsuite/gas/i386/dw2-compressed-3b.d: Likewise.
* testsuite/gas/elf/elf.exp: Run common3a, common3b, common4a
and common4b.
* testsuite/gas/i386/dw2-compress-3.d: Renamed to ...
* testsuite/gas/i386/dw2-compress-3a.d: This. Pass
--elf-stt-common=no to as.
* testsuite/gas/i386/dw2-compressed-3.d: Renamed to ...
* testsuite/gas/i386/dw2-compressed-3a.d: This. Pass
--elf-stt-common=no to as.
* testsuite/gas/i386/i386.exp: Run dw2-compress-3a,
dw2-compress-3b, dw2-compressed-3a and dw2-compressed-3b instead
of dw2-compress-3 and dw2-compressed-3.
include/
PR ld/19645
* bfdlink.h (bfd_link_elf_stt_common): New enum.
(bfd_link_info): Add elf_stt_common.
ld/
PR ld/19645
* NEWS: Mention -z common/-z nocommon for ELF targets.
* emultempl/elf32.em (gld${EMULATION_NAME}_handle_option): Handle
-z common and -z nocommon.
* ld.texinfo: Document -z common/-z nocommon.
* lexsup.c (elf_shlib_list_options): Add -z common/-z nocommon.
* testsuite/ld-elf/tls_common.exp: Test --elf-stt-common=no and
--elf-stt-common=yes with assembler.
* testsuite/ld-elfcomm/common-1.s: New file.
* testsuite/ld-elfcomm/common-1a.d: Likewise.
* testsuite/ld-elfcomm/common-1b.d: Likewise.
* testsuite/ld-elfcomm/common-1c.d: Likewise.
* testsuite/ld-elfcomm/common-1d.d: Likewise.
* testsuite/ld-elfcomm/common-1e.d: Likewise.
* testsuite/ld-elfcomm/common-1f.d: Likewise.
* testsuite/ld-elfcomm/common-2.s: Likewise.
* testsuite/ld-elfcomm/common-2a.d: Likewise.
* testsuite/ld-elfcomm/common-2b.d: Likewise.
* testsuite/ld-elfcomm/common-2c.d: Likewise.
* testsuite/ld-elfcomm/common-2d.d: Likewise.
* testsuite/ld-elfcomm/common-2e.d: Likewise.
* testsuite/ld-elfcomm/common-2f.d: Likewise.
* testsuite/ld-elfcomm/common-3a.rd: Likewise.
* testsuite/ld-elfcomm/common-3b.rd: Likewise.
* testsuite/ld-i386/pr19645.d: Likewise.
* testsuite/ld-i386/pr19645.s: Likewise.
* testsuite/ld-x86-64/largecomm-1.s: Likewise.
* testsuite/ld-x86-64/largecomm-1a.d: Likewise.
* testsuite/ld-x86-64/largecomm-1b.d: Likewise.
* testsuite/ld-x86-64/largecomm-1c.d: Likewise.
* testsuite/ld-x86-64/largecomm-1d.d: Likewise.
* testsuite/ld-x86-64/largecomm-1e.d: Likewise.
* testsuite/ld-x86-64/largecomm-1f.d: Likewise.
* testsuite/ld-x86-64/pr19645.d: Likewise.
* testsuite/ld-x86-64/pr19645.s: Likewise.
* testsuite/ld-elfcomm/elfcomm.exp: Test --elf-stt-common=yes
with assembler.
(assembler_generates_commons): Removed.
Run -z common/-z nocommon tests. Run *.d tests.
* testsuite/ld-i386/i386.exp: Run pr19645.
* testsuite/ld-x86-64/x86-64.exp: Likewise.
* testsuite/ld-x86-64/dwarfreloc.exp: Test --elf-stt-common with
assembler. Test STT_COMMON with readelf.
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Some gas tests are excluded for arc targets using the pattern arc-*-*,
however this only covers little endian arc targets. This commit extends
the patter to cover big endian arc targets, the pattern is now arc*-*-*.
gas/ChangeLog:
* testsuite/gas/all/gas.exp: Change target pattern to cover
arceb-*.
* testsuite/gas/all/redef3.d: Likewise.
* testsuite/gas/elf/elf.exp: Likewise.
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instruction shape.
gas/
2016-02-24 Renlin Li <renlin.li@arm.com>
* config/tc-arm.c (BAD_FP16): New error message macro.
(do_scalar_fp16_v82_encode): Change the coproc field to 9 for armv8.2
fp16 scalar instructions.
(neon_check_type): Allow different size from key.
(do_vfp_nsyn_add_sub): Add support SE_H shape support.
(try_vfp_nsyn): Likewise.
(do_vfp_nsyn_mla_mls): Likewise.
(do_vfp_nsyn_fma_fms): Likewise.
(do_vfp_nsyn_ldm_stm): Likewise
(do_vfp_nsyn_sqrt): Likewise
(do_vfp_nsyn_div): Likewise
(do_vfp_nsyn_nmul): Likewise.
(do_vfp_nsyn_cmp): Likewise.
(do_neon_shll): Likewise.
(do_vfp_nsyn_cvt_fpv8): Likewise.
(do_neon_cvttb_2): Likewise.
(do_neon_mov): Likewise.
(do_neon_rshift_round_imm): Likewise.
(do_neon_ldr_str): Likewise.
(do_vfp_nsyn_fpv8): Likewise.
(do_vmaxnm): Likewise.
(do_vrint_1): Likewise.
(insns): New entry for vins, vmovx.
(md_apply_fix): Left shift 1 bit for fp16 vldr/vstr.
* testsuite/gas/arm/armv8-2-fp16-scalar-thumb.d: New.
* testsuite/gas/arm/armv8-2-fp16-scalar.d: New.
* testsuite/gas/arm/armv8-2-fp16-scalar.s: New.
* testsuite/gas/arm/armv8-2-fp16-scalar-bad.s: New
* testsuite/gas/arm/armv8-2-fp16-scalar-bad.d: New
* testsuite/gas/arm/armv8-2-fp16-scalar-bad.l: New
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opcodes/
2016-02-24 Renlin Li <renlin.li@arm.com>
* arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
(print_insn_coprocessor): Support fp16 instruction.
gas/
2016-02-24 Renlin Li <renlin.li@arm.com>
* testsuite/gas/arm/copro.d: Adjust output.
* testsuite/gas/arm/copro.s: Adjust co-processor num.
|
|
opcodes/
2016-02-24 Renlin Li <renlin.li@arm.com>
* arm-dis.c (coprocessor_opcodes): Fix mask for vsel, vmaxnm, vminnm,
vrint(mpna).
gas/
2016-02-24 Renlin Li <renlin.li@arm.com>
* testsuite/gas/arm/mask_1.d: New.
* testsuite/gas/arm/mask_1.s: New.
|
|
ldc/ldc2, stc/stc2
opcodes/
2016-02-24 Renlin Li <renlin.li@arm.com>
* arm-dis.c (print_insn_coprocessor): Check co-processor number for
cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
gas/
2016-02-24 Renlin Li <renlin.li@arm.com>
* testsuite/gas/arm/copro.s: Use coprocessor other than 10, 11.
* testsuite/gas/arm/copro.d: Update.
|
|
hpux has a non-standard common directive.
* testsuite/gas/elf/elf.exp: Skip tests for common directive on
hpux.
|
|
Increment register number by 16 if RegVRex is set.
* config/tc-i386.c (register_number): Check RegVRex.
* testsuite/gas/i386/x86-64-avx512f.s: Add a test for vgatherqpd
with %zmm19 and %zmm3.
* testsuite/gas/i386/x86-64-avx512f-intel.d: Updated.
* testsuite/gas/i386/x86-64-avx512f.d: Likewise.
|
|
Despite the documentation and the comment in xtensa_move_literals, in
the presence of --text-section-literals and --auto-litpools literals are
moved from the separate literal sections into .init and .fini, because
the check in the xtensa_move_literals is incorrect.
This moving was broken with introduction of auto litpools: some literals
now may be lost. This happens because literal frags emitted from .init
and .fini are not closed when new .literal_position marks new literal
pool. Then frag_align(2, 0, 0) changes type of the last literal frag to
rs_align. rs_align frags are skipped in the xtensa_move_literals. As a
result fixups against such literals are not moved out of .init.literal/
.fini.literal sections producing the following assembler error:
test.S: Warning: fixes not all moved from .init.literal
test.S: Internal error!
Fix check for .init.literal/.fini.literal in the xtensa_move_literals
and don't let it move literals from there in the presence of
--text-section-literals or --auto-litpools.
2016-02-17 Max Filippov <jcmvbkbc@gmail.com>
gas/
* config/tc-xtensa.c (xtensa_move_literals): Fix check for
.init.literal/.fini.literal section name.
* testsuite/gas/xtensa/all.exp: Add init-fini-literals to the
list of xtensa tests.
* testsuite/gas/xtensa/init-fini-literals.d: New file:
init-fini-literals test result patterns.
* testsuite/gas/xtensa/init-fini-literals.s: New file:
init-fini-literals test.
|
|
gas/
2016-02-16 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (tc_arc_frame_initial_instructions): New
function.
(tc_arc_regname_to_dw2regnum): Likewise.
* config/tc-arc.h (TARGET_USE_CFIPOP): Define
(tc_cfi_frame_initial_instructions): Likewise.
(tc_regname_to_dw2regnum): Likewise.
gas/testsuite
2016-02-16 Claudiu Zissulescu <claziss@synopsys.com>
* gas/cfi/cfi-arc-1.d: New file.
* gas/cfi/cfi-arc-1.s: Likewise.
* gas/cfi/cfi.exp: Allow running tests for arc.
binutils/
2016-02-16 Claudiu Zissulescu <claziss@synopsys.com>
* readelf.c (is_32bit_pcrel_reloc): Add R_ARC_32_PCREL.
|
|
In AArch64 gas, register name or string starts with valid register name
is not allowed as symbol name for mov[z,k,n] instruction.
This patch removes the restriction.
gas/
PR gas/19620
* config/tc-aarch64.c (parse_half): Remove restrictions on symbol name.
* testsuite/gas/aarch64/movw_label.d: New.
* testsuite/gas/aarch64/movw_label.s: New.
|
|
PR gas/19665
* config/rx-parse.y (MOV): Opcode generation for index
register addressing mode.
* testsuite/gas/rx/rx.exp: Updated for new testcase.
* testsuite/gas/rx/pr19665.s: New file.
* testsuite/gas/rx/pr19665.s: New file.
* testsuite/gas/rx/mov.d: Update expected output.
|
|
flags and type fields. (ELF only)
gas * doc/as.texinfo (.section): Document that numeric values can now
be used for the flags and type fields of the ELF target's .section
directive. Add notes about the restrictions on setting flags and
types.
* config/obj-elf.c (obj_elf_change_section): Allow known sections
to be given processor specific section types. Allow processor and
application specific flags of a section to be set after
definition.
(obj_elf_parse_section_letters): Handle parsing numeric values.
(obj_elf_section_type): Handle parsing numeric values.
(obj_elf_section): Allow numeric type values.
* config/obj-elf.h (obj_elf_change_section): Update prototype.
* testsuite/gas/elf/section10.d: New test.
* testsuite/gas/elf/section10.s: Source file for new test.
* testsuite/gas/elf/elf.exp: Run the new test.
* testsuite/gas/i386/ilp32/x86-64-unwind.d: Remove dependency upon
the description of the flags produced by readelf.
* testsuite/gas/tic6x/scomm-directive-4.d: Likewise.
* NEWS: Mention the new feature.
bfd * elf-bfd.h (struct bfd_elf_special_section): Use unsigned values
for length and type fields. Use a signed value for the
suffix_length field.
binutils* readelf.c (get_section_type_name): Add hex prefix to offsets
printed for LOPROC and LOOS values. Ensure that a result is
always returned for the V850 target, even when an unrecognised
processor specific value is encountered.
(process_section_headers): Display key values in the order in
which they appear to the user. Add the "C (compressed)" value to
the list.
ld * testsuite/ld-i386/pr12718.d: Remove dependency upon the
description of the flags produced by readelf.
* testsuite/ld-i386/pr12921.d: Likewise.
* testsuite/ld-i386/tlsbin-nacl.rd: Likewise.
* testsuite/ld-i386/tlsbin.rd: Likewise.
* testsuite/ld-i386/tlsbindesc-nacl.rd: Likewise.
* testsuite/ld-i386/tlsbindesc.rd: Likewise.
* testsuite/ld-i386/tlsdesc-nacl.rd: Likewise.
* testsuite/ld-i386/tlsdesc.rd: Likewise.
* testsuite/ld-i386/tlsgdesc-nacl.rd: Likewise.
* testsuite/ld-i386/tlsgdesc.rd: Likewise.
* testsuite/ld-i386/tlsnopic-nacl.rd: Likewise.
* testsuite/ld-i386/tlsnopic.rd: Likewise.
* testsuite/ld-i386/tlspic-nacl.rd: Likewise.
* testsuite/ld-i386/tlspic.rd: Likewise.
* testsuite/ld-s390/tlsbin.rd: Likewise.
* testsuite/ld-s390/tlsbin_64.rd: Likewise.
* testsuite/ld-s390/tlspic.rd: Likewise.
* testsuite/ld-s390/tlspic_64.rd: Likewise.
* testsuite/ld-sh/tlsbin-2.d: Likewise.
* testsuite/ld-sh/tlspic-2.d: Likewise.
* testsuite/ld-tic6x/common.d: Likewise.
* testsuite/ld-tic6x/shlib-1.rd: Likewise.
* testsuite/ld-tic6x/shlib-1b.rd: Likewise.
* testsuite/ld-tic6x/shlib-1r.rd: Likewise.
* testsuite/ld-tic6x/shlib-1rb.rd: Likewise.
* testsuite/ld-tic6x/shlib-app-1.rd: Likewise.
* testsuite/ld-tic6x/shlib-app-1b.rd: Likewise.
* testsuite/ld-tic6x/shlib-app-1r.rd: Likewise.
* testsuite/ld-tic6x/shlib-app-1rb.rd: Likewise.
* testsuite/ld-tic6x/shlib-noindex.rd: Likewise.
* testsuite/ld-tic6x/static-app-1.rd: Likewise.
* testsuite/ld-tic6x/static-app-1b.rd: Likewise.
* testsuite/ld-tic6x/static-app-1r.rd: Likewise.
* testsuite/ld-tic6x/static-app-1rb.rd: Likewise.
* testsuite/ld-x86-64/ilp32-4-nacl.d: Likewise.
* testsuite/ld-x86-64/ilp32-4.d: Likewise.
* testsuite/ld-x86-64/pr12718.d: Likewise.
* testsuite/ld-x86-64/pr12921.d: Likewise.
* testsuite/ld-x86-64/split-by-file-nacl.rd: Likewise.
* testsuite/ld-x86-64/split-by-file.rd: Likewise.
* testsuite/ld-x86-64/tlsbin-nacl.rd: Likewise.
* testsuite/ld-x86-64/tlsbin.rd: Likewise.
* testsuite/ld-x86-64/tlsbindesc-nacl.rd: Likewise.
* testsuite/ld-x86-64/tlsbindesc.rd: Likewise.
* testsuite/ld-x86-64/tlsdesc-nacl.rd: Likewise.
* testsuite/ld-x86-64/tlsdesc.rd: Likewise.
* testsuite/ld-x86-64/tlsgdesc-nacl.rd: Likewise.
* testsuite/ld-x86-64/tlsgdesc.rd: Likewise.
* testsuite/ld-x86-64/tlspic-nacl.rd: Likewise.
* testsuite/ld-x86-64/tlspic.rd: Likewise.
* testsuite/ld-xtensa/tlsbin.rd: Likewise.
* testsuite/ld-xtensa/tlspic.rd: Likewise.
|
|
generation has not yet started.
PR gas/19614
* dw2gencfi.c (cfi_sections_set): Delay setting this variable
until it is actually used.
(cfi_set_sections): Set cfi_sections_set to true.
(dot_cfi_startproc): Likewise.
(dot_cfi_endproc): Likewise.
(dot_cfi_fde_data): Likewise.
(cfi_finish): Likewise.
(dot_cfi_sections): Do not set cfi_sections_set.
* doc/as.texinfo (.cfi_sections): Note that targets can provide
their own cfi section name. Also note that the directive can be
reissued provided that CFI generation has not started.
* testsuite/gas/mips/compact-eh-err2.s: Add .cfi_startproc and
.cfi_endproc directives so that the redefinition of .cfi_sections
will trigger the generation of the error message.
* testsuite/gas/mips/compact-eh-err2.l: Update expected line
number of error message.
|
|
gas/
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
Janek van Oirschot <jvanoirs@synopsys.com>
* config/tc-arc.h (TC_FRAG_TYPE, TC_PCREL_ADJUST, MAX_INSN_ARGS)
(MAX_INSN_FLGS, MAX_FLAG_NAME_LENGHT, TC_GENERIC_RELAX_TABLE):
Define.
(arc_flags, arc_relax_type): New structure.
* config/tc-arc.c (FRAG_MAX_GROWTH, RELAX_TABLE_ENTRY)
(RELAX_TABLE_ENTRY_MAX): New define.
(relaxation_state, md_relax_table, arc_relaxable_insns)
(arc_num_relaxable_ins): New variable.
(rlx_operand_type, arc_rlx_types): New enums.
(arc_relaxable_ins): New structure.
(OPTION_RELAX): New option.
(arc_insn): New relax member.
(arc_flags): Remove.
(relax_insn_p): New function.
(apply_fixups): Likewise.
(relaxable_operand): Likewise.
(may_relax_expr): Likewise.
(relaxable_flag): Likewise.
(arc_pcrel_adjust): Likewise.
(md_estimate_size_before_relax): Implement.
(md_convert_frag): Likewise.
(md_parse_option): Handle new mrelax option.
(md_show_usage): Likewise.
(assemble_insn): Set relax member.
(emit_insn0): New function.
(emit_insn1): Likewise.
(emit_insn): Handle relaxation case.
* NEWS: Mention the new relaxation option.
* doc/c-arc.texi (ARC Options): Document new mrelax option.
gas/testsuite
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
* gas/arc/relax-avoid1.d: New file.
* gas/arc/relax-avoid1.s: Likewise.
* gas/arc/relax-avoid2.d: Likewise.
* gas/arc/relax-avoid2.s: Likewise.
* gas/arc/relax-avoid3.d: Likewise.
* gas/arc/relax-avoid3.s: Likewise.
* gas/arc/relax-b.d: Likewise.
* gas/arc/relax-b.s: Likewise.
include/opcode/
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
Janek van Oirschot <jvanoirs@synopsys.com>
* arc.h (arc_opcode arc_relax_opcodes, arc_num_relax_opcodes):
Declare.
opcodes/
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
Janek van Oirschot <jvanoirs@synopsys.com>
* arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
variable.
|
|
gas * config/obj-elf.c (obj_elf_change_section): Remove support for
ARM NOREAD sections.
* config/tc-arm.c (arm_elf_section_letter): Delete.
* config/tc-arm.h (md_elf_section_letter): Delete.
* doc/c-arm.texi (ARM Section Attribute): Delete section.
* testsuite/gas/arm/section-execute-only.d: Delete.
* testsuite/gas/arm/section-execute-only.s: Delete.
ld * testsuite/ld-arm/arm-elf.exp: Remove ARM NOREAD section tests.
* testsuite/ld-arm/thumb1-input-section-flag-match.d: Delete.
* testsuite/ld-arm/thumb1-input-section-flag-match.s: Delete.
* testsuite/ld-arm/thumb1-noread-not-present-mixing-two-section.d: Delete.
* testsuite/ld-arm/thumb1-noread-not-present-mixing-two-section.s: Delete.
* testsuite/ld-arm/thumb1-noread-present-one-section.d: Delete.
* testsuite/ld-arm/thumb1-noread-present-one-section.s: Delete.
* testsuite/ld-arm/thumb1-noread-present-two-section.d: Delete.
* testsuite/ld-arm/thumb1-noread-present-two-section.s: Delete.
|
|
PR target/19561
opcdoe * msp430-dis.c (print_insn_msp430): Add a special case for
decoding an RRC instruction with the ZC bit set in the extension
word.
include * opcode/msp430.h (IGNORE_CARRY_BIT): New define.
(RRUX): Synthesise using case 2 rather than 7.
gas * config/tc-msp430.c (msp430_operands): Remove case 7. Use case 2
to handle encoding of RRUX instruction.
* testsuite/gas/msp430/msp430x.s: Add more tests of the extended
shift instructions.
* testsuite/gas/msp430/msp430x.d: Update expected disassembly.
|
|
Change 1058c7532d0b "Use signed data type for R_XTENSA_DIFF* relocation
offsets." changed signedness of BFD_RELOC_XTENSA_DIFF* relocations
substituted for BFD_RELOC_*. This made it impossible to encode arbitrary
8-, 16- and 32-bit values, which broke e.g. debug info encoding by .loc
directive. Revert this part and add test.
gas/
2016-02-03 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (md_apply_fix): Mark BFD_RELOC_XTENSA_DIFF*
substitutions for BFD_RELOC_* as unsigned.
* gas/testsuite/gas/xtensa/all.exp: Add loc to list of xtensa
tests.
* gas/testsuite/gas/xtensa/loc.d: New file: loc test result
patterns.
* gas/testsuite/gas/xtensa/loc.s: New file: loc test.
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|
The x86 relax relocations introduced in binutils 2.26 aren't supported
by linker on Solaris older than Solaris 12. To use x86 assembler with
older Solaris linker, this patch adds
1. A command line option -mrelax-relocations= to x86 assembler to
control whether to generate relax relocations.
2. A configure option --enable-x86-relax-relocations to decide whether
x86 assembler should generate relax relocations by default. It is
defaulted to yes, except for x86 Solaris targets older than Solaris 12.
gas/
PR gas/19520
* NEWS: Mention new command line option -mrelax-relocations and
new configure option --enable-x86-relax-relocations for x86
target.
* config.in: Regenerated.
* configure.ac: Add --enable-x86-relax-relocations.
(ac_default_x86_relax_relocations): New. Default to 1 except
for x86 Solaris targets older than Solaris 12.
(DEFAULT_GENERATE_X86_RELAX_RELOCATIONS): Define.
* configure: Likewise.
* config/tc-i386.c (generate_relax_relocations): New.
(OPTION_MRELAX_RELOCATIONS): Likewise.
(output_disp): Don't generate relax relocations if
generate_relax_relocations is 0.
(md_longopts): Add -mrelax-relocations.
(md_show_usage): Likewise.
(md_parse_option): Handle OPTION_MRELAX_RELOCATIONS.
* doc/c-i386.texi: Document -mrelax-relocations=.
* testsuite/gas/i386/got-no-relax.d: New file.
* testsuite/gas/i386/x86-64-gotpcrel-no-relax.d: Likewise.
* testsuite/gas/i386/got.d: Pass -mrelax-relocations=yes to as.
* testsuite/gas/i386/localpic.d: Likewise.
* testsuite/gas/i386/mixed-mode-reloc32.d: Likewise.
* testsuite/gas/i386/reloc32.d: Likewise.
* testsuite/gas/i386/x86-64-gotpcrel.d: Likewise.
* testsuite/gas/i386/x86-64-localpic.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-gotpcrel.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-localpic.d: Likewise.
* testsuite/gas/i386/i386.exp: Run got-no-relax and
x86-64-gotpcrel-no-relax.
ld/
PR gas/19520
* testsuite/ld-i386/branch1.d: Pass -mrelax-relocations=yes to as.
* testsuite/ld-i386/call1.d: Likewise.
* testsuite/ld-i386/call2.d: Likewise.
* testsuite/ld-i386/call3a.d: Likewise.
* testsuite/ld-i386/call3b.d: Likewise.
* testsuite/ld-i386/call3c.d: Likewise.
* testsuite/ld-i386/call3d.d: Likewise.
* testsuite/ld-i386/call3e.d: Likewise.
* testsuite/ld-i386/call3f.d: Likewise.
* testsuite/ld-i386/call3g.d: Likewise.
* testsuite/ld-i386/call3h.d: Likewise.
* testsuite/ld-i386/jmp1.d: Likewise.
* testsuite/ld-i386/jmp2.d: Likewise.
* testsuite/ld-i386/lea1c.d: Likewise.
* testsuite/ld-i386/load1.d: Likewise.
* testsuite/ld-i386/load2.d: Likewise.
* testsuite/ld-i386/load3.d: Likewise.
* testsuite/ld-i386/load4a.d: Likewise.
* testsuite/ld-i386/load5a.d: Likewise.
* testsuite/ld-i386/mov2b.d: Likewise.
* testsuite/ld-i386/mov3.d: Likewise.
* testsuite/ld-ifunc/ifunc-21-x86-64.d: Likewise.
* testsuite/ld-ifunc/ifunc-22-x86-64.d: Likewise.
* testsuite/ld-ifunc/ifunc-5r-local-x86-64.d: Likewise.
* testsuite/ld-x86-64/call1a.d: Likewise.
* testsuite/ld-x86-64/call1b.d: Likewise.
* testsuite/ld-x86-64/call1c.d: Likewise.
* testsuite/ld-x86-64/call1d.d: Likewise.
* testsuite/ld-x86-64/call1e.d: Likewise.
* testsuite/ld-x86-64/call1f.d: Likewise.
* testsuite/ld-x86-64/call1h.d: Likewise.
* testsuite/ld-x86-64/call1i.d: Likewise.
* testsuite/ld-x86-64/load1a.d: Likewise.
* testsuite/ld-x86-64/load1b.d: Likewise.
* testsuite/ld-i386/got1a.S: Load GOT into %ecx and use it.
* testsuite/ld-i386/got1.dd: Updated.
* testsuite/ld-i386/got1d.S (1): Removed.
* testsuite/ld-i386/i386.exp: Add -Wa,-mrelax-relocations=yes.
* testsuite/ld-x86-64/x86-64.exp: Likewise.
|
|
gas/
* testsuite/gas/arm/thumb2_it_search.d: Skip non-elf targets.
|
|
Basic all instructions assembler test, auto-generated by CGEN, then
fixed by hand for some cases where CGEN had generated invalid
instruction operands.
gas/ChangeLog:
* testsuite/gas/ip2k/allinsn.d: New file.
* testsuite/gas/ip2k/allinsn.s: New file.
* testsuite/gas/ip2k/ip2k-allinsn.exp: New file.
|
|
In commit 02a79b89fdeadccb67048291e6c2a1e5ce6ad623 some of the load
instructions with a zero offset (where the offset is not mentioned) were
marked as NO-DIS, meaning that the disassembler must display the offset,
even though it is zero.
This change seems a little strange to me as it was only applied to some
loads, not all, and the same change was not applied to the stores.
However, I'm reluctant to revert a specific change to the assembler,
when the output is obviously correct. With this commit then I simply
bring the expected assembler test results into line with what is
actually produced.
gas/ChangeLog:
* testsuite/gas/epiphany/addr-syntax.d: Add explicit 0 offset to
some load instructions.
* testsuite/gas/epiphany/allinsn.d: Likewise.
* testsuite/gas/epiphany/regression.d: Likewise.
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|
In commit 02a79b89fdeadccb67048291e6c2a1e5ce6ad623 all instruction
aliases that have a '.l' suffix were marked as NO-DIS, so the
disassembler will not display them, in preference to the instruction
without the suffix. However, the gas testsuite was not updated at the
time, this commit fixes that oversight.
gas/ChangeLog:
* testsuite/gas/epiphany/addr-syntax.d: Remove unneeded '.l'
suffixes from instruction mnemonics in expected output.
* testsuite/gas/epiphany/allinsn.d: Likewise.
* testsuite/gas/epiphany/regression.d: Likewise.
* testsuite/gas/epiphany/sample.d: Likewise.
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In commit 02a79b89fdeadccb67048291e6c2a1e5ce6ad623 the register aliases
sb, sl, and ip were made less preferred than r9, r10, and r12, however,
the expected test results were not updated. This commit fixes this
oversight and updates the test results.
gas/ChangeLog:
* testsuite/gas/epiphany/addr-syntax.d: Update expected register
names.
* testsuite/gas/epiphany/allinsn.d: Likewise.
* testsuite/gas/epiphany/sample.d: Likewise.
|
|
Always set the bytes_per_line field (of struct disassemble_info) to the
same constant value, this is inline with the advice contained within
include/dis-asm.h.
Setting this field to a constant value will cause the disassembler
output to be better aligned.
cpu/ChangeLog:
* epiphany.opc (epiphany_print_insn): Set info->bytes_per_line to
a constant to better align disassembler output.
opcodes/ChangeLog:
* epiphany-dis.c: Regenerated from latest cpu files.
gas/ChangeLog:
* testsuite/gas/epiphany/sample.d: Update expected output.
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* config/tc-arc.c (md_apply_fix): Allow addendum.
(arc_reloc_op): Allow complex expressions for tpoff.
(md_apply_fix): Handle resolved TLS local symbol.
* gas/arc/tls-relocs1.d: New file.
* gas/arc/tls-relocs1.s: Likewise.
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|
With -mfence-as-lock-add=yes lfence, mfence and sfence will be encoded
as lock addl $0x0, (%{r,e}sp).
gas/:
* config/tc-i386.c (avoid_fence): New.
(output_insn): Encode as lock addl $0x0, (%{r,e}sp) if avoid_fence
is true.
(OPTION_FENCE_AS_LOCK_ADD): New.
(md_longopts): Add -mfence-as-lock-add.
(md_parse_option): Handle -mfence-as-lock-add.
(md_show_usage): Add -mfence-as-lock-add=[no|yes].
* doc/c-i386.texi (-mfence-as-lock-add): Document.
gas/testsuite/:
* gas/i386/i386.exp: Run new tests.
* gas/i386/fence-as-lock-add.s: New.
* gas/i386/fence-as-lock-add-yes.d: Likewise.
* gas/i386/fence-as-lock-add-no.d: Likewise.
* gas/i386/x86-64-fence-as-lock-add-yes.d: Likewise.
* gas/i386/x86-64-fence-as-lock-add-no.d: Likewise.
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* testsuite/gas/arm/thumb2_it_search.d: Skip for PE targets.
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|
|
|
opcodes/
* arm-dis.c (mapping_symbol_for_insn): New function.
(find_ifthen_state): Call mapping_symbol_for_insn().
gas/
* testsuite/gas/arm/thumb2_it_search.d: New.
* testsuite/gas/arm/thumb2_it_search.s: New.
|
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PR gas/19454
* testsuite/gas/arm/mapshort-elf.d: Fix expected output to cope
with arm-netbsdelf target.
* testsuite/gas/arm/blx-bl-convert.d: Skip for netbsdelf.
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PR 19456
* testsuite/gas/arm/weakdef-1.d: Skip for VxWorks.
* testsuite/gas/arm/blx-bl-convert.d
* testsuite/gas/arm/plt-1.d: Likewise.
* testsuite/gas/arm/reloc-bad.d: Likewise.
* testsuite/gas/arm/thumb-w-good.d: Likewise.
* testsuite/gas/arm/thumb2_pool.d: Likewise.
* testsuite/gas/arm/ldconst.d: Adjust so that it works with VxWorks
* testsuite/gas/arm/tls_vxworks.d: Update expected output.
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In the instruction to write to the ARMv8.2 PSTATE field UAO,
MSR UAO, #<imm>, the immediate should be either 0 or 1 but GAS accepts
any unsigned 4-bit integer.
This patch implements the constraint on the immediate, generating an
error if the immediate operand is invalid, and adds tests for the
illegal forms.
opcodes/
2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (operand_general_constraint_met_p): Check validity
of MSR UAO immediate operand.
gas/
2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
* testsuite/gas/aarch64/armv8_2-a-illegal.d: New.
* testsuite/gas/aarch64/armv8_2-a-illegal.l: New.
* testsuite/gas/aarch64/armv8_2-a-illegal.s: New.
Change-Id: Ibdec4967c00b1ef3be9dbc43d23b2c70d1a0b28c
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