[ARC] Add support for Quarkse opcodes.

gas/
2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>

        * testsuite/gas/arc/ext2op.d: New file.
        * testsuite/gas/arc/ext2op.s: Likewise.
        * testsuite/gas/arc/ext3op.d: Likewise.
        * testsuite/gas/arc/ext3op.s: Likewise.

opcodes/
2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>

        * arc-tbl.h (invld07): Remove.
        * arc-ext-tbl.h: New file.
        * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
        * arc-opc.c (arc_opcodes): Add ext-tbl include.

include/
2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>

        * opcode/arc.h (insn_subclass_t): Add QUARKSE subclass.
        (FIELDA, FIELDB, FIELDC, FIELDF, FIELDQ, INSN3OP, INSN2OP)
        (INSN2OP, INSN3OP_ABC, INSN3OP_ALC, INSN3OP_ABL, INSN3OP_ALL)
        (INSN3OP_0BC, INSN3OP_0LC, INSN3OP_0BL, INSN3OP_0LL, INSN3OP_ABU)
        (INSN3OP_ALU, INSN3OP_0BU, INSN3OP_0LU, INSN3OP_BBS, INSN3OP_0LS)
        (INSN3OP_CBBC, INSN3OP_CBBL, INSN3OP_C0LC, INSN3OP_C0LL)
        (INSN3OP_CBBU, INSN3OP_C0LU, MINSN3OP_ABC, MINSN3OP_ALC)
        (MINSN3OP_ABL, MINSN3OP_ALL, MINSN3OP_0BC, MINSN3OP_0LC)
        (MINSN3OP_0BL, MINSN3OP_0LL, MINSN3OP_ABU, MINSN3OP_ALU)
        (MINSN3OP_0BU, MINSN3OP_0LU, MINSN3OP_BBS, MINSN3OP_0LS)
        (MINSN3OP_CBBC, MINSN3OP_CBBL, MINSN3OP_C0LC, MINSN3OP_C0LL)
        (MINSN3OP_CBBU, MINSN3OP_C0LU, INSN2OP_BC, INSN2OP_BL, INSN2OP_0C)
        (INSN2OP_0L INSN2OP_BU, INSN2OP_0U, MINSN2OP_BC, MINSN2OP_BL)
        (MINSN2OP_0C, MINSN2OP_0L, MINSN2OP_BU, MINSN2OP_0U): Define.

4 files changed, 175 insertions, 0 deletions

diff --git a/gas/testsuite/gas/arc/ext2op.d b/gas/testsuite/gas/arc/ext2op.d
new file mode 100644
index 0000000..144989e
--- /dev/null
+++ b/gas/testsuite/gas/arc/ext2op.d
@@ -0,0 +1,25 @@
+#as: -mcpu=arcem
+#objdump: -dr
+
+.*: +file format .*arc.*
+
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.text>:
+   0:	382f 006d           	dsp_fp_sqrt	r0,r1
+   4:	3b2f 372d           	dsp_fp_sqrt	fp,sp
+   8:	386f 002d           	dsp_fp_sqrt	r0,0
+   c:	392f 0fad ffff ffff 	dsp_fp_sqrt	r1,0xffffffff
+  14:	3e2f 70ad           	dsp_fp_sqrt	0,r2
+  18:	3c2f 0fad 0000 00ff 	dsp_fp_sqrt	r4,0xff
+  20:	3e2f 0fad ffff ff00 	dsp_fp_sqrt	r6,0xffffff00
+  28:	382f 1fad 0000 0100 	dsp_fp_sqrt	r8,0x100
+  30:	392f 1fad ffff feff 	dsp_fp_sqrt	r9,0xfffffeff
+  38:	3b2f 1fad 4242 4242 	dsp_fp_sqrt	r11,0x42424242
+  40:	382f 0fad 0000 0000 	dsp_fp_sqrt	r0,0
+			44: R_ARC_32_ME	foo
+  48:	382f 806d           	dsp_fp_sqrt.f	r0,r1
+  4c:	3a6f 806d           	dsp_fp_sqrt.f	r2,0x1
+  50:	3e2f f12d           	dsp_fp_sqrt.f	0,r4
+  54:	3d2f 8fad 0000 0200 	dsp_fp_sqrt.f	r5,0x200
diff --git a/gas/testsuite/gas/arc/ext2op.s b/gas/testsuite/gas/arc/ext2op.s
new file mode 100644
index 0000000..f99009d
--- /dev/null
+++ b/gas/testsuite/gas/arc/ext2op.s
@@ -0,0 +1,21 @@
+# 2 operand insn test
+
+        dsp_fp_sqrt r0,r1
+        dsp_fp_sqrt fp,sp
+
+        dsp_fp_sqrt r0,0
+        dsp_fp_sqrt r1,-1
+        dsp_fp_sqrt 0,r2
+        dsp_fp_sqrt r4,255
+        dsp_fp_sqrt r6,-256
+
+        dsp_fp_sqrt r8,256
+        dsp_fp_sqrt r9,-257
+        dsp_fp_sqrt r11,0x42424242
+
+        dsp_fp_sqrt r0,foo
+
+        dsp_fp_sqrt.f r0,r1
+        dsp_fp_sqrt.f r2,1
+        dsp_fp_sqrt.f 0,r4
+        dsp_fp_sqrt.f r5,512
diff --git a/gas/testsuite/gas/arc/ext3op.d b/gas/testsuite/gas/arc/ext3op.d
new file mode 100644
index 0000000..926a13c
--- /dev/null
+++ b/gas/testsuite/gas/arc/ext3op.d
@@ -0,0 +1,65 @@
+#as: -mcpu=arcem
+#objdump: -dr
+
+.*: +file format .*arc.*
+
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.text>:
+   0:	392a 0080           	dsp_fp_div	r0,r1,r2
+   4:	3b2a 371a           	dsp_fp_div	gp,fp,sp
+   8:	3d2a 37dd           	dsp_fp_div	ilink,ilink,blink
+   c:	396a 0000           	dsp_fp_div	r0,r1,0
+  10:	3e2a 7080 0000 0000 	dsp_fp_div	r0,0,r2
+  18:	392a 00be           	dsp_fp_div	0,r1,r2
+  1c:	392a 0f80 ffff ffff 	dsp_fp_div	r0,r1,0xffffffff
+  24:	3e2a 7080 ffff ffff 	dsp_fp_div	r0,0xffffffff,r2
+  2c:	392a 0f80 0000 00ff 	dsp_fp_div	r0,r1,0xff
+  34:	3e2a 7080 0000 00ff 	dsp_fp_div	r0,0xff,r2
+  3c:	392a 0f80 ffff ff00 	dsp_fp_div	r0,r1,0xffffff00
+  44:	3e2a 7080 ffff ff00 	dsp_fp_div	r0,0xffffff00,r2
+  4c:	39aa 0004           	dsp_fp_div	r1,r1,256
+  50:	396a 0fc0           	dsp_fp_div	r0,r1,0x3f
+  54:	3e2a 7080 ffff feff 	dsp_fp_div	r0,0xfffffeff,r2
+  5c:	3e2a 7f80 0000 0100 	dsp_fp_div	r0,0x100,0x100
+  64:	392a 0f80 0000 0000 	dsp_fp_div	r0,r1,0
+			68: R_ARC_32_ME	foo
+  6c:	38ea 0080           	dsp_fp_div	r0,r0,r2
+  70:	3bea 0140           	dsp_fp_div	r3,r3,r5
+  74:	3eea 0201           	dsp_fp_div.eq	r6,r6,r8
+  78:	39ea 12c1           	dsp_fp_div.eq	r9,r9,r11
+  7c:	3cea 1382           	dsp_fp_div.ne	r12,r12,r14
+  80:	3fea 1442           	dsp_fp_div.ne	r15,r15,r17
+  84:	3aea 2503           	dsp_fp_div.p	r18,r18,r20
+  88:	3dea 25c3           	dsp_fp_div.p	r21,r21,r23
+  8c:	38ea 3684           	dsp_fp_div.n	r24,r24,gp
+  90:	3bea 3744           	dsp_fp_div.n	fp,fp,ilink
+  94:	3eea 37c5           	dsp_fp_div.c	r30,r30,blink
+  98:	3bea 00c5           	dsp_fp_div.c	r3,r3,r3
+  9c:	3bea 0205           	dsp_fp_div.c	r3,r3,r8
+  a0:	3bea 0106           	dsp_fp_div.nc	r3,r3,r4
+  a4:	3cea 0106           	dsp_fp_div.nc	r4,r4,r4
+  a8:	3cea 01c6           	dsp_fp_div.nc	r4,r4,r7
+  ac:	3cea 0147           	dsp_fp_div.v	r4,r4,r5
+  b0:	3dea 0147           	dsp_fp_div.v	r5,r5,r5
+  b4:	3dea 0148           	dsp_fp_div.nv	r5,r5,r5
+  b8:	3dea 0148           	dsp_fp_div.nv	r5,r5,r5
+  bc:	3eea 0009           	dsp_fp_div.gt	r6,r6,r0
+  c0:	38ea 002a           	dsp_fp_div.ge	r0,r0,0
+  c4:	39ea 006b           	dsp_fp_div.lt	r1,r1,0x1
+  c8:	3bea 00ed           	dsp_fp_div.hi	r3,r3,0x3
+  cc:	3cea 012e           	dsp_fp_div.ls	r4,r4,0x4
+  d0:	3dea 016f           	dsp_fp_div.pnz	r5,r5,0x5
+  d4:	392a 8080           	dsp_fp_div.f	r0,r1,r2
+  d8:	396a 8040           	dsp_fp_div.f	r0,r1,0x1
+  dc:	3e2a f080 0000 0001 	dsp_fp_div.f	r0,0x1,r2
+  e4:	392a 80be           	dsp_fp_div.f	0,r1,r2
+  e8:	392a 8f80 0000 0200 	dsp_fp_div.f	r0,r1,0x200
+  f0:	3e2a f080 0000 0200 	dsp_fp_div.f	r0,0x200,r2
+  f8:	39ea 8081           	dsp_fp_div.eq.f	r1,r1,r2
+  fc:	38ea 8022           	dsp_fp_div.ne.f	r0,r0,0
+ 100:	3aea 808b           	dsp_fp_div.lt.f	r2,r2,r2
+ 104:	3eea f0a9 0000 0001 	dsp_fp_div.gt.f	0,0x1,0x2
+ 10c:	3eea ff8c 0000 0200 	dsp_fp_div.le.f	0,0x200,0x200
+ 114:	3eea f0aa 0000 0200 	dsp_fp_div.ge.f	0,0x200,0x2
diff --git a/gas/testsuite/gas/arc/ext3op.s b/gas/testsuite/gas/arc/ext3op.s
new file mode 100644
index 0000000..ccb3d4c
--- /dev/null
+++ b/gas/testsuite/gas/arc/ext3op.s
@@ -0,0 +1,64 @@
+# 3 operand insn test
+
+	dsp_fp_div r0,r1,r2
+	dsp_fp_div gp,fp,sp
+	dsp_fp_div ilink,ilink,blink
+
+	dsp_fp_div r0,r1,0
+	dsp_fp_div r0,0,r2
+	dsp_fp_div 0,r1,r2
+
+	dsp_fp_div r0,r1,-1
+	dsp_fp_div r0,-1,r2
+	dsp_fp_div r0,r1,255
+	dsp_fp_div r0,255,r2
+	dsp_fp_div r0,r1,-256
+	dsp_fp_div r0,-256,r2
+
+	dsp_fp_div r1,r1,256
+	dsp_fp_div r0,r1,0x3F
+	dsp_fp_div r0,-257,r2
+
+	dsp_fp_div r0,256,256
+
+	dsp_fp_div r0,r1,foo
+
+	dsp_fp_div.al r0,r0,r2
+	dsp_fp_div.ra r3,r3,r5
+	dsp_fp_div.eq r6,r6,r8
+	dsp_fp_div.z  r9,r9,r11
+	dsp_fp_div.ne r12,r12,r14
+	dsp_fp_div.nz r15,r15,r17
+	dsp_fp_div.pl r18,r18,r20
+	dsp_fp_div.p  r21,r21,r23
+	dsp_fp_div.mi r24,r24,r26
+	dsp_fp_div.n  r27,r27,r29
+	dsp_fp_div.cs r30,r30,r31
+	dsp_fp_div.c  r3,r3,r3
+	dsp_fp_div.lo r3,r3,r8
+	dsp_fp_div.cc r3,r3,r4
+	dsp_fp_div.nc r4,r4,r4
+	dsp_fp_div.hs r4,r4,r7
+	dsp_fp_div.vs r4,r4,r5
+	dsp_fp_div.v  r5,r5,r5
+	dsp_fp_div.vc r5,r5,r5
+	dsp_fp_div.nv r5,r5,r5
+	dsp_fp_div.gt r6,r6,r0
+	dsp_fp_div.ge r0,r0,0
+	dsp_fp_div.lt r1,r1,1
+	dsp_fp_div.hi r3,r3,3
+	dsp_fp_div.ls r4,r4,4
+	dsp_fp_div.pnz r5,r5,5
+	dsp_fp_div.f r0,r1,r2
+	dsp_fp_div.f r0,r1,1
+	dsp_fp_div.f r0,1,r2
+	dsp_fp_div.f 0,r1,r2
+	dsp_fp_div.f r0,r1,512
+	dsp_fp_div.f r0,512,r2
+
+	dsp_fp_div.eq.f r1,r1,r2
+	dsp_fp_div.ne.f r0,r0,0
+	dsp_fp_div.lt.f r2,r2,r2
+	dsp_fp_div.gt.f 0,1,2
+	dsp_fp_div.le.f 0,512,512
+	dsp_fp_div.ge.f 0,512,2