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4 daysRISC-V: Support SiFive extensions: xsfvqmaccdod, xsfvqmaccqoq and ↵Nelson Chu6-0/+56
xsfvfnrclipxfqf Those SiFive extensions have been published on the web for a while, and we plan to implement intrinsics in GCC for those instructions soon. NOTE: The original patch was written by Nelson when he was still working at SiFive, and Kito rebased it to the trunk. Therefore, I kept the author as Nelson with his SiFive email. Document links: xsfvqmaccdod: https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification xsfvqmaccqoq: https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification xsfvfnrclipxfqf: https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
5 daysPowerPC: Add support for RFC02677 - VSX Vector Rotate Left WordPeter Bergner2-0/+2
opcodes/ * ppc-opc.c (powerpc_opcodes): Add xvrlw. gas/ * testsuite/gas/ppc/future.s: Add test for xvrlw. * testsuite/gas/ppc/future.d: Likewise.
5 daysarm: Support pac_key_* register operand for MRS/MSR in Armv8.1-M MainlineAndre Vieira2-0/+214
Add support for pac_key_[pu]_[0-3](_ns)? register operands for the MRS and MSR instructions when assembling for Armv8.1-M Mainline, as well as adding the corresponding support for disassembling instructions that use it.
6 daysRISC-V: Add Zcmt instructions and csr.Jiawei13-0/+64
This patch supports Zcmt[1] instruction 'cm.jt' and 'cm.jalt'. Add new CSR jvt for tablejump using. Since 'cm.jt' and 'cm.jalt' have the same instructiong encoding, use 'match_cm_jt' and 'match_cm_jalt' check the 'zcmt_index' field to distinguish them. [1] https://github.com/riscvarchive/riscv-code-size-reduction/releases Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com> Co-Authored by: Mary Bennett <mary.bennett@embecosm.com> Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com> Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com> Co-Authored by: Simon Cook <simon.cook@embecosm.com> Co-Authored by: Shihua Liao <shihua@iscas.ac.cn> Co-Authored by: Yulong Shi <yulong@iscas.ac.cn> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): New extension. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): New CSR. (riscv_csr_address): Ditto. (validate_riscv_insn): New operand. (riscv_ip): Ditto. * testsuite/gas/riscv/csr-version-1p10.d: New CSR. * testsuite/gas/riscv/csr-version-1p10.l: Ditto. * testsuite/gas/riscv/csr-version-1p11.d: Ditto. * testsuite/gas/riscv/csr-version-1p11.l: Ditto. * testsuite/gas/riscv/csr-version-1p12.d: Ditto. * testsuite/gas/riscv/csr-version-1p12.l: Ditto. * testsuite/gas/riscv/csr.s: Ditto. * testsuite/gas/riscv/march-help.l: New extension. * testsuite/gas/riscv/zcmt-fail.d: New test. * testsuite/gas/riscv/zcmt-fail.l: New test. * testsuite/gas/riscv/zcmt-fail.s: New test. * testsuite/gas/riscv/zcmt.d: New test. * testsuite/gas/riscv/zcmt.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_CM_JT): New opcode. (MASK_CM_JT): New mask. (MATCH_CM_JALT): New opcode. (MASK_CM_JALT): New mask. (CSR_JVT): New CSR. (DECLARE_INSN): New declaration. (DECLARE_CSR): Ditto. * opcode/riscv.h (EXTRACT_ZCMT_INDEX): New marco. (ENCODE_ZCMT_INDEX): Ditto. (enum riscv_insn_class): New class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): New operand. * riscv-opc.c (match_cm_jt): New function. (match_cm_jalt): Ditto.
7 daysSupport x86 Intel MSR_IMMHu, Lin19-0/+126
gas/ChangeLog: * NEWS: Support x86 Intel MSR_IMM. * config/tc-i386.c (cpu_arch): Add MSR_IMM. (cpu_flags_match): Add MSR_IMM to APX_F related processing. (i386_assemble): WRMSRNS's first operand is imm32, so add MN_wrmsrns like MN_uwrmsr. * doc/c-i386.texi: Document .msr_imm. * testsuite/gas/i386/i386.exp: Run MSR_IMM tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/msr_imm-inval.l: New test. * testsuite/gas/i386/msr_imm-inval.s: Ditto. * testsuite/gas/i386/x86-64-msr_imm-intel.d: Ditto. * testsuite/gas/i386/x86-64-msr_imm.d: Ditto. * testsuite/gas/i386/x86-64-msr_imm.s: Ditto. opcodes/ChangeLog: * i386-dis.c: Add REG_VEX_MAP7_F6_L_0_W_0, PREFIX_VEX_MAP7_F6_L_0_W_0_R_0_X86_64, X86_64_VEX_MAP7_F6_L_0_W_0_R_0, VEX_LEN_MAP7_F6, VEX_W_MAP7_F6_L_0. (reg_table): New entry for MSR_IMM. (prefix_table): Ditto. (x86_64_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (map7_f6_opcode): New variable for MAP7. (get_valid_dis386): Support MAP7. * i386-gen.c (cpu_flags): Add MSR_IMM. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (i386_cpu_flags): Add cpumsr_imm. * i386-opc.tbl: Add MSR_IMM instructions. * i386-tbl.h: Regenerated.
8 daysx86: VP2INTERSECT{D,Q} have mask register destination groupJan Beulich15-244/+287
Much like AVX512-{4FMAPS,4VNNIW} have a constraint on their register source, there's a constraint (need to be even) on the destination register here. Adjust "good" test cases accordingly, and add a new test case to check the warning.
8 daysx86: generalize "implicit quad group" handlingJan Beulich5-18/+39
We'll want to re-use it for VP2INTERSECT{D,Q}. While there add a testcase for the similarly affected AVX512-4VNNIW insns.
8 dayss390: Add arch15 Concurrent-Functions Facility insnsJens Remus2-0/+8
opcodes/ * s390-opc.txt: Add arch15 Concurrent-Functions Facility instructions. * s390-opc.c (INSTR_SSF_RRDRD2, MASK_SSF_RRDRD2): New SSF instruction format variant. gas/testsuite/ * gas/s390/zarch-arch15.d: Tests for arch15 Concurrent-Functions Facility instructions. * gas/s390/zarch-arch15.s: Likewise. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
13 daysgas: add .cv_ucomp and .cv_scomp pseudo-directivesMark Harmstone3-0/+124
Add .cv_ucomp and .cv_scomp pseudo-directives for object files for Windows targets, which encode compressed CodeView integers according to the algorithm in CVCompressData in https://github.com/Microsoft/microsoft-pdb/blob/master/include/cvinfo.h. This is essentially Microsoft's answer to the LEB128, though used in far fewer places. CodeView uses these to encode the "binary annotations" in the S_INLINESITE symbol, which express the relationship between code offsets and line numbers in inlined functions. This has to be done in the assembler as GCC doesn't know how many bytes each instruction takes up. There's no equivalent for this for MSVC or LLVM, as in both cases the assembler and compiler are integrated. .cv_ucomp represents an unsigned big-endian integer between 0 and 0x1fffffff, taking up 1, 2, or 4 bytes: Value between 0 and 0x7f: 0aaaaaaa -> 0aaaaaaa (identity-mapped) Value between 0x80 and 0x3fff: 00aaaaaa bbbbbbbb -> 10aaaaaa bbbbbbbb Value between 0x4000 and 0x1fffffff: 000aaaaa bbbbbbbb ccccccccc dddddddd -> 110aaaaa bbbbbbbb ccccccccc dddddddd .cv_scomp represents a signed big-endian integer between -0xfffffff and 0xfffffff, encoded according to EncodeSignedInt32 in cvinfo.h. The absolute value of the integer is shifted left one bit, the LSB set for a negative value, and the result expressed as if it were a .cv_ucomp: cv_scomp(x) = cv_ucomp((abs(x) << 1) | (x < 0 ? 1 : 0))
2024-11-08aarch64: testsuite: remove hard-coded instruction addressesMatthieu Longo1-26/+26
2024-11-08arm, objdump: print obsolote warning when 26-bit set in instructionsAndre Vieira5-76/+36
Arm has obsoleted the 26-bit addressing mode. Diagnose this when disasembling these instructions by printing OBSOLETE.
2024-11-08arm, objdump: Make objdump use bfd's machine detection to drive disassemblyAndre Vieira4-17/+19
For any arm elf target, disable an old piece of code that forced disassembly to disassemble for 'unknown architecture' which once upon a time meant it would disassemble ANY arm instruction. This is no longer true with the addition of Armv8.1-M Mainline, as there are conflicting encodings for different thumb instructions. BFD however can detect what architecture the object file was assembled for using information in the notes section. So if available, we use that, otherwise we default to the old 'unknown' behaviour. With the changes above code, a mode changing 'bx lr' assembled for armv4 with the option --fix-v4bx will result in an object file that is recognized by bfd as one for the armv4 architecture. The disassembler now disassembles this encoding as a BX even for Armv4 architectures, but warns the user when disassembling for Armv4 that this instruction is only valid from Armv4T onwards. Remove the unused and wrongfully defined ARM_ARCH_V8A_CRC, and define and use a ARM_ARCH_V8R_CRC to make sure instructions enabled by -march=armv8-r+crc are disassembled correctly. Patch up some of the tests cases, see a brief explanation for each below. inst.d: This test checks the assembly & disassembly of basic instructions in armv3m. I changed the expected behaviour for teqp, cmnp cmpp and testp instructions to properly print p when disassembling, whereas before, in the 'unknown' case it would disassemble these as UNPREDICTABLE as they were changed in later architectures. nops.d: Was missing an -march, added one to make sure we were testing the right behavior of NOP<c> instructions. unpredictable.d: Was missing an -march, added armv6 as that reproduced the behaviour being tested.
2024-11-07arm: Skip two failing tests for wince & pe targetsAndre Simoes Dias Vieira2-0/+2
We don't seem to support any m-profile assembly/disassembly tests for wince or pe, so skipping the pacbti one too. The pr29494 test needs to be skipped because it uses assembly syntax that is not supported in wince/pe like for instance eabi_attribute directives.
2024-11-06PowerPC: Merge rfc2655 and rfc2656 test cases into one future test casePeter Bergner5-32/+18
gas/ * testsuite/gas/ppc/rfc02655.[ds]: Rename from this... * testsuite/gas/ppc/future.[ds]: ... to this. * testsuite/gas/ppc/rfc02656.[ds]: Delete. Move tests to future.[ds]. * testsuite/gas/ppc/ppc.exp: Update for file name changes.
2024-10-30x86/APX: support JMPABS also in assemblerJan Beulich3-3/+26
Without this APX support isn't really complete. For Intel syntax displacement form is needed, such that symbolic operands won't need prefixing by "offset". (The other form is actually not used at all in Intel syntax.) For the record: To restrict displacement form to Intel syntax is not something I actually agree with.
2024-10-30x86/APX: squash REX prefix when REX2 is being emittedJan Beulich2-0/+10
We should not (silently) emit a REX prefix ahead of a REX2-encoded insn; such encodings are illegal. Best we can do is fold the REX bits into the REX2 prefix, and then zap the REX one from i.prefix[].
2024-10-28RISC-V: Fix typo in gas/testsuite/gas/riscv/mapping.sJim Lin3-6/+6
gas/ * gas/riscv/mapping.s: Fix typo. * gas/riscv/mapping-dis.d: Fix typo. * gas/riscv/mapping-symbols.d. Fix typo.
2024-10-22LoongArch: Force relocation for every reference to the global offset tableLulu Cai2-0/+48
Local absolute symbols are resolved at assembly stage and the symbol value is placed in the relocation addend. But non-zero addend will cause an assertion failure during linking. Forces emission of relocations to defer resolution of local abs symbols until link time. bfd/ * elfnn-loongarch.c (loongarch_elf_relax_section): Determine absolute symbols in advance to avoid ld crash. gas/ * config/tc-loongarch.c (loongarch_force_relocation): New function to force relocation. * config/tc-loongarch.h (TC_FORCE_RELOCATION): New macros to force relocation. (loongarch_force_relocation): Function declaration. * testsuite/gas/loongarch/localpic.d: New test. * testsuite/gas/loongarch/localpic.s: New test.
2024-10-18x86: Support x86 ZHAOXIN GMI instructionsMayShao-oc3-0/+21
gas/ChangeLog: * NEWS: Support ZHAOXIN GMI instructions. * config/tc-i386.c: Add gmi. * doc/c-i386.texi: Document gmi. * testsuite/gas/i386/i386.exp: Add gmi test. * testsuite/gas/i386/gmi.d: Ditto. * testsuite/gas/i386/gmi.s: Ditto. opcodes/ChangeLog: * i386-dis.c: New comment. * i386-gen.c: Add gmi. * i386-opc.h (CpuGMI): New. * i386-opc.tbl: Add Zhaoxin GMI instructions. * i386-tbl.h: Regenerated. * i386-mnem.h: Ditto. * i386-init.h: Ditto.
2024-10-16Support Intel AVX10.2 convert instructionsLiwei Xu14-0/+1292
In this patch, we will support AVX10.2 convert instructions. All of them are new instruction forms. Among all the instructions, vcvtbiasph2[b,h]f8[,s] needs extra care. Since Operand 2 could indicate memory size, we do not need suffix under ATTmode. However, we could not fold all three templates but only XMM/YMM since the dst operand size are the same for them. Also, a new iterator <cvt8> is added to reduce redundancy. gas/ * testsuite/gas/i386/i386.exp: Add AVX10.2 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/avx10_2-256-cvt-intel.d: New. * testsuite/gas/i386/avx10_2-256-cvt.d: Ditto. * testsuite/gas/i386/avx10_2-256-cvt.s: Ditto. * testsuite/gas/i386/avx10_2-512-cvt-intel.d: Ditto. * testsuite/gas/i386/avx10_2-512-cvt.d: Ditto. * testsuite/gas/i386/avx10_2-512-cvt.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-cvt-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-cvt.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-cvt.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-cvt-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-cvt.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-cvt.s: Ditto. opcodes/ * i386-dis-evex-prefix.h: Add PREFIX_EVEX_0F3874, PREFIX_EVEX_MAP5_18, PREFIX_EVEX_MAP5_1B, PREFIX_EVEX_MAP5_1E and PREFIX_EVEX_MAP5_74. * i386-dis-evex.h: Add table pass for AVX10.2 instructions. * i386-dis.c (MOD_EVEX_0F38B1): New. (PREFIX_EVEX_0F3874): Ditto. (PREFIX_EVEX_MAP5_18): Ditto. (PREFIX_EVEX_MAP5_1B): Ditto. (PREFIX_EVEX_MAP5_1E): Ditto. (PREFIX_EVEX_MAP5_74): Ditto. * i386-opc.tbl: Add AVX10.2 instructions. * i386-mnem.h: Regenerated. * i386-tbl.h: Ditto. Co-authored-by: Kong Lingling <lingling.kong@intel.com> Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
2024-10-15x86/testsuite: Rename AVX10.2 media testcasesHaochen Jiang14-12/+12
Change these testcase name to make them clearer. gas/ChangeLog: * testsuite/gas/i386/avx10_2-256-1-intel.d: Renamed to... * testsuite/gas/i386/avx10_2-256-media-intel.d: ...this. * testsuite/gas/i386/avx10_2-256-1.d: Renamed to... * testsuite/gas/i386/avx10_2-256-media.d: ...this. * testsuite/gas/i386/avx10_2-256-1.s: Renamed to... * testsuite/gas/i386/avx10_2-256-media.s: ...this. * testsuite/gas/i386/avx10_2-512-1-intel.d: Renamed to... * testsuite/gas/i386/avx10_2-512-media-intel.d: ...this. * testsuite/gas/i386/avx10_2-512-1.d: Renamed to... * testsuite/gas/i386/avx10_2-512-media.d: ...this. * testsuite/gas/i386/avx10_2-512-1.s: Renamed to... * testsuite/gas/i386/avx10_2-512-media.s: ...this. * testsuite/gas/i386/x86-64-avx10_2-256-1-intel.d: Renamed to... * testsuite/gas/i386/x86-64-avx10_2-256-media-intel.d: ...this. * testsuite/gas/i386/x86-64-avx10_2-256-1.d: Renamed to... * testsuite/gas/i386/x86-64-avx10_2-256-media.d: ...this. * testsuite/gas/i386/x86-64-avx10_2-256-1.s: Renamed to... * testsuite/gas/i386/x86-64-avx10_2-256-media.s: ...this. * testsuite/gas/i386/x86-64-avx10_2-512-1-intel.d: Renamed to... * testsuite/gas/i386/x86-64-avx10_2-512-media-intel.d: ...this. * testsuite/gas/i386/x86-64-avx10_2-512-1.d: Renamed to... * testsuite/gas/i386/x86-64-avx10_2-512-media.d: ...this. * testsuite/gas/i386/x86-64-avx10_2-512-1.s: Renamed to... * testsuite/gas/i386/x86-64-avx10_2-512-media.s: ...this. * testsuite/gas/i386/i386.exp: Change testcase name. * testsuite/gas/i386/x86-64.exp: Ditto.
2024-10-14ia64/ELF: fix HPUX testsuite falloutJan Beulich3-13/+13
... from 1f1b5e506bf0 ("bfd/ELF: restrict file alignment for object files"), as noticed / reported by Alan.
2024-10-14LoongArch: Fixed R_LARCH_[32/64]_PCREL generation bugLulu Cai2-0/+18
The enum BFD_RELOC_[32/64] was mistakenly used in the macro instead of the relocation in fixp. This can cause the second relocation of a pair to be deleted when -mthin-add-sub is enabled. Apply the correct macro to fix this. Also sets the initial value of -mthin-add-sub.
2024-10-11bfd/ELF: restrict file alignment for object filesJan Beulich5-18/+18
While for executables properly aligning sections within the file can be quite relevant, the same is of pretty little importance for relocatable object files. Avoid passing "true" into _bfd_elf_assign_file_position_for_section() when dealing with object files, but compensate minimally by applying log_file_align in such cases as a cap to the alignment put in place.
2024-10-11Support Intel AVX10.2 media instructionsHaochen Jiang18-0/+1604
In disassembler part, for vnni instructions, we extended previous VEX part using %XE in disassembler to promote them to EVEX by reusing the original VEX table. For vmpsadbw, we will also use %XE. However, it is hard to reuse the VEX table, so we are using new ones. In assmbler part, we put the vnni table entries with previous vnni instructions since they are just promotion from AVX-VNNI-INT{8,16}. Since we will prefer VEX encoding, we need to use the different table order in template <vnni>, which prefers EVEX due to earlier introduction for AVX512_VNNI than AVX_VNNI. This means a new <vnni>. For vdpphps and vmpsadbw, we put them at the end of the table, with future AVX10.2 instructions. Nit: I will remove the arch requirement for avx_vnni_int{8,16} in evex-promote testcases after AVX10.2 implies AVX-VNNI-INT{8,16}. gas/Changelog: * testsuite/gas/i386/i386.exp: Add AVX10.2 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/avx10_2-256-1-intel.d: New. * testsuite/gas/i386/avx10_2-256-1.d: Ditto. * testsuite/gas/i386/avx10_2-256-1.s: Ditto. * testsuite/gas/i386/avx10_2-512-1-intel.d: Ditto. * testsuite/gas/i386/avx10_2-512-1.d: Ditto. * testsuite/gas/i386/avx10_2-512-1.s: Ditto. * testsuite/gas/i386/avx10_2-promote.d: Ditto. * testsuite/gas/i386/avx10_2-promote.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-1-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-1.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-1.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-1-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-1.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-1.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-promote.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-promote.s: Ditto. opcodes/Changelog: * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F3852. Add PREFIX_EVEX_0F3A42_W_0. * i386-dis-evex-w.h: Adjust EVEX_W_0F3A42. * i386-dis-evex.h: Add table pass for AVX10.2 instructions. * i386-dis.c: Adjust PREFIX_VEX_0F3850_W_0, PREFIX_VEX_0F3851_W_0, PREFIX_VEX_0F38D2_W_0 and PREFIX_VEX_0F38D3_W_0. * i386-opc.tbl: Add AVX10.2 instructions. * i386-mnem.h: Regenerated. * i386-tbl.h: Ditto. Co-authored-by: Lili Cui <lili.cui@intel.com>
2024-10-10s390: Add arch15 instructionsAndreas Krebbel3-0/+199
opcodes/ * s390-mkopc.c (main) Accept arch15 as CPU string. * s390-opc.txt: Add arch15 instructions. include/ * opcode/s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_ARCH15. gas/ * config/tc-s390.c (s390_parse_cpu): New entry for arch15. * doc/c-s390.texi: Document arch15 march option. * doc/as.texi: Likewise. * testsuite/gas/s390/s390.exp: Run the arch15 related tests. * testsuite/gas/s390/zarch-arch15.d: Tests for arch15 instructions. * testsuite/gas/s390/zarch-arch15.s: Likewise. Signed-off-by: Andreas Krebbel <krebbel@linux.ibm.com> Reviewed-by: Jens Remus <jremus@linux.ibm.com>
2024-10-08RISC-V: Fix implicit dependency of Zabha and ZacasXiao Zeng1-2/+2
1 Zabha depends on Zaamo: <https://github.com/riscv/riscv-isa-manual/blob/main/src/zabha.adoc> 2 Zacas depends on Zaamo: <https://github.com/riscv/riscv-isa-manual/blob/main/src/zacas.adoc> bfd/ChangeLog: * elfxx-riscv.c: Zabha and Zacas implicitly depend on Zaamo. gas/ChangeLog: * testsuite/gas/riscv/imply.d: Updated. Signed-off-by: Xiao Zeng <zengxiao@eswincomputing.com>
2024-09-27x86: fix Solaris gas testsuite runJan Beulich1-1/+9
Commits 8015b1b0c1a1 ("x86-64: Never make R_X86_64_GOT64 section relative"), d774bf9b3623 ("x86: Add tls check in gas"), and 1b714c14e40f ("x86: Turn PLT32 to PC32 only for PC-relative relocations") all should have adjusted the Solaris counterpart of the reloc64 test as well.
2024-09-27RISC-V: odd data padding vs mapping symbolsJan Beulich2-0/+25
Odd data padding has a $d label inserted at its beginning. When a $x... label is removed instead, a replacement is inserted after the padding. The same, however, needs to also happen when there's no $x to replace.
2024-09-27RISC-V: correct alignment directive handling for text sectionsJan Beulich4-0/+163
.insn or data emitted inside text sections can lead to positions not being at insn granularity. In such situations using alignment directives should reliably enforce the requested alignment. Specifically requests to align back to insn granularity may not be ignored (where, as a subcase thereof, the ordering of ".option norvc" and e.g. ".p2align 2" should not matter; so far the alignment directive needs to come first to have any effect). Similarly ahead of emitting NOPs alignment first needs to be forced back to insn granularity. The new testcases actually point out a corner case issue in the disassembler as well, which is being corrected at the same time: We don't want to print "0x" without any subsequent digits.
2024-09-27x86: optimize {,V}INSERTPS with certain immediatesJan Beulich9-0/+106
They are equivalent to simple moves or xors, which are up to 3 bytes shorter to encode (and maybe/likely also cheaper to execute).
2024-09-27x86: optimize {,V}EXTRACT{F,I}{128,32x{4,8},64x{2,4}} with immediate 0Jan Beulich8-0/+222
They, too, are equivalent to simple moves, which are up to 3 bytes shorter to encode (and maybe also cheaper to execute).
2024-09-27x86: optimize {,V}EXTRACTPS with immediate 0Jan Beulich9-0/+78
They are equivalent to simple moves, which are up to 2 bytes shorter to encode (and maybe also cheaper to execute).
2024-09-26x86/testsuite: Refine AVX10.2 rounding testcasesHaochen Jiang2-2/+3
Using hard byte code is not a good idea in dump file. Add a label for intel syntax test check to avoid that. gas/ChangeLog: * testsuite/gas/i386/avx10_2-rounding-intel.d: Use label for test split. * testsuite/gas/i386/avx10_2-rounding.s: Add label to avoid hard coding in dump file.
2024-09-25RISC-V: Add Smrnmi extension csrs.Jiawei8-0/+79
This patch support Smrnmi extension[1], The csrs address can be find in[2]. [1] https://github.com/riscv/riscv-isa-manual/commit/35eb3948bf0b87c83fab5a7238bd68b6211faf62 [2] https://github.com/riscv/riscv-isa-manual/blob/smrnmi-1.0/src/priv-csrs.adoc bfd/ChangeLog: * elfxx-riscv.c: New extension. gas/ChangeLog: * NEWS: Add Smrnmi extension support. * config/tc-riscv.c (enum riscv_csr_class): New extension class. (riscv_csr_address): Ditto. * testsuite/gas/riscv/csr-version-1p10.d: New csrs. * testsuite/gas/riscv/csr-version-1p10.l: Ditto. * testsuite/gas/riscv/csr-version-1p11.d: Ditto. * testsuite/gas/riscv/csr-version-1p11.l: Ditto. * testsuite/gas/riscv/csr-version-1p12.d: Ditto. * testsuite/gas/riscv/csr-version-1p12.l: Ditto. * testsuite/gas/riscv/csr.s: Ditto. * testsuite/gas/riscv/march-help.l: New extension. include/ChangeLog: * opcode/riscv-opc.h (CSR_MNSCRATCH): New csr. (CSR_MNEPC): Ditto. (CSR_MNCAUSE): Ditto. (CSR_MNSTATUS): Ditto. (DECLARE_CSR): New csr declarations.
2024-09-23x86: Turn PLT32 to PC32 only for PC-relative relocationsH.J. Lu4-0/+11
commit 292676c15a615b5a95bede9ee91004d3f7ee7dfd Author: H.J. Lu <hjl.tools@gmail.com> Date: Thu Feb 13 13:44:17 2020 -0800 x86: Resolve PLT32 reloc aganst local symbol to section resolved PLT32 relocation against local symbol to section and commit 2585b7a5ce5830e60a089aa2316a329558902f0c Author: H.J. Lu <hjl.tools@gmail.com> Date: Sun Jul 19 06:51:19 2020 -0700 x86: Change PLT32 reloc against section to PC32 turned PLT32 relocation against section into PC32 relocation. But these transformations are valid only for PC-relative relocations. Add fx_pcrel check for PC-relative relocations when performing these transformations to keep PLT32 relocation in `movq $foo@PLT, %rax`. gas/ PR gas/32196 * config/tc-i386.c (tc_i386_fix_adjustable): Return fixP->fx_pcrel for PLT32 relocations. (i386_validate_fix): Turn PLT32 relocation into PC32 relocation only if fixp->fx_pcrel is set. * testsuite/gas/i386/reloc32.d: Updated. * testsuite/gas/i386/reloc64.d: Likewise. * testsuite/gas/i386/reloc32.s: Add PR gas/32196 test. * testsuite/gas/i386/reloc64.s: Likewise. ld/ PR gas/32196 * testsuite/ld-x86-64/plt3.s: New file. * testsuite/ld-x86-64/x86-64.exp: Run plt3. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-09-21x86: Add tls check in gasCui, Lili18-8/+395
Assembler shouldn't accept invalid TLS instructions, TLS relocations can only be used with specific instructions as specified in TLS psABI and linker issues an error when TLS relocations are used with wrong instructions or format. Since it is inconvenient for gcc to rely on linker to report errors, adding TLS check in the assembler stage so that gcc can know TLS errors earlier. gas/ChangeLog: PR gas/32022 * config.in: Regenerate. * config/tc-i386.c *(enum x86_tls_error_type): New. *(struct _i386_insn): Added has_gotrel to indicate whether TLS relocations need to be checked. (x86_check_tls_relocation): Added a new function to check TLS relocation. (x86_report_tls_error): Created a new function to report TLS error. (i386_assemble): Handle x86_check_tls_relocation. (lex_got): Set i.has_gotrel. (OPTION_MTLS_CHECK): Added a new option to contrl TLS check. (struct option): Ditto. (md_parse_option): Ditto. (md_show_usage): Ditto. * configure.ac: Added a new option to check TLS relocation by default. * configure: Regenerated. * doc/c-i386.texi: Document -mtls-check=. * testsuite/gas/i386/i386.exp: Added new tests. * testsuite/gas/i386/ilp32/ilp32.exp: Ditto. * testsuite/gas/i386/ilp32/reloc64.d: Disable TLS check for it. * testsuite/gas/i386/ilp32/x32-tls.d: Ditto. * testsuite/gas/i386/inval-tls.l: Added more test cases. * testsuite/gas/i386/inval-tls.s: Ditto. * testsuite/gas/i386/reloc32.d: Disable TLS check for it. * testsuite/gas/i386/reloc64.d: Ditto. * testsuite/gas/i386/x86-64-inval-tls.l: Added more test cases. * testsuite/gas/i386/x86-64-inval-tls.s: Ditto. * testsuite/gas/i386/x86-64.exp: Added new tests. * testsuite/gas/i386/ilp32/x32-inval-tls.l: New test. * testsuite/gas/i386/ilp32/x32-inval-tls.s: Ditto. * testsuite/gas/i386/ilp32/x86-64-tls.d: Ditto. * testsuite/gas/i386/tls.d: Ditto. * testsuite/gas/i386/tls.s: Ditto. * testsuite/gas/i386/x86-64-tls.d: Ditto. * testsuite/gas/i386/x86-64-tls.s: Ditto. ld/ChangeLog: PR gas/32022 * testsuite/ld-i386/tlsgdesc1.d: Disable TLS check for it. * testsuite/ld-i386/tlsgdesc2.d: Ditto. * testsuite/ld-i386/tlsie2.d: Ditto. * testsuite/ld-i386/tlsie3.d: Ditto. * testsuite/ld-i386/tlsie4.d: Ditto. * testsuite/ld-i386/tlsie5.d: Ditto. * testsuite/ld-i386/tlsgdesc3.d: Ditto. * testsuite/ld-x86-64/tlsdesc3.d: Ditto. * testsuite/ld-x86-64/tlsdesc4.d: Ditto. * testsuite/ld-x86-64/tlsie2.d: Ditto. * testsuite/ld-x86-64/tlsie3.d: Ditto. * testsuite/ld-x86-64/tlsie5.d: Ditto. * testsuite/ld-x86-64/tlsdesc5.d: Ditto.
2024-09-20x86-64: Never make R_X86_64_GOT64 section relativeH.J. Lu2-0/+16
R_X86_64_GOT64 relocation should never be made section relative. Change tc_i386_fix_adjustable to return 0 for BFD_RELOC_X86_64_GOT64. gas/ PR gas/32189 * config/tc-i386.c (tc_i386_fix_adjustable): Return 0 for BFD_RELOC_X86_64_GOT64. * testsuite/gas/i386/reloc64.d: Updated. * testsuite/gas/i386/reloc64.s: Add more tests for R_X86_64_GOT64 and R_X86_64_GOTOFF64. ld/ PR gas/32189 * testsuite/ld-x86-64/x86-64.exp: Run PR gas/32189 test. * testsuite/ld-x86-64/pr32189.s: New file. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-09-18x86/APX: Don't promote AVX/AVX2 instructions out of APX specH.J. Lu7-44/+18
V{BROADCAST,EXTRACT,INSERT}{F,I}128 and VROUND{P,S}{S,D} aren't promoted to support EGPR in APX spec. Don't promote them out of APX spec. This commit effectively reverted: ec3babb8c10 x86/APX: V{BROADCAST,EXTRACT,INSERT}{F,I}128 can also be expressed 5a635f1f59a x86/APX: VROUND{P,S}{S,D} encodings require AVX512{F,VL} eea4357967b x86/APX: VROUND{P,S}{S,D} can generally be encoded gas/ PR gas/32171 * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.s: Add V{BROADCAST,EXTRACT,INSERT}{F,I}128 tests with EGPR. * testsuite/gas/i386/x86-64-apx-evex-promoted.s: Remove V{BROADCAST,EXTRACT,INSERT}{F,I}128 and VROUND{P,S}{S,D} tests with EGPR. * testsuite/gas/i386/x86-64-apx-egpr-inval.l: Updated. * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.l: Likewise. * testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: Likewise. * testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d: Likewise. * testsuite/gas/i386/x86-64-apx-evex-promoted.d: Likewise. opcodes/ PR gas/32171 * i386-opc.tbl: Remove V{BROADCAST,EXTRACT,INSERT}{F,I}128 and VROUND{P,S}{S,D} entries with EGPR. * i386-tbl.h: Regenerated. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-09-15MIPS/GAS: Discard redundant instruction from DDIV/DREM macrosMaciej W. Rozycki11-25/+4
A sequence such as: li at,-1 bne xx,at,0f li at,1 dsll32 at,at,0x1f is produced in the expansion of the DDIV and DREM assembly macros, where a redundant `li at,1' instruction is used to load an intermediate value of 1 into $at, which is then left-shifted by 63 with `dsll32 at,at,0x1f' yielding 0x8000000000000000. However this value likewise results from left-shifting the value of -1, already present in $at at this point. Remove the extraneous instruction then, shortening the sequence emitted. Adjust dumps in the testsuite accordingly.
2024-09-15MIPS/GAS/testsuite: Print instructions in hex in division testsMaciej W. Rozycki21-241/+249
Add `--show-raw-insn' to division tests so as to verify branch offsets without the need to know actual offsets into the text section individual instructions have been assembled at. Add `-z' where applicable to make interlock NOP instructions appear in output so as to verify them without the need to know the offsets too. Replace individual offsets to match against with generic patterns so that a change in the expansion of an assembly macro does not affect code that follows.
2024-09-12s390: Relax risbg[n]z, risb{h|l}gz, {rns|ros|rxs}bgt operand constraintsJens Remus2-12/+12
This leverages commit ("s390: Simplify (dis)assembly of insn operands with const bits") to relax the operand constraints of the immediate operand that contains the constant Z- or T-bit of the following extended mnemonics: risbgz, risbgnz, risbhgz, risblgz, rnsbgt, rosbgt, rxsbgt Previously those instructions were the only ones where the assembler on s390 restricted the specification of the subject I3/I4 operand values exactly according to their specification to an unsigned 6- or 5-bit unsigned integer. For any other instructions the assembler allows to specify any operand value allowed by the instruction format, regardless of whether the instruction specification is more restrictive. Allow to specify the subject I3/I4 operand as unsigned 8-bit integer with the constant operand bits being ORed during assembly. Relax the instructions subject significant operand bit masks to only consider the Z/T-bit as significant, so that the instructions get disassembled as their *z or *t flavor regardless of whether any reserved bits are set in addition to the Z/T-bit. Adapt the rnsbg, rosbg, and rxsbg test cases not to inadvertently set the T-bit in operand I3, as they otherwise get disassembled as their rnsbgt, rosbgt, and rxsbgt counterpart. This aligns GNU Assembler to LLVM Assembler. opcodes/ * s390-opc.c (U6_18, U5_27, U6_26): Remove. (INSTR_RIE_RRUUU2, INSTR_RIE_RRUUU3, INSTR_RIE_RRUUU4): Define as INSTR_RIE_RRUUU while retaining insn fmt mask. (MASK_RIE_RRUUU2, MASK_RIE_RRUUU3, MASK_RIE_RRUUU4): Treat only Z/T-bit of I3/I4 operand as significant. gas/testsuite/ * gas/s390/zarch-z10.s (rnsbg, rosbg, rxsbg): Do not set T-bit. Reported-by: Dominik Steenken <dost@de.ibm.com> Suggested-by: Ulrich Weigand <ulrich.weigand@de.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-09-11gas: avoid (scrubber) diagnostics for stuff past .endJan Beulich5-0/+52
What's past an active .end directive (when that has its default purpose) is supposed to be entirely ignored. That should be true not just for regular processing, but also for "pre-processing" (aka scrubbing). A complication is that such a directive may of course occur inside a (false) conditional or a macro definition. To deal with that make sure we can continue as usual if called another time. Note however that .end inside a macro will still have the full macro body expanded; dealing with that would require further (perhaps intrusive) adjustments in sb_scrub_and_add_sb() and/or callers thereof. However, at least some of the warnings issued by do_scrub_chars() are unlikely to occur when expanding a macro. (If we needed to go that far, presumably .exitm would also want recognizing.)
2024-09-11arm: don't engage symver scrubber hack in CCS modeJan Beulich2-0/+17
In that mode the comment char is ; while @ has no special meaning. Engaging the special logic in that case results in comments not being respected on .symver lines.
2024-09-09LoongArch: Fixed precedence of expression operators in instructionsLulu Cai2-0/+11
The precedence of the operators "+" and "-" in the current loongarch instruction expression is higher than "<<" and ">>", which is different from the explanation in the user guide. We modified the precedence of "<<" and ">>" to be higher than "+" and "-".
2024-09-07Add macros to get opcode of instructions approriatelyXin Wang1-104/+104
LoongArch: Add macros to get opcode and register of instructions appropriately Currently, we get opcode of an instruction by manipulate the binary with it's mask, it's a bit of a pain. Now a macro is defined to do this and a macro to get the RD and RJ registers which is applicable to most instructions of LoongArch are added.
2024-09-06x86/APX: optimize certain reg-only CFCMOVcc formsJan Beulich2-0/+20
Along the lines of 2513312930b2 ("x86/APX: apply NDD-to-legacy transformation to further CMOVcc forms") these can similarly be converted to the shorter legacy-encoded CMOVcc.
2024-09-03RISC-V: Add support for XCVsimd extension in CV32E40PMary Bennett6-0/+4175
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett682@gmail.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvsimd` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * NEWS: Updated. * config/tc-riscv.c (validate_riscv_insn): Add custom operands. (riscv_ip): Likewise. * doc/c-riscv.texi: Note XCVsimd as an additional ISA extension for CORE-V. * testsuite/gas/riscv/march-help.l: Add xcvsimd. * testsuite/gas/riscv/x-cv-simd.d: New test. * testsuite/gas/riscv/x-cv-simd.s: New test. * testsuite/gas/riscv/x-cv-simd-fail.d: New test. * testsuite/gas/riscv/x-cv-simd-fail.l: New test. * testsuite/gas/riscv/x-cv-simd-fail.s: New test. include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK macros for XCVsimd. * opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVsimd. (enum riscv_insn_class): Add the XCVsimd instruction class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add custom operands. * riscv-opc.c: Add XCVsimd instructions.
2024-09-02Support ymm rounding control for Intel AVX10.2Haochen Jiang10-0/+2583
In the patch, in order to support ymm rounding for AVX10.2, we derive evex attribute for all cases instead of only for rc_none to encode U bit. Also changed some bad_opcode return due to the share of U bit with APX_F. gas/ChangeLog: * config/tc-i386.c (cpu_flags_match): Handle AVX10_2. (build_evex_prefix): Handle U bit. Derive evex attribute for all cases. (check_VecOperands): Handle AVX10.2 and ymm roundings. * doc/c-i386.texi: Document .avx10.2. * testsuite/gas/i386/i386.exp: Run AVX10.2 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/avx10_2-rounding-intel.d: New test. * testsuite/gas/i386/avx10_2-rounding-inval.l: Ditto. * testsuite/gas/i386/avx10_2-rounding-inval.s: Ditto. * testsuite/gas/i386/avx10_2-rounding.d: Ditto. * testsuite/gas/i386/avx10_2-rounding.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-rounding-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-rounding.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-rounding.s: Ditto. opcodes/ChangeLog: * i386-dis.c (struct instr_info): Add U bit. (get_valid_dis386): Handle U bit. * i386-gen.c (isa_dependencies): Add AVX10.2. (cpu_flags): Ditto. * i386-init.h: Regenerated. * i386-opc.h (CpuAVX10_2): New. (i386_cpu_flags): Add cpuavx10_2. * i386-opc.tbl: Add rounding to old entries which do not permit rounding previously. Also eliminate the redundant RegXMM for vcvtps2uqq. * i386-tbl.h: Regenerated.
2024-08-30gas: generated code/data listing output vs .endr and alikeJan Beulich2-0/+9
These ending directives are swallowed by buffer_and_nest() and hence aren't seen by read_a_source_file(). Thus they also weren't announced to the listing subsystem. That was, when macro expansions are included, thus misguided to associate possible output resulting from the first line of the construct being expanded with both the .endr and that first line (i.e. showing it twice).
generated by cgit v1.1 at 2024-11-26 00:05:22 +0000