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2024-02-06x86: Warn .insn instruction with length > 15 bytesH.J. Lu2-0/+11
Change .insn instruction with length > 15 bytes from error to warning. PR gas/31323 * config/tc-i386.c (output_insn): Issue a warning when .insn instruction length exceeds the limit of 15 bytes. * testsuite/gas/i386/oversized64.s: Add a test for .insn * testsuite/gas/i386/oversized64.l: Updated.
2024-02-04LoongArch: gas: Fix the types of symbols referred with %le_*_r in the symtabXi Ruoyao2-0/+9
When a symbol is referred with %le_{hi20,lo12,add}_r, it's definitely a TLS symbol and we should set its type to TLS in the symtab. Otherwise when building Perl with gcc-14 -flto, we get: /usr/bin/ld: PL_current_context: TLS definition in ./miniperl.ltrans0.ltrans.o section .tbss mismatches non-TLS reference in ./miniperl.ltrans1.ltrans.o A minimal reproducer: $ cat t1.s .section .tbss .globl x x: .word 0 $ cat t2.s f: lu12i.w $a0, %le_hi20_r(x) add.d $a0, $a0, $tp, %le_add_r(x) li.w $a1, 1 st.w $a1, $a0, %le_lo12_r(x) $ gas/as-new t1.s -o t1.o $ gas/as-new t2.s -o t2.o $ ld/ld-new t1.o t2.o ld/ld-new: x: TLS definition in t1.o section .tbss mismatches non-TLS reference in t2.o Unfortunately this was undetected before Binutils-2.42 release because GCC < 14 does not use %le_*_r, and without LTO it's very rare to have a TLS LE definition and its reference in two different translation units. So this fix should be backported to Binutils-2.42 branch too. Signed-off-by: Xi Ruoyao <xry111@xry111.site>
2024-02-02x86: Disallow instructions with length > 15 bytesH.J. Lu5-30/+38
It is a hard error when an instruction length exceeds the limit of 15 bytes: [hjl@gnu-cfl-3 tmp]$ cat x.s .text xacquire lock addq $0x11223344, %fs:(,%eax) [hjl@gnu-cfl-3 tmp]$ gcc -c x.s x.s: Assembler messages: x.s:2: Warning: instruction length of 16 bytes exceeds the limit of 15 [hjl@gnu-cfl-3 tmp]$ objdump -dw x.o x.o: file format elf64-x86-64 Disassembly of section .text: 0000000000000000 <.text>: 0: 64 67 f2 f0 48 81 04 05 00 00 00 00 44 33 22 xacquire lock (bad) f: 11 .byte 0x11 [hjl@gnu-cfl-3 tmp]$ and [hjl@gnu-cfl-3 tmp]$ cat z.s addq $0xe0, %fs:0, %rdx [hjl@gnu-cfl-3 tmp]$ as -o z.o z.s z.s: Assembler messages: z.s:1: Warning: instruction length of 16 bytes exceeds the limit of 15 [hjl@gnu-cfl-3 tmp]$ objdump -dw z.o z.o: file format elf64-x86-64 Disassembly of section .text: 0000000000000000 <.text>: 0: 64 62 f4 ec 18 81 04 25 00 00 00 00 e0 00 00 (bad) ... [hjl@gnu-cfl-3 pr31323]$ Instructions with length > 15 bytes are always invalid. It is quite easy to generate invalid instructions with AVX now. We should issue an error when instruction length exceeds the limit of 15 bytes. PR gas/31323 * config/tc-i386.c (output_insn): Issue an error when instruction length exceeds the limit of 15 bytes. * testsuite/gas/i386/oversized16.l: Updated. * testsuite/gas/i386/oversized64.l: Likewise. * testsuite/gas/i386/x86-64-apx-inval.l: New file. * testsuite/gas/i386/x86-64-apx-inval.s: Likewise.
2024-02-02x86: actually implement .nooptJan Beulich5-18/+33
For quite some time we've had support for -O command line options. With that ignoring at least .noopt isn't really a good idea. Re-purpose the optimize-3 test for testing this directive's effect as well. As to the doc addition - this uses the same text as is there for the {nooptimize} pseudo-prefix, despite me not being convinced of the "size" part being fully accurate there (and hence also here).
2024-02-01gas: x86: ginsn: adjust ginsns for certain lea opsIndu Bhagat3-0/+77
A review comment on the SCFI V4 series was to handle ginsn creation for certain lea opcodes more precisely. Specifically, we should preferably handle the following two cases of lea opcodes similarly: - #1 lea with "index register and scale factor of 1, but no base register", - #2 lea with "no index register, but base register present". Currently, a ginsn of type GINSN_TYPE_OTHER is generated for the case of #1 above. For #2, however, the lea insn is translated to either a GINSN_TYPE_ADD or GINSN_TYPE_MOV depending on whether the immediate for displacement is non-zero or not respectively. Change the handling in x86_ginsn_lea so that both of the above lea manifestations are handled similarly. While at it, remove the code paths creating GINSN_TYPE_OTHER altogether from the function. It makes sense to piggy back on the x86_ginsn_unhandled code path to create GINSN_TYPE_OTHER if the destination register is interesting. This was also suggested in one of the previous review rounds; the other functions already follow that model, so this keeps functions symmetrical looking. gas/ * gas/config/tc-i386.c (x86_ginsn_lea): Handle select lea ops with no base register similar to the case of no index register. Remove creation of GINSN_TYPE_OTHER from the function. gas/testsuite/ * gas/scfi/x86_64/ginsn-lea-1.l: New test. * gas/scfi/x86_64/ginsn-lea-1.s: Likewise. * gas/scfi/x86_64/scfi-x86-64.exp: Add new test.
2024-01-29bpf: there is no ldinddw nor ldabsdw instructionsJose E. Marchesi6-97/+82
There are no legacy ldind nor ldabs BPF instructions with BPF_SIZE_DW. For some reason we were (incorrectly) supporting these. This patch updates the opcodes so the instructions get removed and modifies the GAS manual and testsuite accordingly. See discussion at https://lore.kernel.org/bpf/110aad7a-f8a3-46ed-9fda-2f8ee54dcb89@linux.dev Tested in bpf-uknonwn-none target, x86-64-linux-gnu host. include/ChangeLog: 2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/bpf.h (enum bpf_insn_id): Remove BPF_INSN_LDINDDW and BPF_INSN_LDABSDW instructions. opcodes/ChangeLog: 2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Remove BPF_INSN_LDINDDW and BPF_INSN_LDABSDW instructions. gas/ChangeLog: 2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com> * doc/c-bpf.texi (BPF Instructions): There is no indirect 64-bit load instruction. (BPF Instructions): There is no absolute 64-bit load instruction. * testsuite/gas/bpf/mem.s: Update test accordingly. * testsuite/gas/bpf/mem-be-pseudoc.d: Likewise. * testsuite/gas/bpf/mem-be.d: Likewise. * testsuite/gas/bpf/mem-pseudoc.d: Likewise. * testsuite/gas/bpf/mem-pseudoc.s: Likewise. * testsuite/gas/bpf/mem.d: Likewise. * testsuite/gas/bpf/mem.s: Likewise.
2024-01-26gas: scfi: untraceable control flow should be a hard errorIndu Bhagat2-9/+11
PR gas/31284 Currently, if an indirect jump is seen, GCFG (a CFG of ginsns) cannot be created, and the SCFI machinery bails out with a warning: "Warning: Untraceable control flow for func 'foo'; Skipping SCFI" It is, however, better suited if this is a hard error. Change it to a hard error. Also change the message to skip mentioning "SCFI", because the error itself may also useful when ginsns are used for other passes (distinct from SCFI) involving GCFG, like a pass to detect if there is unreachable code. Hence, simply say: "Error: untraceable control flow for func 'foo'" gas/ PR gas/31284 * ginsn.c (ginsn_data_end): Use as_bad instead of as_warn. gas/testsuite/ PR gas/31284 * gas/scfi/x86_64/ginsn-cofi-1.l: Adjust to the expected output in case of errors. * gas/scfi/x86_64/scfi-unsupported-cfg-1.l: Error not Warning.
2024-01-26x86: testsuite: scfi: adjust COFI testcaseIndu Bhagat5-14/+37
The testcase for change of flow instructions in its current shape is not doing much: it checks that SCFI issues an appropriate warning. The same warning is covered by another testcase (scfi-unsupported-cfg-1); It is better to test the ginsn translation instead, for these 'change of flow instructions'. gas/testsuite/ * gas/scfi/x86_64/scfi-cofi-1.s: Moved to... * gas/scfi/x86_64/ginsn-cofi-1.s: ...here. * gas/scfi/x86_64/scfi-x86-64.exp: Adjust tests. * gas/scfi/x86_64/scfi-cofi-1.d: Removed. * gas/scfi/x86_64/scfi-cofi-1.l: Removed. * gas/scfi/x86_64/ginsn-cofi-1.l: New test.
2024-01-26x86: make "-msyntax=intel -mnaked-reg" match ".intel_syntax noprefix"Jan Beulich5-3/+12
Adjustments made for the directive (by set_intel_syntax()) need also making for the command line option. Break out respective code into a new helper function, to also be invoked during command line processing. Further also set register_prefix when processing -mnaked-reg.
2024-01-26x86/APX: optimize MOVBEJan Beulich2-0/+6
With identical source and destination it can be covered by the NDD-to- legacy conversion logic as well, even if in this case the original insn doesn't use an NDD encoding. The size savings are even better here, for the replacement (BSWAP) not having a ModR/M byte.
2024-01-26LoongArch: gas: Add support for s9 registermengqinggang3-0/+4
In LoongArch ABI, r22 register can be used as frame pointer or static register(s9). Link: https://github.com/loongson/la-abi-specs/blob/release/lapcs.adoc#general-purpose-registers
2024-01-24LoongArch: gas: Start a new frag after instructions that can be relaxedmengqinggang2-0/+79
For R_LARCH_TLS_{LE_HI20_R,LE_ADD_R,LD_PC_HI20,GD_PC_HI20, DESC_PC_HI20} relocations, start a new frag to get correct eh_frame Call Frame Information FDE DW_CFA_advance_loc info.
2024-01-24LoongArch: gas: Don't define LoongArch .alignmengqinggang3-0/+7
Gcc may generate "\t.align\t%d,54525952,4\n" before commit b20c7ee066cb7d952fa193972e8bc6362c6e4063. To write 54525952 (NOP) to object file, we call s_align_ptwo (-4). It result in alignment padding must be a multiple of 4 if .align has second parameter. Use default s_align_ptwo for .align.
2024-01-22LoongArch: Use tab to indent assembly in TLSDESC test suiteTatsuyuki Ishi2-2/+2
The usual convention is to use tabs. Not all test are following this, but at least when using tabs, let's use it consistently throughout the file.
2024-01-22x86/APX: also amend the PUSH2/POP2 testcaseJan Beulich2-0/+2
Commit f530d5f1bab6 ("Update x86/APX: VROUND{P,S}{S,D} can generally be encoded") took care of only half of the remaining issue. Add #pass here as well.
2024-01-21LoongArch: Do not emit R_LARCH_RELAX for two register macrosmengqinggang2-111/+98
For two register macros (e.g. la.local $t0, $t1, symbol) used in extreme code model, do not emit R_LARCH_RELAX relocations.
2024-01-19Update x86/APX: VROUND{P,S}{S,D} can generally be encodedH.J. Lu2-0/+2
Append "#pass" to APX tests for targets which pad text sections with NOPs. * testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: Append "#pass". * testsuite/gas/i386/x86-64-apx-evex-promoted.d: Likewise.
2024-01-19x86/APX: VROUND{P,S}{S,D} can generally be encodedJan Beulich5-8/+20
VRNDSCALE{P,S}{S,D} is the AVX512 generalization of these AVX insns. As long as the immediate has the top 4 bits clear, they are equivalent to the earlier VEX-encoded insns, and hence can be used to permit use of eGPR-s in the memory operand. Since this is the normal way of using these insns, also alter the resulting diagnostic to complain about the immediate, not the eGPR use.
2024-01-19x86/APX: be consistent with insn suffixesJan Beulich1-43/+43
When there's a suitably disambiguating register operand, suffixes are generally omitted (unless in suffix-always mode). All NDD insns have a suitable register operand, so they shouldn't have suffixes by default.
2024-01-19x86: support APX forms of U{RD,WR}MSRJan Beulich3-0/+20
This was missed in 6177c84d5edc ("Support APX GPR32 with extend evex prefix").
2024-01-15x86-64: Skip SCFI tests for x32 targetsH.J. Lu1-1/+1
Since SCFI isn't supported on x32: Fatal error: SCFI is not supported for this ABI skip SCFI tests for x32 targets. PR gas/31245 * testsuite/gas/scfi/x86_64/scfi-x86-64.exp: Skip for x32 targets.
2024-01-15aarch64: rcpc3: Add FP load/store insnsVictor Do Nascimento5-0/+90
Along with the relevant unit-tests, this adds the following rcpc3 instructions: STL1 { <Vt>.D }[<index>], [<Xn|SP>] LDAP1 { <Vt>.D }[<index>], [<Xn|SP>] LDAPUR <Bt>, [<Xn|SP>{, #<simm>}] LDAPUR <Ht>, [<Xn|SP>{, #<simm>}] LDAPUR <St>, [<Xn|SP>{, #<simm>}] LDAPUR <Dt>, [<Xn|SP>{, #<simm>}] LDAPUR <Qt>, [<Xn|SP>{, #<simm>}] STLUR <Bt>, [<Xn|SP>{, #<simm>}] STLUR <Ht>, [<Xn|SP>{, #<simm>}] STLUR <St>, [<Xn|SP>{, #<simm>}] STLUR <Dt>, [<Xn|SP>{, #<simm>}] STLUR <Qt>, [<Xn|SP>{, #<simm>}] with `#<simm>' taking on a signed 8-bit integer value in the range [-256,255] and `index' the values 0 or 1. Co-authored-by: Srinath Parvathaneni <srinath.parvathaneni@arm.com>
2024-01-15aarch64: rcpc3: Add integer load/store insnsVictor Do Nascimento6-2/+65
Along with the relevant unit tests and updates to the existing regression tests, this adds support for the following novel rcpc3 insns: LDIAPP <Wt1>, <Wt2>, [<Xn|SP>] LDIAPP <Wt1>, <Wt2>, [<Xn|SP>], #8 LDIAPP <Xt1>, <Xt2>, [<Xn|SP>] LDIAPP <Xt1>, <Xt2>, [<Xn|SP>], #16 STILP <Wt1>, <Wt2>, [<Xn|SP>] STILP <Wt1>, <Wt2>, [<Xn|SP>, #-8]! STILP <Xt1>, <Xt2>, [<Xn|SP>] STILP <Xt1>, <Xt2>, [<Xn|SP>, #-16]! LDAPR <Wt>, [<Xn|SP>], #4 LDAPR <Xt>, [<Xn|SP>], #8 STLR <Wt>, [<Xn|SP>, #-4]! STLR <Xt>, [<Xn|SP>, #-8]!
2024-01-15aarch64: Fix tlbi and tlbip instructionsAndrew Carlotti8-142/+231
There are some tlbi operations that don't have a corresponding tlbip operation, but we were incorrectly using the same list for both. Add the missing tlbi *nxs operations, and use the F_REG_128 flag to filter tlbi operations that don't have a tlbip analogue. For increased clarity, I have also used a macro to reduce duplication between the 'nxs' and non-'nxs' variants, and added a test to verify that no invalid combinations are accepted. Additionally, fix two missing checks for AARCH64_OPND_SYSREG_TLBIP that were preventing disassembly of tlbip instructions.
2024-01-15aarch64: Add SVE2.1 Contiguous load/store instructions.Srinath Parvathaneni3-0/+43
Hi, This patch add support for SVE2.1 instructions ld1q, ld2q, ld3q and ld4q, st1q, st2q, st3q and st4q. Regression testing for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath.
2024-01-15PATCH 5/6][Binutils] aarch64: Add SVE2.1 fmin and fmax instructions.Srinath Parvathaneni3-0/+79
Hi, This patch add support for SVE2.1 instruction faddqv, fmaxnmqv, fmaxqv, fminnmqv and fminqv. Regression testing for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath.
2024-01-15aarch64: Add SVE2.1 dupq, eorqv and extq instructions.Srinath Parvathaneni3-0/+62
Hi, This patch add support for SVE2.1 instruction dupq, eorqv and extq. Regression testing for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath.
2024-01-15aarch64: Add support for FEAT_SVE2p1.Srinath Parvathaneni4-0/+128
Hi, This patch add support for FEAT_SVE2p1 (SVE2.1 Extension) feature along with +sve2p1 optional flag to enabe this feature. Also support for following SVE2p1 instructions is added addqv, andqv, smaxqv, sminqv, umaxqv, uminqv and uminqv. Regression testing for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath.
2024-01-15aarch64: Add support for FEAT_SME2p1 instructions.Srinath Parvathaneni2-0/+81
Hi, This patch add support for FEAT_SME2p1 and "movaz" instructions along with the optional flag +sme2p1. Following "movaz" instructions are add: Move and zero two ZA tile slices to vector registers. Move and zero four ZA tile slices to vector registers. Regression testing for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath.
2024-01-15aarch64: Add support for FEAT_B16B16 instructions.Srinath Parvathaneni4-0/+319
Hi, This patch add support for SVE2.1 and SME2.1 non-widening BFloat16 (FEAT_B16B16) instructions. Following instructions predicated, unpredicated and indexed variants are added in this patch. bfadd, bfclamp, bfmax bfmaxnm, bfmin,bfminnm, bfmla,bfmls,bfmul and bfsub. Regression testing for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath.
2024-01-15gas: testsuite: add an x86 testsuite for SCFIIndu Bhagat129-0/+3074
The testsuite for SCFI contains target-specific tests. When a test is executed with --scfi=experimental command line option, the CFI annotations in the test .s files are skipped altogether by the GAS for processing. The CFI directives in the input assembly files are, however, validated by running the assembler one more time without --scfi=experimental. Some testcases are used to highlight those asm constructs that the SCFI machinery in GAS currently does not support: - Only System V AMD64 ABI is supported for now. Using either --32 or --x32 with SCFI results in hard error. See scfi-unsupported-1.s. - Untraceable stack-pointer manipulation in function epilougue and prologue. See scfi-unsupported-2.s. - Using Dynamically Realigned Arguement Pointer (DRAP) register to realign the stack. For SCFI, the CFA must be only REG_SP or REG_FP based. See scfi-unsupported-drap-1.s Some testcases are used to highlight some diagnostics that the SCFI machinery in GAS currently issues, with an intent to help user correct inadvertent errors in their hand-written asm. An error is issued when GAS finds that input asm is not amenable to correct CFI synthesis. - (#1) "Warning: SCFI: Asymetrical register restore" - (#2) "Error: SCFI: usage of REG_FP as scratch not supported" - (#3) "Error: SCFI: unsupported stack manipulation pattern" In case of (#2) and (#3), SCFI generation is skipped for the respective function. Above is a subset of the warnings/errors implemented in the code. gas/testsuite/: * gas/scfi/README: New test. * gas/scfi/x86_64/ginsn-add-1.l: New test. * gas/scfi/x86_64/ginsn-add-1.s: New test. * gas/scfi/x86_64/ginsn-dw2-regnum-1.l: New test. * gas/scfi/x86_64/ginsn-dw2-regnum-1.s: New test. * gas/scfi/x86_64/ginsn-pop-1.l: New test. * gas/scfi/x86_64/ginsn-pop-1.s: New test. * gas/scfi/x86_64/ginsn-push-1.l: New test. * gas/scfi/x86_64/ginsn-push-1.s: New test. * gas/scfi/x86_64/scfi-add-1.d: New test. * gas/scfi/x86_64/scfi-add-1.l: New test. * gas/scfi/x86_64/scfi-add-1.s: New test. * gas/scfi/x86_64/scfi-add-2.d: New test. * gas/scfi/x86_64/scfi-add-2.l: New test. * gas/scfi/x86_64/scfi-add-2.s: New test. * gas/scfi/x86_64/scfi-asm-marker-1.d: New test. * gas/scfi/x86_64/scfi-asm-marker-1.l: New test. * gas/scfi/x86_64/scfi-asm-marker-1.s: New test. * gas/scfi/x86_64/scfi-asm-marker-2.d: New test. * gas/scfi/x86_64/scfi-asm-marker-2.l: New test. * gas/scfi/x86_64/scfi-asm-marker-2.s: New test. * gas/scfi/x86_64/scfi-asm-marker-3.d: New test. * gas/scfi/x86_64/scfi-asm-marker-3.l: New test. * gas/scfi/x86_64/scfi-asm-marker-3.s: New test. * gas/scfi/x86_64/scfi-bp-sp-1.d: New test. * gas/scfi/x86_64/scfi-bp-sp-1.l: New test. * gas/scfi/x86_64/scfi-bp-sp-1.s: New test. * gas/scfi/x86_64/scfi-bp-sp-2.d: New test. * gas/scfi/x86_64/scfi-bp-sp-2.l: New test. * gas/scfi/x86_64/scfi-bp-sp-2.s: New test. * gas/scfi/x86_64/scfi-callee-saved-1.d: New test. * gas/scfi/x86_64/scfi-callee-saved-1.l: New test. * gas/scfi/x86_64/scfi-callee-saved-1.s: New test. * gas/scfi/x86_64/scfi-callee-saved-2.d: New test. * gas/scfi/x86_64/scfi-callee-saved-2.l: New test. * gas/scfi/x86_64/scfi-callee-saved-2.s: New test. * gas/scfi/x86_64/scfi-callee-saved-3.d: New test. * gas/scfi/x86_64/scfi-callee-saved-3.l: New test. * gas/scfi/x86_64/scfi-callee-saved-3.s: New test. * gas/scfi/x86_64/scfi-callee-saved-4.d: New test. * gas/scfi/x86_64/scfi-callee-saved-4.l: New test. * gas/scfi/x86_64/scfi-callee-saved-4.s: New test. * gas/scfi/x86_64/scfi-cfg-1.d: New test. * gas/scfi/x86_64/scfi-cfg-1.l: New test. * gas/scfi/x86_64/scfi-cfg-1.s: New test. * gas/scfi/x86_64/scfi-cfg-2.d: New test. * gas/scfi/x86_64/scfi-cfg-2.l: New test. * gas/scfi/x86_64/scfi-cfg-2.s: New test. * gas/scfi/x86_64/scfi-cfi-label-1.d: New test. * gas/scfi/x86_64/scfi-cfi-label-1.l: New test. * gas/scfi/x86_64/scfi-cfi-label-1.s: New test. * gas/scfi/x86_64/scfi-cfi-sections-1.d: New test. * gas/scfi/x86_64/scfi-cfi-sections-1.l: New test. * gas/scfi/x86_64/scfi-cfi-sections-1.s: New test. * gas/scfi/x86_64/scfi-cofi-1.d: New test. * gas/scfi/x86_64/scfi-cofi-1.l: New test. * gas/scfi/x86_64/scfi-cofi-1.s: New test. * gas/scfi/x86_64/scfi-diag-1.l: New test. * gas/scfi/x86_64/scfi-diag-1.s: New test. * gas/scfi/x86_64/scfi-diag-2.l: New test. * gas/scfi/x86_64/scfi-diag-2.s: New test. * gas/scfi/x86_64/scfi-dyn-stack-1.d: New test. * gas/scfi/x86_64/scfi-dyn-stack-1.l: New test. * gas/scfi/x86_64/scfi-dyn-stack-1.s: New test. * gas/scfi/x86_64/scfi-enter-1.d: New test. * gas/scfi/x86_64/scfi-enter-1.l: New test. * gas/scfi/x86_64/scfi-enter-1.s: New test. * gas/scfi/x86_64/scfi-fp-diag-2.l: New test. * gas/scfi/x86_64/scfi-fp-diag-2.s: New test. * gas/scfi/x86_64/scfi-indirect-mov-1.d: New test. * gas/scfi/x86_64/scfi-indirect-mov-1.l: New test. * gas/scfi/x86_64/scfi-indirect-mov-1.s: New test. * gas/scfi/x86_64/scfi-indirect-mov-2.d: New test. * gas/scfi/x86_64/scfi-indirect-mov-2.l: New test. * gas/scfi/x86_64/scfi-indirect-mov-2.s: New test. * gas/scfi/x86_64/scfi-indirect-mov-3.d: New test. * gas/scfi/x86_64/scfi-indirect-mov-3.l: New test. * gas/scfi/x86_64/scfi-indirect-mov-3.s: New test. * gas/scfi/x86_64/scfi-indirect-mov-4.d: New test. * gas/scfi/x86_64/scfi-indirect-mov-4.l: New test. * gas/scfi/x86_64/scfi-indirect-mov-4.s: New test. * gas/scfi/x86_64/scfi-indirect-mov-5.s: New test. * gas/scfi/x86_64/scfi-lea-1.d: New test. * gas/scfi/x86_64/scfi-lea-1.l: New test. * gas/scfi/x86_64/scfi-lea-1.s: New test. * gas/scfi/x86_64/scfi-leave-1.d: New test. * gas/scfi/x86_64/scfi-leave-1.l: New test. * gas/scfi/x86_64/scfi-leave-1.s: New test. * gas/scfi/x86_64/scfi-pushq-1.d: New test. * gas/scfi/x86_64/scfi-pushq-1.l: New test. * gas/scfi/x86_64/scfi-pushq-1.s: New test. * gas/scfi/x86_64/scfi-pushsection-1.d: New test. * gas/scfi/x86_64/scfi-pushsection-1.l: New test. * gas/scfi/x86_64/scfi-pushsection-1.s: New test. * gas/scfi/x86_64/scfi-pushsection-2.d: New test. * gas/scfi/x86_64/scfi-pushsection-2.l: New test. * gas/scfi/x86_64/scfi-pushsection-2.s: New test. * gas/scfi/x86_64/scfi-selfalign-func-1.d: New test. * gas/scfi/x86_64/scfi-selfalign-func-1.l: New test. * gas/scfi/x86_64/scfi-selfalign-func-1.s: New test. * gas/scfi/x86_64/scfi-simple-1.d: New test. * gas/scfi/x86_64/scfi-simple-1.l: New test. * gas/scfi/x86_64/scfi-simple-1.s: New test. * gas/scfi/x86_64/scfi-simple-2.d: New test. * gas/scfi/x86_64/scfi-simple-2.l: New test. * gas/scfi/x86_64/scfi-simple-2.s: New test. * gas/scfi/x86_64/scfi-sub-1.d: New test. * gas/scfi/x86_64/scfi-sub-1.l: New test. * gas/scfi/x86_64/scfi-sub-1.s: New test. * gas/scfi/x86_64/scfi-sub-2.d: New test. * gas/scfi/x86_64/scfi-sub-2.l: New test. * gas/scfi/x86_64/scfi-sub-2.s: New test. * gas/scfi/x86_64/scfi-unsupported-1.l: New test. * gas/scfi/x86_64/scfi-unsupported-1.s: New test. * gas/scfi/x86_64/scfi-unsupported-2.l: New test. * gas/scfi/x86_64/scfi-unsupported-2.s: New test. * gas/scfi/x86_64/scfi-unsupported-3.l: New test. * gas/scfi/x86_64/scfi-unsupported-3.s: New test. * gas/scfi/x86_64/scfi-unsupported-4.l: New test. * gas/scfi/x86_64/scfi-unsupported-4.s: New test. * gas/scfi/x86_64/scfi-unsupported-cfg-1.l: New test. * gas/scfi/x86_64/scfi-unsupported-cfg-1.s: New test. * gas/scfi/x86_64/scfi-unsupported-cfg-2.l: New test. * gas/scfi/x86_64/scfi-unsupported-cfg-2.s: New test. * gas/scfi/x86_64/scfi-unsupported-drap-1.l: New test. * gas/scfi/x86_64/scfi-unsupported-drap-1.s: New test. * gas/scfi/x86_64/scfi-unsupported-insn-1.l: New test. * gas/scfi/x86_64/scfi-unsupported-insn-1.s: New test. * gas/scfi/x86_64/scfi-x86-64.exp: New file.
2024-01-12bpf: fix relocation addend incorrect symbol valueDavid Faust3-0/+63
Relocations installed by the BPF ELF backend were sometimes incorrectly adding the symbol value to the relocation entry addend, when the correct relocation value was already stored in the addend. This could lead to a relocation effectively adding the symbol value twice. Fix that by making bpf_elf_generic_reloc () more similar to the flow of bfd_install_relocation in the case where howto->install_addend is set, which is how it ought to behave. bfd/ * bpf-reloc.def (R_BPF_64_ABS32, R_BPF_64_ABS64) (R_BPF_64_NODYLD32): Set partial_inplace to true. * elf64-bpf.c (bpf_elf_generic_reloc): Do not include the value of the symbol when installing relocation. Copy some additional logic from bfd_elf_generic_reloc. gas/ * testsuite/gas/bpf/bpf.exp: Run new test. * testsuite/gas/bpf/elf-relo-1.d: New. * testsuite/gas/bpf/elf-relo-1.s: New.
2024-01-12aarch64: Make FEAT_ASMv8p2 instruction aliases always availableAndrew Carlotti1-1/+1
There's no reason to disallow the aliases when the aliased instructions are always available. The new behaviour matches existing LLVM behaviour.
2024-01-12aarch64: Add +xs flag for existing instructionsAndrew Carlotti2-0/+20
Additionally, change FEAT_XS tlbi variants to be gated on "+xs" instead of "+d128". This is an incremental improvement; there are still some FEAT_XS tlbi variants that are gated incorrectly or missing entirely.
2024-01-12aarch64: Add +wfxt flag for existing instructionsAndrew Carlotti2-0/+132
2024-01-12aarch64: Add +rcpc2 flag for existing instructionsAndrew Carlotti3-1/+2232
2024-01-12aarch64: Add +flagm2 flag for existing instructionsAndrew Carlotti1-0/+1
2024-01-12aarch64: Add +frintts flag for existing instructionsAndrew Carlotti4-4/+15
2024-01-12aarch64: Add +jscvt flag for existing fjcvtzs instructionAndrew Carlotti1-0/+1
2024-01-12aarch64: Fix option parsing to disallow prefixes of valid optionsAndrew Carlotti3-0/+3
Add "+rdm" as an explicit alias for "+rdma", to maintain existing compatibility with Clang.
2024-01-12aarch64: Add +fcma alias for +compnumAndrew Carlotti1-0/+1
2024-01-12gas: sframe: warn when skipping SFrame FDE generationIndu Bhagat2-0/+2
Fix PR gas/31213. gas/ PR gas/31213 * gen-sframe.c (sframe_do_cfi_insn): Add new warning. gas/testsuite/ * gas/cfi-sframe/common-empty-1.d: Test the new warning as well. * gas/cfi-sframe/common-empty-2.d: Likewise.
2024-01-11LoongArch: Discard extra spaces in objdump outputLulu Cai6-13/+13
Due to the formatted output of objdump, some instructions that do not require output operands (such as nop/ret) will have extra spaces added after them. Determine whether to output operands through the format of opcodes. When opc->format is an empty string, no extra spaces are output.
2024-01-10gas: aarch64: Add system registers for Debug and PMU extensionsSaurabh Jha3-0/+151
This patch adds support for the new AArch64 system registers that are part of the following extensions: * FEAT_DEBUGv8p9 * FEAT_PMUv3p9 * FEAT_PMUv3_SS * FEAT_PMUv3_ICNTR * FEAT_SEBEP
2024-01-09x86: add missing APX logic to cpu_flags_match()Jan Beulich2-0/+17
As already indicated during review, we can't get away without certain adjustments here: Without these, respective {evex}-prefixed insns are assembled to APX encodings even when APX_F is turned off. While there also extend the respective comment in the opcode table, to explain why this construct is used.
2024-01-09x86: FMA insns aren't eligible to VEX2 encodingJan Beulich7-0/+9
PR gas/31178 In da0784f961d8 ("x86: fold FMA VEX and EVEX templates") I overlooked that C aliases StaticRounding, and hence build_vex_prefix() now needs to be aware of that aliasing. Disambiguation is easy, as StaticRounding is only ever used together with SAE (hence why the overlaying works in the first place).
2024-01-09aarch64: ADD FEAT_THE RCWCAS instructions.Srinath Parvathaneni15-0/+1289
This patch adds support for FEAT_THE doubleword and quadword instructions. doubleword insturctions are enabled by "+the" flag whereas quadword instructions are enabled on passing both "+the and +d128" flags. Support for following sets of instructions is added in this patch. Read check write compare and swap doubleword: (rcwcas, rcwcasa, rcwcasal, rcwcasl) Read check write compare and swap quadword: (rcwcasp,rcwcaspa, rcwcaspal, rcwcaspl) Read check write software compare and swap doubleword: (rcwscas, rcwscasa, rcwscasal, rcwscasl) Read check write software compare and swap quadword: (rcwscasp, rcwscaspa, rcwscaspal, rcwscaspl) Read check write atomic bit clear on doubleword: (rcwclr, rcwclra, rcwclral, rcwclrl) Read check write atomic bit clear on quadword: (rcwclrp, rcwclrpa, rcwclrpal, rcwclrpl) Read check write software atomic bit clear on doubleword: (rcwsclr, rcwsclra, rcwsclral, rcwsclrl) Read check write software atomic bit clear on quadword: (rcwsclrp,rcwsclrpa, rcwsclrpal,rcwsclrpl) Read check write atomic bit set on doubleword: (rcwset,rcwseta, rcwsetal,rcwsetl) Read check write atomic bit set on quadword: (rcwsetp,rcwsetpa,rcwsetpal,rcwsetpl) Read check write software atomic bit set on doubleword: (rcwsset,rcwsseta,rcwssetal,rcwssetl) Read check write software atomic bit set on quadword: (rcwssetp,rcwssetpa,rcwssetpal,rcwssetpl) Read check write swap doubleword: (rcwswp,rcwswpa,rcwswpal,rcwswpl) Read check write swap quadword: (rcwswpp,rcwswppa, rcwswppal,rcwswppl) Read check write software swap doubleword: (rcwsswp,rcwsswpa,rcwsswpal,rcwsswpl) Read check write software swap quadword: (rcwsswpp,rcwsswppa,rcwsswppal,rcwsswppl)
2024-01-09arch64: Add optional operand register pair support testsVictor Do Nascimento5-0/+57
Add tests to cover the full range of behaviors observed around optional register operands for the `tlbip' and `sysp' instructions, namely: * Not all `tlbip' operations take GPR operands. When this is the case, we should check that neither optional operand was supplied. * When a `tlbip' operation is labeled with the `F_HASXT' flag, xzr is not a valid optional operand. In such case, at least the fist optional register needs to be specified with a non-xzr value. * The first operand for both insns should be either xzr or an even-numbered register (n % 2 == 0). In the former scenario, the second operand should default to xzr too, while in the latter, it should default to n + 1.
2024-01-09aarch64: Add support for 128-bit system register mrrs and msrr insnsVictor Do Nascimento5-0/+66
With the addition of 128-bit system registers to the Arm architecture starting with Armv9.4-a, a mechanism for manipulating their contents is introduced with the `msrr' and `mrrs' instruction pair. These move values from one such 128-bit system register into a pair of contiguous general-purpose registers and vice-versa, as for example: msrr ttlb0_el1, x0, x1 mrrs x0, x1, ttlb0_el1 This patch adds the necessary support for these instructions, adding checks for system-register width by defining a new operand type in the form of `AARCH64_OPND_SYSREG128' and the `aarch64_sys_reg_128bit_p' predicate, responsible for checking whether the requested system register table entry is marked as implemented in the 128-bit mode via the F_REG_128 flag.
2024-01-09aarch64: Add TLBIP testsVictor Do Nascimento2-0/+259
generated by cgit v1.1 at 2024-11-25 18:25:39 +0000