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AgeCommit message (Expand)AuthorFilesLines
2024-02-06x86: Warn .insn instruction with length > 15 bytesH.J. Lu2-0/+11
2024-02-04LoongArch: gas: Fix the types of symbols referred with %le_*_r in the symtabXi Ruoyao2-0/+9
2024-02-02x86: Disallow instructions with length > 15 bytesH.J. Lu5-30/+38
2024-02-02x86: actually implement .nooptJan Beulich5-18/+33
2024-02-01gas: x86: ginsn: adjust ginsns for certain lea opsIndu Bhagat3-0/+77
2024-01-29bpf: there is no ldinddw nor ldabsdw instructionsJose E. Marchesi6-97/+82
2024-01-26gas: scfi: untraceable control flow should be a hard errorIndu Bhagat2-9/+11
2024-01-26x86: testsuite: scfi: adjust COFI testcaseIndu Bhagat5-14/+37
2024-01-26x86: make "-msyntax=intel -mnaked-reg" match ".intel_syntax noprefix"Jan Beulich5-3/+12
2024-01-26x86/APX: optimize MOVBEJan Beulich2-0/+6
2024-01-26LoongArch: gas: Add support for s9 registermengqinggang3-0/+4
2024-01-24LoongArch: gas: Start a new frag after instructions that can be relaxedmengqinggang2-0/+79
2024-01-24LoongArch: gas: Don't define LoongArch .alignmengqinggang3-0/+7
2024-01-22LoongArch: Use tab to indent assembly in TLSDESC test suiteTatsuyuki Ishi2-2/+2
2024-01-22x86/APX: also amend the PUSH2/POP2 testcaseJan Beulich2-0/+2
2024-01-21LoongArch: Do not emit R_LARCH_RELAX for two register macrosmengqinggang2-111/+98
2024-01-19Update x86/APX: VROUND{P,S}{S,D} can generally be encodedH.J. Lu2-0/+2
2024-01-19x86/APX: VROUND{P,S}{S,D} can generally be encodedJan Beulich5-8/+20
2024-01-19x86/APX: be consistent with insn suffixesJan Beulich1-43/+43
2024-01-19x86: support APX forms of U{RD,WR}MSRJan Beulich3-0/+20
2024-01-15x86-64: Skip SCFI tests for x32 targetsH.J. Lu1-1/+1
2024-01-15aarch64: rcpc3: Add FP load/store insnsVictor Do Nascimento5-0/+90
2024-01-15aarch64: rcpc3: Add integer load/store insnsVictor Do Nascimento6-2/+65
2024-01-15aarch64: Fix tlbi and tlbip instructionsAndrew Carlotti8-142/+231
2024-01-15aarch64: Add SVE2.1 Contiguous load/store instructions.Srinath Parvathaneni3-0/+43
2024-01-15PATCH 5/6][Binutils] aarch64: Add SVE2.1 fmin and fmax instructions.Srinath Parvathaneni3-0/+79
2024-01-15aarch64: Add SVE2.1 dupq, eorqv and extq instructions.Srinath Parvathaneni3-0/+62
2024-01-15aarch64: Add support for FEAT_SVE2p1.Srinath Parvathaneni4-0/+128
2024-01-15aarch64: Add support for FEAT_SME2p1 instructions.Srinath Parvathaneni2-0/+81
2024-01-15aarch64: Add support for FEAT_B16B16 instructions.Srinath Parvathaneni4-0/+319
2024-01-15gas: testsuite: add an x86 testsuite for SCFIIndu Bhagat129-0/+3074
2024-01-12bpf: fix relocation addend incorrect symbol valueDavid Faust3-0/+63
2024-01-12aarch64: Make FEAT_ASMv8p2 instruction aliases always availableAndrew Carlotti1-1/+1
2024-01-12aarch64: Add +xs flag for existing instructionsAndrew Carlotti2-0/+20
2024-01-12aarch64: Add +wfxt flag for existing instructionsAndrew Carlotti2-0/+132
2024-01-12aarch64: Add +rcpc2 flag for existing instructionsAndrew Carlotti3-1/+2232
2024-01-12aarch64: Add +flagm2 flag for existing instructionsAndrew Carlotti1-0/+1
2024-01-12aarch64: Add +frintts flag for existing instructionsAndrew Carlotti4-4/+15
2024-01-12aarch64: Add +jscvt flag for existing fjcvtzs instructionAndrew Carlotti1-0/+1
2024-01-12aarch64: Fix option parsing to disallow prefixes of valid optionsAndrew Carlotti3-0/+3
2024-01-12aarch64: Add +fcma alias for +compnumAndrew Carlotti1-0/+1
2024-01-12gas: sframe: warn when skipping SFrame FDE generationIndu Bhagat2-0/+2
2024-01-11LoongArch: Discard extra spaces in objdump outputLulu Cai6-13/+13
2024-01-10gas: aarch64: Add system registers for Debug and PMU extensionsSaurabh Jha3-0/+151
2024-01-09x86: add missing APX logic to cpu_flags_match()Jan Beulich2-0/+17
2024-01-09x86: FMA insns aren't eligible to VEX2 encodingJan Beulich7-0/+9
2024-01-09aarch64: ADD FEAT_THE RCWCAS instructions.Srinath Parvathaneni15-0/+1289
2024-01-09arch64: Add optional operand register pair support testsVictor Do Nascimento5-0/+57
2024-01-09aarch64: Add support for 128-bit system register mrrs and msrr insnsVictor Do Nascimento5-0/+66
2024-01-09aarch64: Add TLBIP testsVictor Do Nascimento2-0/+259
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