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author | Victor Do Nascimento <victor.donascimento@arm.com> | 2024-01-04 14:06:38 +0000 |
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committer | Victor Do Nascimento <victor.donascimento@arm.com> | 2024-01-15 13:11:48 +0000 |
commit | e771eaf8bb4cfc4a04346a14756fa21e01e7b9ba (patch) | |
tree | 01d2911ac905de462246f50d060ea75c2ac03edc /gas/testsuite | |
parent | b88fbd5213b2c38141c066365d7ea092ab7cfea8 (diff) | |
download | gdb-e771eaf8bb4cfc4a04346a14756fa21e01e7b9ba.zip gdb-e771eaf8bb4cfc4a04346a14756fa21e01e7b9ba.tar.gz gdb-e771eaf8bb4cfc4a04346a14756fa21e01e7b9ba.tar.bz2 |
aarch64: rcpc3: Add integer load/store insns
Along with the relevant unit tests and updates to the existing
regression tests, this adds support for the following novel rcpc3
insns:
LDIAPP <Wt1>, <Wt2>, [<Xn|SP>]
LDIAPP <Wt1>, <Wt2>, [<Xn|SP>], #8
LDIAPP <Xt1>, <Xt2>, [<Xn|SP>]
LDIAPP <Xt1>, <Xt2>, [<Xn|SP>], #16
STILP <Wt1>, <Wt2>, [<Xn|SP>]
STILP <Wt1>, <Wt2>, [<Xn|SP>, #-8]!
STILP <Xt1>, <Xt2>, [<Xn|SP>]
STILP <Xt1>, <Xt2>, [<Xn|SP>, #-16]!
LDAPR <Wt>, [<Xn|SP>], #4
LDAPR <Xt>, [<Xn|SP>], #8
STLR <Wt>, [<Xn|SP>, #-4]!
STLR <Xt>, [<Xn|SP>, #-8]!
Diffstat (limited to 'gas/testsuite')
-rw-r--r-- | gas/testsuite/gas/aarch64/illegal-ldapr.l | 4 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/rcpc3-fail.d | 3 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/rcpc3-fail.l | 9 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/rcpc3-fail.s | 13 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/rcpc3.d | 21 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/rcpc3.s | 17 |
6 files changed, 65 insertions, 2 deletions
diff --git a/gas/testsuite/gas/aarch64/illegal-ldapr.l b/gas/testsuite/gas/aarch64/illegal-ldapr.l index 5e3ca6d..8811b73 100644 --- a/gas/testsuite/gas/aarch64/illegal-ldapr.l +++ b/gas/testsuite/gas/aarch64/illegal-ldapr.l @@ -22,7 +22,7 @@ [^:]+:23: Info: macro .* [^:]+:6: Error: the optional immediate offset can only be 0 at operand 2 -- `ldapr w1,\[x7,#8\]' [^:]+:23: Info: macro .* -[^:]+:7: Error: invalid addressing mode at operand 2 -- `ldapr w1,\[x7,#8\]!' +[^:]+:7: Error: unexpected address writeback at operand 2 -- `ldapr w1,\[x7,#8\]!' [^:]+:23: Info: macro .* -[^:]+:8: Error: invalid addressing mode at operand 2 -- `ldapr w1,\[x7\],#8' +[^:]+:8: Error: invalid increment amount at operand 2 -- `ldapr w1,\[x7\],#8' [^:]+:23: Info: macro .* diff --git a/gas/testsuite/gas/aarch64/rcpc3-fail.d b/gas/testsuite/gas/aarch64/rcpc3-fail.d new file mode 100644 index 0000000..508a27f --- /dev/null +++ b/gas/testsuite/gas/aarch64/rcpc3-fail.d @@ -0,0 +1,3 @@ +#name: RCPC3 GPR load/store illegal +#as: -march=armv8.3-a+rcpc3 -mno-verbose-error +#error_output: rcpc3-fail.l diff --git a/gas/testsuite/gas/aarch64/rcpc3-fail.l b/gas/testsuite/gas/aarch64/rcpc3-fail.l new file mode 100644 index 0000000..4b33c85 --- /dev/null +++ b/gas/testsuite/gas/aarch64/rcpc3-fail.l @@ -0,0 +1,9 @@ +[^:]+: Assembler messages: +[^:]+:3: Error: operand 3 must be an address with post-incrementing by ammount of loaded bytes -- `ldiapp w0,w1,\[x3,#8\]' +[^:]+:4: Error: operand 3 must be an address with post-incrementing by ammount of loaded bytes -- `ldiapp x0,x1,\[x3,#16\]' +[^:]+:6: Error: operand 3 must be an address with pre-incrementing with write-back by ammount of stored bytes -- `stilp w0,w1,\[x3,#8\]' +[^:]+:7: Error: operand 3 must be an address with pre-incrementing with write-back by ammount of stored bytes -- `stilp x0,x1,\[x3,#16\]' +[^:]+:9: Error: invalid addressing mode at operand 3 -- `stilp w0,w1,\[x3\],#8' +[^:]+:10: Error: invalid addressing mode at operand 3 -- `stilp x0,x1,\[x3\],#16' +[^:]+:12: Error: invalid addressing mode at operand 3 -- `ldiapp w0,w1,\[x3,#-8\]!' +[^:]+:13: Error: invalid addressing mode at operand 3 -- `ldiapp x0,x1,\[x3,#-16\]!' diff --git a/gas/testsuite/gas/aarch64/rcpc3-fail.s b/gas/testsuite/gas/aarch64/rcpc3-fail.s new file mode 100644 index 0000000..23b9eaa --- /dev/null +++ b/gas/testsuite/gas/aarch64/rcpc3-fail.s @@ -0,0 +1,13 @@ +.text + + ldiapp w0, w1, [x3, #8] + ldiapp x0, x1, [x3, #16] + + stilp w0, w1, [x3, #8] + stilp x0, x1, [x3, #16] + + stilp w0, w1, [x3], #8 + stilp x0, x1, [x3], #16 + + ldiapp w0, w1, [x3, #-8]! + ldiapp x0, x1, [x3, #-16]! diff --git a/gas/testsuite/gas/aarch64/rcpc3.d b/gas/testsuite/gas/aarch64/rcpc3.d new file mode 100644 index 0000000..4560ed0 --- /dev/null +++ b/gas/testsuite/gas/aarch64/rcpc3.d @@ -0,0 +1,21 @@ +#name: RCPC3 GPR load/store +#as: -march=armv8.2-a+rcpc3 +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0+ <.*>: + 0: d9411860 ldiapp x0, x1, \[x3\] + 4: 99411860 ldiapp w0, w1, \[x3\] + 8: d9410860 ldiapp x0, x1, \[x3\], #16 + c: 99410860 ldiapp w0, w1, \[x3\], #8 + 10: d9011860 stilp x0, x1, \[x3\] + 14: 99011860 stilp w0, w1, \[x3\] + 18: d9010860 stilp x0, x1, \[x3, #-16\]! + 1c: 99010860 stilp w0, w1, \[x3, #-8\]! + 20: 99c00841 ldapr w1, \[x2\], #4 + 24: d9c00841 ldapr x1, \[x2\], #8 + 28: 99800841 stlr w1, \[x2, #-4\]! + 2c: d9800841 stlr x1, \[x2, #-8\]! diff --git a/gas/testsuite/gas/aarch64/rcpc3.s b/gas/testsuite/gas/aarch64/rcpc3.s new file mode 100644 index 0000000..2a87734 --- /dev/null +++ b/gas/testsuite/gas/aarch64/rcpc3.s @@ -0,0 +1,17 @@ +.text + + ldiapp x0, x1, [x3] + ldiapp w0, w1, [x3] + ldiapp x0, x1, [x3], #16 + ldiapp w0, w1, [x3], #8 + + stilp x0, x1, [x3] + stilp w0, w1, [x3] + stilp x0, x1, [x3, #-16]! + stilp w0, w1, [x3, #-8]! + + ldapr w1, [x2], #4 + ldapr x1, [x2], #8 + + stlr w1, [x2, #-4]! + stlr x1, [x2, #-8]! |