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2019-09-18Re-generate many configure and Makefile.in filesSimon Marchi1-1/+0
I get some spurious changes when running autoconf/automake for various projects in the tree. This is likely because they were generated using distro-patched tools last time. I ran `autoreconf -f` in the various automake projects of the binutils-gdb tree, and this is the result. The tools I am using have been compiled from source, from the upstream release. bfd/ChangeLog: * Makefile.in: Re-generate. * configure: Re-generate. * doc/Makefile.in: Re-generate. binutils/ChangeLog: * Makefile.in: Re-generate. * configure: Re-generate. * doc/Makefile.in: Re-generate. gas/ChangeLog: * Makefile.in: Re-generate. * configure: Re-generate. * doc/Makefile.in: Re-generate. gold/ChangeLog: * testsuite/Makefile.in: Re-generate. gprof/ChangeLog: * Makefile.in: Re-generate. * configure: Re-generate. ld/ChangeLog: * Makefile.in: Re-generate. * configure: Re-generate. opcodes/ChangeLog: * Makefile.in: Re-generate. * configure: Re-generate.
2019-09-16Update version to 2.33.50 and regenerate configure scripts.Phil Blundell1-0/+1
2019-08-22Arm: Add support for missing CPUsDennis Zhang1-0/+3
This patch adds support for following CPUs: Cortex-M35P, Cortex-A77, Cortex-A76AE. Related specifications can be found at https://developer.arm.com/ip-products/processors. gas/ChangeLog: * config/tc-arm.c: New entries for Cortex-M35P, Cortex-A77, and Cortex-A76AE. * doc/c-arm.texi: Document new processors. * testsuite/gas/arm/cpu-cortex-a76ae.d: New test. * testsuite/gas/arm/cpu-cortex-a77.d: New test. * testsuite/gas/arm/cpu-cortex-m35p.d: New test. bfd/ChangeLog: * cpu-arm.c: New entries for Cortex-M35P, Cortex-A77, Cortex-A76AE.
2019-08-22Implement a float16 directive for assembling 16 bit IEEE 754 floating point ↵Barnaby Wilks1-0/+8
numbers for the AArch64 assembler. The syntax of the directive is: .float16 <0-n decimal numbers> e.g. .float16 0.5 .float16 10.2, NaN, 452.09 The floats will always be encoded using the binary16 format as described in the IEEE 754-2008 standard. There is no need to support Arm's alternative half-precision format since AArch64 only supports the IEEE format. gas * config/tc-aarch64.c: Add float16 directive and add "Hh" to acceptable float characters. * doc/c-aarch64.texi: Documentation for float16 directive. * testsuite/gas/aarch64/float16-be.d: New test. * testsuite/gas/aarch64/float16-le.d: New test. * testsuite/gas/aarch64/float16.s: New test. * NEWS: Add NEWS entry.
2019-08-20Adds support for following CPUs to the ARM and Aarch64 assemblers: ↵Dennis Zhang1-0/+5
Cortex-A77, Cortex-A76AE, Cortex-A34, Cortex-A65, and Cortex-A65AE. Related specifications can be found at https://developer.arm.com/ip-products/processors. gas * NEWS: Mention the Arm and AArch64 new processors. * config/tc-aarch64.c: New entries for Cortex-A34, Cortex-A65, Cortex-A77, cortex-A65AE, and Cortex-A76AE. * doc/c-aarch64.texi: Document new CPUs. * testsuite/gas/aarch64/cpu-cortex-a34.d: New test. * testsuite/gas/aarch64/cpu-cortex-a65.d: New test. * testsuite/gas/aarch64/cpu-cortex-a65ae.d: New test. * testsuite/gas/aarch64/cpu-cortex-a76ae.d: New test. * testsuite/gas/aarch64/cpu-cortex-a77.d: New test. * testsuite/gas/aarch64/nop-asm.s: New test. bfd * cpu-aarch64.c: New entries for Cortex-A34, Cortex-A65, Cortex-A77, cortex-A65AE, and Cortex-A76AE.
2019-08-12Add generic and ARM specific support for half-precision IEEE 754 floating ↵Barnaby Wilks1-0/+33
point numbers to the assembler. Half precision floating point numbers will be encoded using the IEEE 754 half precision floating point format - 16 bits in total, 1 for sign, 5 for exponent and 10 bits of mantissa. This patch implements the float16 directive for both the IEEE 754 format and the Arm alternative format for the Arm backend. The syntax of the directive is: .float16 <0-n decimal numbers> e.g. .float16 12.0 .float16 0.23, 433.1, 0.06 The Arm alternative format is almost identical to the IEEE 754 format, except that it doesn't encode for NaNs or Infinity (instead an exponent of 0x1F represents a normalized number in the range 65536 to 131008). The alternative format is documented in the reference manual: https://static.docs.arm.com/ddi0487/db/DDI0487D_b_armv8_arm.pdf?_ga=2.72318806.49764181.1561632697-999473562.1560847439 Which format is used is controlled by the .float16_format <format> directive, where if <format> = ieee, then use the IEEE 754 half-precision format else if <format> = alternative, then use the Arm alternative format Or the format can be set on the command line via the -mfp16-format option that has a similar syntax. -mfp16-format=<ieee|alternative>. This also fixes the format and it cannot be changed by any directives. Once the format has been set (either by the command line option or a directive) it cannot be changed, and any attempts to change it (i.e. with the float16_format directive) will result in a warning and the line being ignored. For ELF targets the appropriate EABI attribute will be written out at the end of assembling if the format has been explicitly specified. If no format has been explicitly specified then no EABI attributes will be written. If the format is not explicitly specified then any float16 directives are encoding using the IEEE 754-2008 format by default until the format is fixed or changed with the float16_format directive. gas * config/tc-arm.c (enum fp_16bit_format): Add enum to represent the 2 float16 encodings. (md_atof): Set precision for float16 type. (arm_is_largest_exponent_ok): Check for whether to encode with the IEEE or alternative format. (set_fp16_format): Parse a float16_format directive. (arm_parse_fp16_opt): Parse the fp16-format command line option. (aeabi_set_public_attributes): For ELF encode the FP16 format EABI attribute. * config/tc-arm.h (TC_LARGEST_EXPONENT_IS_NORMAL): Macro that expands to arm_is_largest_exponent_ok. (arm_is_largest_exponent_ok): Add prototype for arm_is_largest_exponent_ok function. * doc/c-arm.texi: Add documentation for .float16, .float16_format and -mfp16-format= * testsuite/gas/arm/float16-bad.d: New test. * testsuite/gas/arm/float16-bad.l: New test. * testsuite/gas/arm/float16-bad.s: New test. * testsuite/gas/arm/float16-be.d: New test. * testsuite/gas/arm/float16-format-bad.d: New test. * testsuite/gas/arm/float16-format-bad.l: New test. * testsuite/gas/arm/float16-format-bad.s: New test. * testsuite/gas/arm/float16-format-opt-bad.d: New test. * testsuite/gas/arm/float16-format-opt-bad.l: New test. * testsuite/gas/arm/float16-le.d: New test. * testsuite/gas/arm/float16.s: New test. * testsuite/gas/arm/float16-eabi-alternative-format.d: New test. * testsuite/gas/arm/float16-eabi-ieee-format.d: New test. * testsuite/gas/arm/float16-eabi-no-format.d: New test. * testsuite/gas/arm/float16-eabi.s: New test. * config/atof-ieee.c (H_PRECISION): Macro for precision of float16 type. (atof_ieee): Set precision and exponent bits for encoding float16 types. (gen_to_words): NaN and Infinity encoding for float16. (ieee_md_atof): Set precision for encoding float16 type.
2019-07-19[AArch64] Rename +bitperm to +sve2-bitpermRichard Sandiford1-1/+1
After some discussion, we've decided to rename the +bitperm feature flag to +sve2-bitperm, so that it's consistent with the other SVE2 feature flags. The associated internal macros already used "SVE2_BITPERM", so only the feature flag itself needs to change. 2019-07-19 Richard Sandiford <richard.sandiford@arm.com> gas/ * doc/c-aarch64.texi: Remame the +bitperm extension to +sve2-bitperm. * config/tc-aarch64.c (aarch64_features): Likewise. * testsuite/gas/aarch64/illegal-sve2-aes.d: Update accordingly. * testsuite/gas/aarch64/illegal-sve2-sha3.d: Likewise. * testsuite/gas/aarch64/illegal-sve2-sm4.d: Likewise. * testsuite/gas/aarch64/illegal-sve2.d: Likewise. * testsuite/gas/aarch64/sve2.d: Likewise.
2019-07-17gas: support .half, .word and .dword directives in eBPFJose E. Marchesi1-0/+23
This little patch adds support to the eBPF port of GAS for a few data directives. The names for the directives have been chosen to be coherent with the suffixes used in eBPF instructions: b, h, w and dw for 8, 16, 32 and 64-bit values respectively. Documentation and tests included. Tested in a x86_64 host. gas/ChangeLog: 2019-07-17 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c (md_pseudo_table): .half, .word and .dword. * testsuite/gas/bpf/data.s: New file. * testsuite/gas/bpf/data.d: Likewise. * testsuite/gas/bpf/data-be.d: Likewise. * testsuite/gas/bpf/bpf.exp: Run data and data-be. * doc/c-bpf.texi (BPF Directives): New section.
2019-07-15cpu,opcodes,gas: fix explicit arguments to eBPF ldabs instructionsJose E. Marchesi1-8/+8
This patch fixes the eBPF CPU description in order to reflect the right explicit arguments passed to the ldabs{b,h,w,dw} instructions, updates the corresponding GAS tests, and updates the BPF section of the GAS manual. cpu/ChangeLog: 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf.cpu (dlabs): New pmacro. (dlind): Likewise. opcodes/ChangeLog: 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-desc.c: Regenerate. * bpf-opc.c: Likewise. * bpf-opc.h: Likewise. gas/ChangeLog: 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/mem.s: ldabs instructions do not take a `src' register as an argument. * testsuite/gas/bpf/mem.d: Updated accordingly. * testsuite/gas/bpf/mem-be.d: Likewise. * doc/c-bpf.texi (BPF Opcodes): Update to reflect the correct explicit arguments to ldabs and ldind instructions.
2019-07-05Kito's 5-part patch set to improve .insn support.Jim Wilson1-5/+9
From Kito Cheng <kito.cheng@sifive.com> gas/ChangeLog * doc/c-riscv.texi (Instruction Formats): Add r4 type. * testsuite/gas/riscv/insn.d: Add testcase for r4 type. * testsuite/gas/riscv/insn.s: Ditto. * doc/c-riscv.texi (Instruction Formats): Add b and j type. * testsuite/gas/riscv/insn.d: Add test case for b and j type. * testsuite/gas/riscv/insn.s: Ditto. * testsuite/gas/riscv/insn.s: Correct instruction type for load and store. * testsuite/gas/riscv/insn.d: Using regular expression to match address. * doc/c-riscv.texi (Instruction Formats): Fix encoding table for SB type and fix typo. opcode/ChangeLog * riscv-opc.c (riscv_insn_types): Add r4 type. * riscv-opc.c (riscv_insn_types): Add b and j type. * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect format for sb type and correct s type.
2019-07-04gas/ELF: don't accumulate .type settingsJan Beulich1-0/+4
Recently a patch was submitted for a Xen Project test harness binary to override the compiler specified @object to @func (see [1]). In a reply I suggested we shouldn't make ourselves dependent on currently unspecified behavior of gas here: It accumulates all requests, and then bfd/elf.c:swap_out_syms(), in an apparently ad hoc manner, prioritizes certain flags over others. Make the behavior predictable: Generally the last .type is what counts. Exceptions are directives which set multiple bits (TLS, IFUNC, and UNIQUE): Subsequent directives requesting just the more generic bit (i.e. FUNC following IFUNC) won't clear the more specific one. Warn about incompatible changes, except from/to STT_NOTYPE. Also add a new target hook, which hppa wants to use right away afaict. In the course of adding the warning I ran into two ld testsuite failures. I can only assume that it was a copy-and-paste mistake that lead to the same symbol having its type set twice. [1] https://lists.xenproject.org/archives/html/xen-devel/2019-05/msg01980.html
2019-07-01[gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AESMatthew Malcomson1-1/+2
I had mistakenly given all variants of the new SVE2 instructions pmull{t,b} a dependency on the feature +sve2-aes. Only the variant specifying .Q -> .D sizes should have that restriction. This patch fixes that mistake and updates the testsuite to have extra tests (matching the given set of tests per line in aarch64-tbl.h that the rest of the SVE2 tests follow). We also add a line in the documentation of the command line to clarify how to enable `pmull{t,b}` of this larger size. This is needed because all other instructions gated under the `sve2-aes` architecture extension are marked in the instruction documentation by an `HaveSVE2AES` check while pmull{t,b} is gated under the `HaveSVE2PMULL128` check. Regtested targeting aarch64-linux. gas/ChangeLog: 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com> * testsuite/gas/aarch64/illegal-sve2-aes.d: Update tests. * testsuite/gas/aarch64/illegal-sve2.l: Update tests. * doc/c-aarch64.texi: Add special note of pmull{t,b} instructions under the sve2-aes architecture extension. * testsuite/gas/aarch64/illegal-sve2.s: Add small size pmull{t,b} instructions. * testsuite/gas/aarch64/sve2.d: Add small size pmull{t,b} disassembly. * testsuite/gas/aarch64/sve2.s: Add small size pmull{t,b} instructions. include/ChangeLog: 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): sve_size_013 renamed to sve_size_13. opcodes/ChangeLog: 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new sve_size_13 icode to account for variant behaviour of pmull{t,b}. * aarch64-dis-2.c: Regenerate. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new sve_size_13 icode to account for variant behaviour of pmull{t,b}. * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier. (OP_SVE_VVV_Q_D): Add new qualifier. (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier. (struct aarch64_opcode): Split pmull{t,b} into those requiring AES and those not.
2019-07-01Document the .value directive supported by the x86 and x86_64 assemblers.Nick Clifton1-0/+6
PR 24738 * doc/c-i386.texi (i386-Directives): Add a description of the Value directive.
2019-07-01Correct a typo in the description of the Align and P2align directives.Nick Clifton1-2/+2
PR 24737 * doc/as.texi (Align): Add missing word to description of pseudo-op. (P2align): Likewise.
2019-07-01Fix spelling error in assembler documentation.Nick Clifton1-1/+1
2019-07-01x86: optimize AND/OR with twice the same registerJan Beulich1-1/+2
It seems to be not uncommon for people to use AND or OR in this form for just setting the status flags. TEST, which doesn't write to any register other than EFLAGS, ought to be preferred. Make the change only for -O2 and above though, at least for now.
2019-07-01x86-64: optimize certain commutative VEX-encoded insnsJan Beulich1-1/+4
When they're in the 0F opcode space, swapping their source operands may allow switching from 3-byte to 2-byte VEX prefix encoding. Note that NaN behavior precludes us doing so for many packed and scalar floating point insns; such an optimization would need to be done by the compiler instead in this case, when it knows that NaN-s have undefined behavior anyway. While for explicitly specified AVX/AVX2 insns the optimization (for now at least) gets done only for -O2 and -Os, it is utilized by default in SSE2AVX mode, as there we're re-writing the programmer's specified insns anyway. Rather than introducing a new attribute flag, the change re-uses one which so far was meaningful only for EVEX-encoded insns.
2019-07-01x86: optimize EVEX packed integer logical instructionsJan Beulich1-6/+10
As long as there's no write mask as well as no broadcast, and as long as the scaled Disp8 wouldn't result in a shorter EVEX encoding, encode VPAND{D,Q}, VPANDN{D,Q}, VPOR{D,Q}, and VPXOR{D,Q} acting on only the lower 16 XMM/YMM registers using their VEX equivalents with -O1. Also take the opportunity and avoid looping twice over all operands when dealing with memory-with-displacement ones.
2019-06-26i386: Document memory size reference in assemblerLili Cui1-5/+10
* doc/c-i386.texi: Document x/y/z instruction sufffixes in AT&T syntax and xmmword/ymmword/zmmword/fword/tbyte/oword ptr in Intel syntax.
2019-06-25x86: document certain command line options as "dangerous"Jan Beulich1-0/+6
Errata BT36, BT41, and BT230 mean that gas may, when using one ofthese options, produce code that causes #UD on (at least) SandyBridge systems.
2019-06-14Regenerate with approved autotools versionAlan Modra1-1/+0
bfd/ * Makefile.in: Regenerate. * configure: Regenerate. binutils/ * Makefile.in: Regenerate. * aclocal.m4: Regenerate. * doc/Makefile.in: Regenerate. gas/ * Makefile.in: Regenerate. * configure: Regenerate. * doc/Makefile.in: Regenerate. ld/ * Makefile.in: Regenerate. * configure: Regenerate. libctf/ * configure: Regenerate.
2019-06-06gas: Add .enqcmd and noenqcmd directivesH.J. Lu1-0/+1
2019-06-06 Lili Cui <lili.cui@intel.com> * config/tc-i386.c (cpu_arch): Add .enqcmd. (cpu_noarch): Add noenqcmd. * doc/c-i386.texi: Document noenqcmd.
2019-06-04Enable Intel AVX512_VP2INTERSECT insnH.J. Lu1-1/+2
This patch enables support for VP2INTERSECT in binutils. Please refer to https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf for VP2INTERSECT details. Make check-gas is ok. gas/ 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (cpu_arch): Add .avx512_vp2intersect. (cpu_noarch): Likewise. * doc/c-i386.texi: Document avx512_vp2intersect. * testsuite/gas/i386/i386.exp: Run vp2intersect tests. * testsuite/gas/i386/vp2intersect-intel.d: New test. * testsuite/gas/i386/vp2intersect.d: Likewise. * testsuite/gas/i386/vp2intersect.s: Likewise. * testsuite/gas/i386/vp2intersect-inval-bcast.l: Likewise. * testsuite/gas/i386/vp2intersect-inval-bcast.s: Likewise. * testsuite/gas/i386/x86-64-vp2intersect-intel.d: Likewise. * testsuite/gas/i386/x86-64-vp2intersect.d: Likewise. * testsuite/gas/i386/x86-64-vp2intersect.s: Likewise. * testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.l: Likewise. * testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.s: Likewise. opcodes/ 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3. * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT instructions. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS, CPU_ANY_AVX512_VP2INTERSECT_FLAGS. (cpu_flags): Add CpuAVX512_VP2INTERSECT. * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT. (i386_cpu_flags): Add cpuavx512_vp2intersect. * i386-opc.tbl: Add AVX512_VP2INTERSECT insns. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2019-06-04Add support for Intel ENQCMD[S] instructionsH.J. Lu1-1/+2
This patch enables support for ENQCMD[S] in binutils. Please refer to https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf for ENQCMD[S] details. Make check-gas is ok. gas/ChangeLog: 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com> Lili Cui <lili.cui@intel.com> * doc/c-i386.texi: Document enqcmd. * testsuite/gas/i386/enqcmd-intel.d: New file. * testsuite/gas/i386/enqcmd-inval.l: Likewise. * testsuite/gas/i386/enqcmd-inval.s: Likewise. * testsuite/gas/i386/enqcmd.d: Likewise. * testsuite/gas/i386/enqcmd.s: Likewise. * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise. * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise. * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise. * testsuite/gas/i386/x86-64-enqcmd.d: Likewise. * testsuite/gas/i386/x86-64-enqcmd.s: Likewise. * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval, enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval, and x86-64-enqcmd. opcodes/ChangeLog: 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (enum): Add MOD_0F38F8_PREFIX_1 and MOD_0F38F8_PREFIX_3. (prefix_table): New instructions (see prefix above). (mod_table): New instructions (see prefix above). * i386-gen.c (cpu_flag_init): Add entries for enqcmd. (cpu_flags): Add a bitfield for enqmcd. * i386-init.h: Regenerated. * i386-opc.h (enum): Add CpuENQCMD. (i386_cpu_flags): Add a bitfield for cpuenqcmd. * i386-opc.tbl: Add enqcmd and enqcmds instructions. * i386-init.h: Regenerated. * i386-tbl.h: Regenerated.
2019-05-24aarch64: handle .variant_pcs directive in gasSzabolcs Nagy1-0/+6
In ELF objects the specified symbol is marked with STO_AARCH64_VARIANT_PCS. gas/ChangeLog: * config/tc-aarch64.c (s_variant_pcs): New function. * doc/c-aarch64.texi: Document .variant_pcs. * testsuite/gas/aarch64/symbol-variant_pcs-1.d: New test. * testsuite/gas/aarch64/symbol-variant_pcs-1.s: New test. * testsuite/gas/aarch64/symbol-variant_pcs-2.d: New test. * testsuite/gas/aarch64/symbol-variant_pcs-2.s: New test.
2019-05-23gas: add support for eBPFJose E. Marchesi5-0/+402
This patch adds a port for the Linux kernel eBPF to the GNU assembler. A testsuite and documentation updates are included. gas/ChangeLog: 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com> * configure.ac: Handle bpf-*-* targets. * configure.tgt (generic_target): Likewise. * configure: Regenerate. * Makefile.am (TARGET_CPU_CFILES): Add tc-bpf.c. (TARGET_CPU_HFILES): Add tc-bpf.h. * Makefile.in: Regenerated. * config/tc-bpf.c: New file. * config/tc-bpf.h: Likewise. * doc/Makefile.am (CPU_DOCS): Add c-bpf.texi. * doc/Makefile.in: Regenerated. * doc/all.texi: set BPF. * doc/as.texi: Add eBPF contents. * doc/c-bpf.texi: New file. * testsuite/gas/bpf/alu.d: New file. * testsuite/gas/bpf/mem-be.d: Likewise. * testsuite/gas/bpf/mem.s: Likewise. * testsuite/gas/bpf/mem.d: Likewise. * testsuite/gas/bpf/lddw-be.d: Likewise. * testsuite/gas/bpf/lddw.s: Likewise. * testsuite/gas/bpf/lddw.d: Likewise. * testsuite/gas/bpf/jump-be.d: Likewise. * testsuite/gas/bpf/jump.s: Likewise. * testsuite/gas/bpf/jump.d: Likewise. * testsuite/gas/bpf/exit-be.d: Likewise. * testsuite/gas/bpf/exit.s: Likewise. * testsuite/gas/bpf/exit.d: Likewise. * testsuite/gas/bpf/call-be.d: Likewise. * testsuite/gas/bpf/call.s: Likewise. * testsuite/gas/bpf/call.d: Likewise. * testsuite/gas/bpf/bpf.exp: Likewise. * testsuite/gas/bpf/atomic-be.d: Likewise. * testsuite/gas/bpf/atomic.s: Likewise. * testsuite/gas/bpf/atomic.d: Likewise. * testsuite/gas/bpf/alu-be.d: Likewise. * testsuite/gas/bpf/alu32-be.d: Likewise. * testsuite/gas/bpf/alu32.s: Likewise. * testsuite/gas/bpf/alu32.d: Likewise. * testsuite/gas/bpf/alu.s: Likewise. * testsuite/gas/all/gas.exp: Introduce a nop_type for eBPF. * testsuite/gas/all/org-1.s: Support nop_type 6. * testsuite/gas/all/org-1.l: Updated to reflect changes in org-1.s.
2019-05-22S12Z: GAS: New option --mdollar-hex.John Darrington1-0/+13
This option (also implied by --traditional) causes '$' to introduce literal hexadecimal constants, rather than the modern convention '0x'. gas/ * config/tc-s12z.c (s12z_strtol): New function. (md_show_usage): Update. (md_parse_option): new case OPTION_DOLLAR_HEX. (s12z_init_after_args): (<global>): Use s12z_strtol instead of strtol. * doc/c-s12z.texi (S12Z Options): Document new option -mdollar-hex. * testsuite/gas/s12z/dollar-hex.d: New file. * testsuite/gas/s12z/dollar-hex.s: New file. * testsuite/gas/s12z/s12z.exp: Add them.
2019-05-18S12Z (doc): Minor improvements to text and formatting.John Darrington1-53/+47
gas/ * doc/c-s12z.texi: Miscellaneous adjustments.
2019-05-17GAS (documentation): Remove trademark acknowledgements.John Darrington2-2/+2
GNU policy is not to include trademark acknowlegements in documentation [1] [1] https://www.gnu.org/prep/standards/html_node/Trademarks.html Committing as obvious. gas/ * doc/c-arm.texi (ARM Options): Remove "(r)" and "(tm)" * doc/c-bfin.texi (Blackfin Syntax): Remove "(r)"
2019-05-16[PATCH 1/57][Arm][GAS]: Add support for +mve and +mve.fpAndre Vieira1-1/+6
bfd/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * elf32-arm.c (elf32_arm_merge_eabi_attributes): Add case for Tag_MVE_arch. binutils/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * readelf.c (arm_attr_tag_MVE_arch): New array for Tag_MVE_arch values. (arm_attr_public_tag arm_attr_public_tags): Add case for Tag_MVE_arch. elfcpp/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * arm.h (Tag_MVE_arch): Define new enum value. gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (mve_ext, mve_fp_ext): New features. (armv8_1m_main_ext_table): Add new extensions. (aeabi_set_public_attributes): Translate new features to new build attributes. (arm_convert_symbolic_attribute): Add Tag_MVE_arch. * doc/c-arm.texi: Document new extensions and new build attribute. include/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * elf/arm.h (Tag_MVE_arch): Define new enum value. * opcode/arm.h (FPU_MVE, FPU_MVE_FP): New MACROs for new features.
2019-05-15S12Z: New option -mreg-prefixJohn Darrington1-9/+77
Add a new machine dependent option to set a prefix for register names. gas/ * config/tc-s12z.c (register_prefix): New variable. (md_show_usage, md_parse_option): parse the new option. (lex_reg_name): Scan the prefix if one is set. * doc/c-s12z.texi (S12Z-Opts): Document the new option. * testsuite/gas/s12z/reg-prefix.d: New file. * testsuite/gas/s12z/reg-prefix.s: New file. * testsuite/gas/s12z/s12z.exp: Add them.
2019-05-15GAS (doc): Fix misaligned menu entry.John Darrington1-1/+1
gas/ * doc/as.texi (Machine Dependencies): Fix misaligned menu entry.
2019-05-09[binutils][aarch64] SVE2 feature extension flags.Matthew Malcomson1-0/+10
Include all feature flag macros. The "sve2" extension that enables the core sve2 instructions. This also enables the sve extension, since sve is a requirement of sve2. Extra optional sve2 features are the bitperm, sm4, aes, and sha3 extensions. These are all given extra feature flags, "bitperm", "sve2-sm4", "sve2-aes", and "sve2-sha3" respectively. The sm4, aes, and sha3 extensions are explicitly marked as sve2 extensions to distinguish them from the corresponding NEON extensions. Rather than continue extending the current feature flag numbers, I used some bits that have been skipped. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c: Add command line architecture feature flags "sve2", "sve2-sm4", "sve2-aes", "sve2-sha3", "bitperm". * doc/c-aarch64.texi: Document new architecture feature flags. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_SVE2 AARCH64_FEATURE_SVE2_AES, AARCH64_FEATURE_SVE2_BITPERM, AARCH64_FEATURE_SVE2_SM4, AARCH64_FEATURE_SVE2_SHA3): New feature macros. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-tbl.h (aarch64_feature_sve2, aarch64_feature_sve2aes, aarch64_feature_sve2sha3, aarch64_feature_sve2sm4, aarch64_feature_sve2bitperm): New feature sets. (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros for feature set addresses. (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN, SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
2019-05-01[BINUTILS, AArch64] Enable Transactional Memory ExtensionSudakshina Das1-0/+2
This patch enables the new Transactional Memory Extension added recently as part of Arm's new architecture technologies. We introduce a new optional extension "tme" to enable this. The following instructions are part of the extension: * tstart <Xt> * ttest <Xt> * tcommit * tcancel #<imm> The ISA for the above can be found here: https://developer.arm.com/docs/ddi0602/latest/base-instructions-alphabetic-order *** gas/ChangeLog *** 2019-05-01 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_operands): Add case for AARCH64_OPND_TME_UIMM16. (aarch64_features): Add "tme". * doc/c-aarch64.texi: Document the same. * testsuite/gas/aarch64/tme-invalid.d: New test. * testsuite/gas/aarch64/tme-invalid.l: New test. * testsuite/gas/aarch64/tme-invalid.s: New test. * testsuite/gas/aarch64/tme.d: New test. * testsuite/gas/aarch64/tme.s: New test. *** include/ChangeLog *** 2019-05-01 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_TME): New. (enum aarch64_opnd): Add AARCH64_OPND_TME_UIMM16. *** opcodes/ChangeLog *** 2019-05-01 Sudakshina Das <sudi.das@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Add case for AARCH64_OPND_TME_UIMM16. (aarch64_print_operand): Likewise. * aarch64-tbl.h (QL_IMM_NIL): New. (TME): New. (_TME_INSN): New. (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
2019-04-15[GAS, ARM, 2/16] Add CLI extension support for Armv8.1-M MainlineAndre Vieira1-0/+11
This patch implements the dsp, fp and fp.dp extensions for Armv8.1-M Mainline. This patch also removes the fp-armv8 check from the half-precision move instructions 'do_neon_movhf', as checking that the FP16 instructions extension feature bit is enabled 'ARM_EXT2_FP16_INST' is enough. gas/ChangeLog: 2019-04-15 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (do_neon_movhf): Remove fp-armv8 check. (armv8_1m_main_ext_table): New extension table. (arm_archs): Use the new extension table. * doc/c-arm.texi: Add missing arch and document new extensions. * testsuite/gas/arm/armv8.1-m.main-fp.d: New. * testsuite/gas/arm/armv8.1-m.main-fp-dp.d: New. * testsuite/gas/arm/armv8.1-m.main-hp.d: New.
2019-04-13[MIPS] Add i6500 CPU and fix i6400 default ASEsMatthew Fortune1-0/+1
gas/ * config/tc-mips.c (mips_cpu_info_table): Add i6500. Update default ASEs for i6400. * doc/c-mips.texi (-march): Document i6500. * testsuite/gas/mips/elf_mach_i6400.d: New test. * testsuite/gas/mips/elf_mach_i6500.d: New test. * testsuite/gas/mips/mips.exp: Run the new tests.
2019-04-05x86: Support Intel AVX512 BF16Xuepeng Guo1-1/+3
Add assembler and disassembler support Intel AVX512 BF16: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference gas/ 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com> * config/tc-i386.c (cpu_arch): Add .avx512_bf16. (cpu_noarch): Add noavx512_bf16. * doc/c-i386.texi: Document avx512_bf16. * testsuite/gas/i386/avx512_bf16.d: New file. * testsuite/gas/i386/avx512_bf16.s: Likewise. * testsuite/gas/i386/avx512_bf16_vl-inval.l: Likewise. * testsuite/gas/i386/avx512_bf16_vl-inval.s: Likewise. * testsuite/gas/i386/avx512_bf16_vl.d: Likewise. * testsuite/gas/i386/avx512_bf16_vl.s: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16.d: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16.s: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.l: Likesie. * testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.s: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16_vl.s: Likewise. * testsuite/gas/i386/i386.exp: Add BF16 related tests. opcodes/ 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com> * i386-dis-evex.h (evex_table): Updated to support BF16 instructions. * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1 and EVEX_W_0F3872_P_3. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS. (cpu_flags): Add bitfield for CpuAVX512_BF16. * i386-opc.h (enum): Add CpuAVX512_BF16. (i386_cpu_flags): Add bitfield for cpuavx512_bf16. * i386-opc.tbl: Add AVX512 BF16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2019-04-01[GAS, Arm] CLI with architecture sensitive extensionsAndre Vieira1-3/+164
This patch adds a new framework to add architecture sensitive extensions, like GCC does. This patch also implements all architecture extensions currently available in GCC. This framework works as follows. To enable architecture sensitive extensions for a particular architecture, that architecture must contain an ARM_ARCH_OPT2 entry in the 'arm_archs' table. All fields here are the same as previous, with the addition of a new extra field at the end to <name> it's extension table. This <name>, corresponds to a <name>_ext_table of type 'struct arm_ext_table'. This struct can be filled with three types of entries: ARM_ADD (string <ext>, arm_feature_set <enable_bits>), which means +<ext> will enable <enable_bits> ARM_REMOVE (string <ext>, arm_feature_set <disable_bits>), which means +no<ext> will disable <disable_bits> ARM_EXT (string <ext>, arm_feature_set <enable_bits>, arm_feature_set <disable_bits>), which means +<ext> will enable <enable_bits> and +no<ext> will disable <disable_bits> (this is to be used instead of adding an ARM_ADD and ARM_REMOVE for the same <ext>) This patch does not disable the use of the old extensions, even if some of them are duplicated in the new tables. This is a "in-between-step" as we may want to deprecate the old table of extensions in later patches. For now, GAS will first look for the +<ext> or +no<ext> in the new table and if no entry is found it will continue searching in the old table, following old behaviour. If only an ARM_ADD or an ARM_REMOVE is defined for <ext> and +no<ext> or +<ext> resp. is used then it also continues to search the old table for it. A couple of caveats: - This patch does not enable the use of these architecture extensions with the '.arch_extension' directive. This is future work that I will tend to later. - This patch does not enable the use of these architecture extensions with the -mcpu option. This is future work that I will tend to later. - This patch does not change the current behaviour when combining an architecture extension and using -mfpu on the command-line. The current behaviour of GAS is to stage the union of feature bits enabled by both -march and -mfpu. GCC behaves differently here, so this is something we may want to revisit on a later date.
2019-03-18x86: Optimize EVEX vector load/store instructionsH.J. Lu1-1/+3
When there is no write mask, we can encode lower 16 128-bit/256-bit EVEX vector register load and store instructions as VEX vector register load and store instructions with -O1. gas/ PR gas/24348 * config/tc-i386.c (optimize_encoding): Encode 128-bit and 256-bit EVEX vector register load/store instructions as VEX vector register load/store instructions for -O1. * doc/c-i386.texi: Update -O1 documentation. * testsuite/gas/i386/i386.exp: Run PR gas/24348 tests. * testsuite/gas/i386/optimize-1.s: Add tests for EVEX vector load/store instructions. * testsuite/gas/i386/optimize-2.s: Likewise. * testsuite/gas/i386/optimize-3.s: Likewise. * testsuite/gas/i386/optimize-5.s: Likewise. * testsuite/gas/i386/x86-64-optimize-2.s: Likewise. * testsuite/gas/i386/x86-64-optimize-3.s: Likewise. * testsuite/gas/i386/x86-64-optimize-4.s: Likewise. * testsuite/gas/i386/x86-64-optimize-5.s: Likewise. * testsuite/gas/i386/x86-64-optimize-6.s: Likewise. * testsuite/gas/i386/optimize-1.d: Updated. * testsuite/gas/i386/optimize-2.d: Likewise. * testsuite/gas/i386/optimize-3.d: Likewise. * testsuite/gas/i386/optimize-4.d: Likewise. * testsuite/gas/i386/optimize-5.d: Likewise. * testsuite/gas/i386/x86-64-optimize-2.d: Likewise. * testsuite/gas/i386/x86-64-optimize-3.d: Likewise. * testsuite/gas/i386/x86-64-optimize-4.d: Likewise. * testsuite/gas/i386/x86-64-optimize-5.d: Likewise. * testsuite/gas/i386/x86-64-optimize-6.d: Likewise. * testsuite/gas/i386/optimize-7.d: New file. * testsuite/gas/i386/optimize-7.s: Likewise. * testsuite/gas/i386/x86-64-optimize-8.d: Likewise. * testsuite/gas/i386/x86-64-optimize-8.s: Likewise. opcodes/ PR gas/24348 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32 and vmovdqu64. * i386-tbl.h: Regenerated.
2019-03-18x86: Encode 256-bit/512-bit VEX/EVEX insns with 128-bit VEXH.J. Lu1-4/+6
Since all AVX512 processors support AVX, we can encode 256-bit/512-bit VEX/EVEX vector register clearing instructions with 128-bit VEX vector register clearing instructions at -O1. * config/tc-i386.c (optimize_encoding): Encode 256-bit/512-bit VEX/EVEX vector register clearing instructions with 128-bit VEX vector register clearing instructions at -O1. * doc/c-i386.texi: Update -O1 and -O2 documentation. * testsuite/gas/i386/i386.exp: Run optimize-1a and x86-64-optimize-2a. * testsuite/gas/i386/optimize-1a.d: New file. * testsuite/gas/i386/x86-64-optimize-2a.d: Likewise.
2019-02-22[arm][gas] Add support for Neoverse N1Kyrylo Tkachov1-0/+1
This adds support for the Neoverse N1 CPU [1] to gas. This was previously enabled under the Ares codename, which remains as a valid option for -mcpu for compatibility reasons. make check-gas passes on arm-none-eabi. [1] https://community.arm.com/processors/b/blog/posts/arm-neoverse-n1-platform-accelerating-the-transformation-to-a-scalable-cloud-to-edge-infrastructure 2019-02-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/tc-arm.c (arm_cpus): Add neoverse-n1. * doc/c-arm.texi (-mcpu): Document neoverse-n1 value.
2019-02-22[AArch64][gas] Add support for Neoverse E1Kyrylo Tkachov1-0/+1
This adds support for the Neoverse E1 CPU [1] to gas. make check-gas passes on aarch64-none-elf. [1] https://community.arm.com/processors/b/blog/posts/arm-neoverse-e1-platform-empowering-the-infrastructure-to-meet-next-generation-throughput-demands 2019-02-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/tc-aarch64.c (aarch64_cpus): Add neoverse-e1. * doc/c-aarch64.texi (-mcpu): Document neoverse-e1 value.
2019-02-22[AArch64][gas] Add support for Neoverse N1Kyrylo Tkachov1-0/+1
This adds support for the Neoverse N1 [1] CPU to gas. This was previously enabled under the Ares codename, which remains as a valid option for -mcpu for compatibility reasons. make check-gas passes on aarch64-none-elf. [1] https://community.arm.com/processors/b/blog/posts/arm-neoverse-n1-platform-accelerating-the-transformation-to-a-scalable-cloud-to-edge-infrastructure 2019-02-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/tc-aarch64.c (aarch64_cpus): Add neoverse-n1. * doc/c-aarch64.texi (-mcpu): Document neoverse-n1 value.
2019-02-19Fix a potential deadlock in some older Loongson 3A1000 MIPS processors.Paul Hua1-0/+7
* NEWS: Mention -m[no-]fix-loongson3-llsc. * configure.ac: Add --enable-mips-fix-loongson3-llsc. Define DEFAULT_MIPS_FIX_LOONGSON3_LLSC. * config.in: Regenerated. * configure: Likewise. * config/tc-mips.c (sync_insn, mips_fix_loongson3_llsc): New variables. (options): New OPTION_FIX_LOONGSON3_LLSC, OPTION_NO_FIX_LOONGSON3_LLSC. (md_longopts): Add -m[no-]fix-loongson3-llsc. (md_begin): Initialize sync insn. (fix_loongson3_llsc): New. (append_insn): Call fix_loongson3_llsc. (md_parse_option): Handle OPTION_FIX_LOONGSON3_LLSC, OPTION_NO_FIX_LOONGSON3_LLSC. (md_show_usage): Display -m[no-]fix-loongson3-llsc. * doc/c-mips.texi: Document -m[no-]fix-loongson3-llsc, --enable-mips-fix-loongson3-llsc=[yes|no].
2019-02-10gas: Pass max_bytes to TC_FRAG_INITH.J. Lu1-3/+4
ommit 3ae729d5a4f63740ed9a778960b17c2912b0bbdd Author: H.J. Lu <hjl.tools@gmail.com> Date: Wed Mar 7 04:18:45 2018 -0800 x86: Rewrite NOP generation for fill and alignment increased MAX_MEM_FOR_RS_ALIGN_CODE to 4095 which resulted in increase of assembler time and memory usage by 5 times for inputs with many .p2align directives, which is typical for LTO output. This patch passes max_bytes to TC_FRAG_INIT so that MAX_MEM_FOR_RS_ALIGN_CODE can be set as needed and tracked by backend it so that HANDLE_ALIGN can check the maximum alignment for each rs_align_code frag. Wall time to assemble the same cc1plus.s: before: 423.78user 0.89system 7:05.71elapsed 99%CPU after: 102.35user 0.27system 1:42.89elapsed 99%CPU PR gas/24165 * frags.c (frag_var_init): Pass max_chars to TC_FRAG_INIT as max_bytes. * config/tc-aarch64.h (TC_FRAG_INIT): Add and pass max_bytes to aarch64_init_frag. * /config/tc-arm.h (TC_FRAG_INIT): And and pass max_bytes to arm_init_frag. * config/tc-avr.h (TC_FRAG_INIT): And and ignore max_bytes. * config/tc-ia64.h (TC_FRAG_INIT): Likewise. * config/tc-mmix.h (TC_FRAG_INIT): Likewise. * config/tc-nds32.h (TC_FRAG_INIT): Likewise. * config/tc-ns32k.h (TC_FRAG_INIT): Likewise. * config/tc-rl78.h (TC_FRAG_INIT): Likewise. * config/tc-rx.h (TC_FRAG_INIT): Likewise. * config/tc-score.h (TC_FRAG_INIT): Likewise. * config/tc-tic54x.h (TC_FRAG_INIT): Likewise. * config/tc-tic6x.h (TC_FRAG_INIT): Likewise. * config/tc-xtensa.h (TC_FRAG_INIT): Likewise. * config/tc-i386.h (MAX_MEM_FOR_RS_ALIGN_CODE): Set to (alignment ? ((1 << alignment) - 1) : 1) (i386_tc_frag_data): Add max_bytes. (TC_FRAG_INIT): Add and track max_bytes. (HANDLE_ALIGN): Replace MAX_MEM_FOR_RS_ALIGN_CODE with fragP->tc_frag_data.max_bytes. * doc/internals.texi: Update TC_FRAG_TYPE with max_bytes.
2019-01-31S/390: Implement instruction set extensionsAndreas Krebbel1-3/+5
opcodes/ChangeLog: 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> * s390-mkopc.c (main): Accept arch13 as cpu string. * s390-opc.c: Add new instruction formats and instruction opcode masks. * s390-opc.txt: Add new arch13 instructions. include/ChangeLog: 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> * opcode/s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_ARCH13. gas/ChangeLog: 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> * config/tc-s390.c (s390_parse_cpu): New entry for arch13. * doc/c-s390.texi: Document arch13 march option. * testsuite/gas/s390/s390.exp: Run the arch13 related tests. * testsuite/gas/s390/zarch-arch13.d: New test. * testsuite/gas/s390/zarch-arch13.s: New test. * testsuite/gas/s390/zarch-z13.d: Expect the renamed mnemonics also for z13.
2019-01-16RISC-V: Support ELF attribute for gas and readelf.Jim Wilson1-0/+53
2019-01-16 Kito Cheng <kito@andestech.com> Nelson Chu <nelson@andestech.com> bfd/ * elfnn-riscv.c (riscv_elf_obj_attrs_arg_type): New. (elf_backend_obj_attrs_vendor): Define. (elf_backend_obj_attrs_section_type): Likewise. (elf_backend_obj_attrs_section): Likewise. (elf_backend_obj_attrs_arg_type): Define as riscv_elf_obj_attrs_arg_type. * elfxx-riscv.c (riscv_estimate_digit): New. (riscv_estimate_arch_strlen1): Likewise. (riscv_estimate_arch_strlen): Likewise. (riscv_arch_str1): Likewise. (riscv_arch_str): Likewise. * elfxx-riscv.h (riscv_arch_str): Declare. binutils/ * readelf.c (get_riscv_section_type_name): New function. (get_section_type_name): Add handler for RISC-V. (riscv_attr_tag_t): Declare. (riscv_attr_tag): New. (display_riscv_attribute): New function. (process_attributes): Add handler for RISC-V. * testsuite/binutils-all/strip-3.d: Remove .riscv.attribute section. gas/ * config/tc-riscv.c (DEFAULT_RISCV_ATTR): Define to 0 if not defined. (riscv_set_options): Add `arch_attr` field. (riscv_opts): Set default value for arch_attr. (riscv_write_out_arch_attr): New. (riscv_set_public_attributes): Likewise. (riscv_md_end): Likewise. (riscv_convert_symbolic_attribute): Likewise. (s_riscv_attribute): Likewise. (explicit_arch_attr): Likewise. (riscv_pseudo_table): Add .attribute to the table. (options): Add OPTION_ARCH_ATTR and OPTION_NO_ARCH_ATTR enumeration constants. (md_longopts): Add `march-attr' and `mno-arch-attr' options. (md_parse_option): Handle the new options. (md_show_usage): Document the `march-attr' option. * config/tc-riscv.h (md_end): Define as riscv_md_end (riscv_md_end): Declare. (CONVERT_SYMBOLIC_ATTRIBUTE): Define as riscv_convert_symbolic_attribute. (riscv_convert_symbolic_attribute): Declare. (start_assemble): Declare. * testsuite/gas/elf/elf.exp: Adjust test case for section2.e. * testsuite/gas/elf/section2.e-riscv: New. * testsuite/gas/riscv/attribute-01.d: New test * testsuite/gas/riscv/attribute-02.d: Likewise. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/attribute-04.d: Likewise. * testsuite/gas/riscv/attribute-04.s: Likewise. * testsuite/gas/riscv/attribute-05.d: Likewise. * testsuite/gas/riscv/attribute-05.s: Likewise. * testsuite/gas/riscv/attribute-06.d: Likewise. * testsuite/gas/riscv/attribute-06.s: Likewise. * testsuite/gas/riscv/attribute-07.d: Likewise. * testsuite/gas/riscv/attribute-07.s: Likewise. * testsuite/gas/riscv/attribute-08.d: Likewise. * testsuite/gas/riscv/attribute-08.s: Likewise. * testsuite/gas/riscv/attribute-unknown.d: Likewise. * testsuite/gas/riscv/attribute-unknown.s: Likewise. * testsuite/gas/riscv/empty.l: Likewise. * doc/c-riscv.texi (.attribute): Add documentation. * configure.ac (--enable-default-riscv-attribute): New options. * configure: Re-generate. * config.in: Re-generate. include/ * elf/riscv.h (SHT_RISCV_ATTRIBUTES): Define. (Tag_RISCV_arch): Likewise. (Tag_RISCV_priv_spec): Likewise. (Tag_RISCV_priv_spec_minor): Likewise. (Tag_RISCV_priv_spec_revision): Likewise. (Tag_RISCV_unaligned_access): Likewise. (Tag_RISCV_stack_align): Likewise.
2019-01-08[AArch64][gas] Add -mcpu support for Arm AresKyrylo Tkachov1-0/+1
This adds support for the Arm Ares CPU for AArch64. It implements the Armv8.2-A architecture with the optional features of statistical profiling, dot product and FP16 on by default. Note: Ares is a codename to enable early adopters and in time we will add the final product name once it's announced. * config/tc-aarch64.c (aarch64_cpus): Add ares. * doc/c-aarch64.texi (-mcpu): Document ares value.
2019-01-07[arm][gas] Add -mcpu support for Arm AresKyrylo Tkachov1-0/+1
This adds support for the Arm Ares CPU in the arm port. It implements the Armv8.2-A architecture with the relevant optional features of dot product and FP16 on by default. Note: Ares is a codename to enable early adopters and in time we will add the final product name once it's announced. * config/tc-arm.c (arm_cpus): Add ares. * doc/c-arm.texi (-mcpu): Document ares value.
2019-01-05RX: gas - Add RXv3 instruction support.Yoshinori Sato1-4/+4
Instruction manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01us0316ej0100-rxv3sm.pdf * config/rx-defs.h (rx_cpu_types): Add type RXV3 and RXV3FPU. (rx_bfield): Add prototype. (rx_post): Likewise. * config/rx-parse.y: Add v3 instructions and Double FPU registers. (DSIZE): Define. (POST): Define. (rx_check_v3): New. check v3 type. (rx_check_dfpu): New. check have double support. (double_condition_table): New. dcmp<cond> contiditon. (check_condition): Multiple condition support. (rx_lex): RXv3 instructions support. Add parse dcmp<cond> instruction and Double FPU registers. (immediate): Disable optimize in dmov #imm case. (displacement): Add double displacement in dmov instraction. * config/tc-rx.c (rx_use_conventional_section_names): Invert default value in rx-*-linux target. (cpu_type): Add additional ELF flags. (cpu_type_list): Add RXv3. (md_parse_option): Refer elf_flags from cpu_type_list. (md_show_usage): Add rxv3 and rxv3-dfpu. (rx_bytesT): Add post byte. (rx_bfield): New. generate bfmov / bfmovz "imm" field. (rx_post): New. Set instruction post byte. (md_assemble): Add post byte. doc/c-rx.texi: Add cpu types. * testsuite/gas/rx/Xtod.d: New. * testsuite/gas/rx/Xtod.sm: New. * testsuite/gas/rx/bfmov.d: New. * testsuite/gas/rx/bfmov.sm: New. * testsuite/gas/rx/dabs.d: New. * testsuite/gas/rx/dabs.sm: New. * testsuite/gas/rx/dadd.d: New. * testsuite/gas/rx/dadd.sm: New. * testsuite/gas/rx/dcmp.d: New. * testsuite/gas/rx/dcmp.sm: New. * testsuite/gas/rx/ddiv.d: New. * testsuite/gas/rx/ddiv.sm: New. * testsuite/gas/rx/dmov.d: New. * testsuite/gas/rx/dmov.sm: New. * testsuite/gas/rx/dmul.d: New. * testsuite/gas/rx/dmul.sm: New. * testsuite/gas/rx/dneg.d: New. * testsuite/gas/rx/dneg.sm: New. * testsuite/gas/rx/dpopm.d: New. * testsuite/gas/rx/dpopm.sm: New. * testsuite/gas/rx/dpushm.d: New. * testsuite/gas/rx/dpushm.sm: New. * testsuite/gas/rx/dround.d: New. * testsuite/gas/rx/dround.sm: New. * testsuite/gas/rx/dsqrt.d: New. * testsuite/gas/rx/dsqrt.sm: New. * testsuite/gas/rx/dsub.d: New. * testsuite/gas/rx/dsub.sm: New. * testsuite/gas/rx/dtoX.d: New. * testsuite/gas/rx/dtoX.sm: New. * testsuite/gas/rx/macros.inc: Add double FPU registers. * testsuite/gas/rx/mvfdc.d: New. * testsuite/gas/rx/mvfdc.sm: New. * testsuite/gas/rx/mvfdr.d: New. * testsuite/gas/rx/mvfdr.sm: New. * testsuite/gas/rx/mvtdc.d: New. * testsuite/gas/rx/mvtdc.sm: New. * testsuite/gas/rx/rstr.d: New. * testsuite/gas/rx/rstr.sm: New. * testsuite/gas/rx/rx.exp: Use rxv3-dfpu option. * testsuite/gas/rx/save.d: New. * testsuite/gas/rx/save.sm: New. * testsuite/gas/rx/xor.d: New. * testsuite/gas/rx/xor.sm: Add pattern.
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