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| author | H.J. Lu <hjl.tools@gmail.com> | 2019-03-18 03:50:45 +0800 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2019-03-18 03:51:50 +0800 |
| commit | 99112332cda2e63d33959ac8ea2ed13524b09bd6 (patch) | |
| tree | 5dc762d698d2a2b62d4552a505516c7b91b78b76 /gas/doc | |
| parent | d4cbef22ba406707a4fcb30a7a57308447626f14 (diff) | |
| download | gdb-99112332cda2e63d33959ac8ea2ed13524b09bd6.zip gdb-99112332cda2e63d33959ac8ea2ed13524b09bd6.tar.gz gdb-99112332cda2e63d33959ac8ea2ed13524b09bd6.tar.bz2 | |
x86: Encode 256-bit/512-bit VEX/EVEX insns with 128-bit VEX
Since all AVX512 processors support AVX, we can encode 256-bit/512-bit
VEX/EVEX vector register clearing instructions with 128-bit VEX vector
register clearing instructions at -O1.
* config/tc-i386.c (optimize_encoding): Encode 256-bit/512-bit
VEX/EVEX vector register clearing instructions with 128-bit VEX
vector register clearing instructions at -O1.
* doc/c-i386.texi: Update -O1 and -O2 documentation.
* testsuite/gas/i386/i386.exp: Run optimize-1a and
x86-64-optimize-2a.
* testsuite/gas/i386/optimize-1a.d: New file.
* testsuite/gas/i386/x86-64-optimize-2a.d: Likewise.
Diffstat (limited to 'gas/doc')
| -rw-r--r-- | gas/doc/c-i386.texi | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 6c63560..7e5f5c2 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -453,10 +453,12 @@ Intel64 ISA in 64-bit mode. The default is to accept both. Optimize instruction encoding with smaller instruction size. @samp{-O} and @samp{-O1} encode 64-bit register load instructions with 64-bit immediate as 32-bit register load instructions with 31-bit or 32-bits -immediates and encode 64-bit register clearing instructions with 32-bit -register clearing instructions. @samp{-O2} includes @samp{-O1} -optimization plus encodes 256-bit and 512-bit vector register clearing -instructions with 128-bit vector register clearing instructions. +immediates, encode 64-bit register clearing instructions with 32-bit +register clearing instructions and encode 256-bit/512-bit VEX/EVEX +vector register clearing instructions with 128-bit VEX vector register +clearing instructions. @samp{-O2} includes @samp{-O1} optimization plus +encodes 256-bit/512-bit EVEX vector register clearing instructions with +128-bit EVEX vector register clearing instructions. @samp{-Os} includes @samp{-O2} optimization plus encodes 16-bit, 32-bit and 64-bit register tests with immediate as 8-bit register test with immediate. @samp{-O0} turns off this optimization. |