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| author | Jan Beulich <jbeulich@suse.com> | 2019-07-01 08:31:14 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2019-07-01 08:31:14 +0200 |
| commit | a0a1771e895e6606a2a795c407e20aed73f69bd9 (patch) | |
| tree | 9b75ffcdaa3d8b5f343c148821ddb4da987aa88d /gas/doc | |
| parent | cd546e7bd2832c882e69809fdbeb7b376b62039e (diff) | |
| download | gdb-a0a1771e895e6606a2a795c407e20aed73f69bd9.zip gdb-a0a1771e895e6606a2a795c407e20aed73f69bd9.tar.gz gdb-a0a1771e895e6606a2a795c407e20aed73f69bd9.tar.bz2 | |
x86: optimize EVEX packed integer logical instructions
As long as there's no write mask as well as no broadcast, and as long
as the scaled Disp8 wouldn't result in a shorter EVEX encoding, encode
VPAND{D,Q}, VPANDN{D,Q}, VPOR{D,Q}, and VPXOR{D,Q} acting on only the
lower 16 XMM/YMM registers using their VEX equivalents with -O1.
Also take the opportunity and avoid looping twice over all operands
when dealing with memory-with-displacement ones.
Diffstat (limited to 'gas/doc')
| -rw-r--r-- | gas/doc/c-i386.texi | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 80bbcbe..ba20067 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -465,13 +465,17 @@ Optimize instruction encoding with smaller instruction size. @samp{-O} and @samp{-O1} encode 64-bit register load instructions with 64-bit immediate as 32-bit register load instructions with 31-bit or 32-bits immediates, encode 64-bit register clearing instructions with 32-bit -register clearing instructions and encode 256-bit/512-bit VEX/EVEX -vector register clearing instructions with 128-bit VEX vector register -clearing instructions as well as encode 128-bit/256-bit EVEX vector +register clearing instructions, encode 256-bit/512-bit VEX/EVEX vector +register clearing instructions with 128-bit VEX vector register +clearing instructions, encode 128-bit/256-bit EVEX vector register load/store instructions with VEX vector register load/store -instructions. @samp{-O2} includes @samp{-O1} optimization plus -encodes 256-bit/512-bit EVEX vector register clearing instructions with -128-bit EVEX vector register clearing instructions. +instructions, and encode 128-bit/256-bit EVEX packed integer logical +instructions with 128-bit/256-bit VEX packed integer logical. + +@samp{-O2} includes @samp{-O1} optimization plus encodes +256-bit/512-bit EVEX vector register clearing instructions with 128-bit +EVEX vector register clearing instructions. + @samp{-Os} includes @samp{-O2} optimization plus encodes 16-bit, 32-bit and 64-bit register tests with immediate as 8-bit register test with immediate. @samp{-O0} turns off this optimization. |