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AgeCommit message (Expand)AuthorFilesLines
2022-11-04Support Intel AVX-NE-CONVERTkonglin11-0/+1
2022-11-02x86: simplify expressions in update_imm()Jan Beulich1-23/+14
2022-11-02RISC-V: Fixed the missing $x+arch when adding odd paddings for alignment.Nelson Chu1-29/+36
2022-11-02Support Intel MSRLISTHu, Lin11-0/+1
2022-11-02Support Intel WRMSRNSHu, Lin11-0/+1
2022-11-02Add handler for more i386_cpu_flagsKong Lingling1-0/+17
2022-11-02Support Intel CMPccXADDHaochen Jiang1-1/+2
2022-11-02Support Intel AVX-VNNI-INT8Cui,Lili1-0/+1
2022-11-02Support Intel AVX-IFMAHongyu Wang1-0/+1
2022-10-31x86: minor improvements to optimize_imm() (part III)Jan Beulich1-9/+8
2022-10-31x86: Silence GCC 12 warning on tc-i386.cH.J. Lu1-1/+1
2022-10-31Support Intel PREFETCHICui, Lili1-3/+8
2022-10-29RISC-V: Always generate mapping symbols at the start of the sections.Nelson Chu1-13/+0
2022-10-28RISC-V: Improve "bits undefined" diagnosticsTsukasa OI1-2/+2
2022-10-28RISC-V: Fallback for instructions longer than 64bTsukasa OI1-5/+8
2022-10-28RISC-V/gas: fix build with certain gcc versionsJan Beulich1-7/+7
2022-10-28RISC-V: Fix build failure for -Werror=maybe-uninitializedTsukasa OI1-1/+1
2022-10-28RISC-V: Output mapping symbols with ISA string.Nelson Chu2-37/+131
2022-10-27PowerPC: Add support for RFC02658 - MMA+ Outer-Product InstructionsPeter Bergner1-2/+1
2022-10-27PowerPC: Add support for RFC02653 - Dense Math FacilityPeter Bergner1-1/+12
2022-10-21Support Intel AMX-FP16Cui,Lili1-0/+1
2022-10-20x86: Check VEX/EVEX encoding before checking vector operandsH.J. Lu1-4/+4
2022-10-20x86: re-work AVX-VNNI supportJan Beulich1-6/+0
2022-10-19aarch64-pe support for LD, GAS and BFDJedidiah Thompson4-24/+76
2022-10-16PowerPC se_rfmci and VLE, SPE2 and LSP insns with -manyAlan Modra1-56/+40
2022-10-14e200 LSP supportAlan Modra1-0/+24
2022-10-12x86: drop "regmask" static variableJan Beulich1-3/+2
2022-10-05x86/gas: support quoted address scale factor in AT&T syntaxJan Beulich1-12/+19
2022-10-04RISC-V/gas: allow generating up to 176-bit instructions with .insnJan Beulich1-6/+26
2022-10-04RISC-V/gas: don't open-code insn_length()Jan Beulich1-1/+1
2022-10-04RISC-V/gas: drop stray call to install_insn()Jan Beulich1-1/+0
2022-10-04RISC-V/gas: drop riscv_subsets static variableJan Beulich1-18/+14
2022-10-04RISC-V: don't cast expressions' X_add_number to long in diagnosticsJan Beulich1-4/+4
2022-10-03RISC-V: Assign DWARF numbers to vector registersTsukasa OI1-0/+3
2022-09-30RISC-V: Eliminate long-casts of X_add_number in diagnosticsChristoph Müllner1-8/+8
2022-09-30RISC-V: fix build after "Add support for arbitrary immediate encoding formats"Jan Beulich1-4/+4
2022-09-30x86: improve match_template()'s diagnosticsJan Beulich1-31/+50
2022-09-30x86/Intel: restrict suffix derivationJan Beulich2-61/+85
2022-09-30LoongArch: Update ELF e_flags handling according to specification.liuzhensong1-10/+10
2022-09-28The help document of as misses some many optionsNick Clifton1-1/+2
2022-09-22RISC-V: Add support for literal instruction argumentsChristoph Müllner1-0/+10
2022-09-22RISC-V: Add support for arbitrary immediate encoding formatsChristoph Müllner1-0/+74
2022-09-22RISC-V: Add macro-only operands to validate_riscv_insnTsukasa OI1-0/+3
2022-09-21RISC-V: Fix riscv_set_tso declarationTsukasa OI1-1/+1
2022-09-21RISC-V: Set EF_RISCV_TSO also on .option archTsukasa OI1-0/+3
2022-09-21RISC-V: Implement Ztso extensionShihua1-0/+11
2022-09-21RISC-V: Always generate R_RISCV_CALL_PLT reloc for call in assembler.Nelson Chu1-6/+2
2022-09-21Re: PowerPC64 pcrel got relocs against local symbolsAlan Modra1-6/+52
2022-09-20LoongArch: Set macro SUB_SEGMENT_ALIGN to 0.liuzhensong1-0/+2
2022-09-16PowerPC64 pcrel got relocs against local symbolsAlan Modra1-0/+6
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