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authorChristoph Müllner <christoph.muellner@vrull.eu>2022-07-21 00:26:29 +0200
committerPhilipp Tomsich <philipp.tomsich@vrull.eu>2022-09-22 18:06:09 +0200
commit25236d63fdb138e24cb34aa6c513ae8de2dac7b8 (patch)
treea22052af6988dd1f70eb08d863e9892f093df565 /gas/config
parent27cfd142d0a7e378d19aa9a1278e2137f849b71b (diff)
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RISC-V: Add support for literal instruction arguments
This patch introduces support for arbitrary literal instruction arguments, that are not encoded in the opcode. A typical use case for this feature would be an instruction that applies an implicit shift by a constant value on an immediate (that is a real operand). With this patch it is possible to make this shift visible in the dissasembly and support such artificial parameter as part of the asssembly code. Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'gas/config')
-rw-r--r--gas/config/tc-riscv.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 00e4635..d9f63b1 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1279,6 +1279,9 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
switch (*++oparg)
{
+ case 'l': /* Literal. */
+ oparg += strcspn(oparg, ",") - 1;
+ break;
case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */
goto use_imm;
case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit S. */
@@ -3310,6 +3313,13 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
switch (*++oparg)
{
+ case 'l': /* Literal. */
+ n = strcspn (++oparg, ",");
+ if (strncmp (oparg, asarg, n))
+ as_bad (_("unexpected literal (%s)"), asarg);
+ oparg += n - 1;
+ asarg += n;
+ continue;
case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */
sign = true;
goto parse_imm;