diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/aarch64.h | 16 | ||||
| -rw-r--r-- | include/opcode/riscv-opc.h | 33 | ||||
| -rw-r--r-- | include/opcode/riscv.h | 40 |
3 files changed, 83 insertions, 6 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index dfe3f05..df90bb7 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -704,12 +704,16 @@ enum aarch64_opnd AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */ AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */ AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */ - AARCH64_OPND_SVE_ADDR_R, /* SVE [<Xn|SP>]. */ - AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */ - AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */ - AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */ - AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */ - AARCH64_OPND_SVE_ADDR_RR_LSL4, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #4]. */ + AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>{, <Xm|XZR>}]. */ + AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>{, <Xm|XZR>, LSL #1}]. */ + AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>{, <Xm|XZR>, LSL #2}]. */ + AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>{, <Xm|XZR>, LSL #3}]. */ + AARCH64_OPND_SVE_ADDR_RR_LSL4, /* SVE [<Xn|SP>{, <Xm|XZR>, LSL #4}]. */ + AARCH64_OPND_SVE_ADDR_RM, /* SVE [<Xn|SP>, <Xm|XZR>]. */ + AARCH64_OPND_SVE_ADDR_RM_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */ + AARCH64_OPND_SVE_ADDR_RM_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */ + AARCH64_OPND_SVE_ADDR_RM_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */ + AARCH64_OPND_SVE_ADDR_RM_LSL4, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #4]. */ AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */ AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */ AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */ diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index fea4948..c20cb20 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -3804,6 +3804,25 @@ #define MASK_SFVFNRCLIPXUFQF 0xfe00707f #define MATCH_SFVFNRCLIPXFQF 0x8e00505b #define MASK_SFVFNRCLIPXFQF 0xfe00707f +/* MIPS custom instruction. */ +#define MATCH_MIPS_CCMOV 0x600300b +#define MASK_MIPS_CCMOV 0x600707f +#define MATCH_MIPS_LWP 0x0010400b +#define MASK_MIPS_LWP 0x0030707f +#define MATCH_MIPS_LDP 0x0000400b +#define MASK_MIPS_LDP 0x0070707f +#define MATCH_MIPS_SWP 0x0000508b +#define MASK_MIPS_SWP 0x000071ff +#define MATCH_MIPS_SDP 0x0000500b +#define MASK_MIPS_SDP 0x000073ff +#define MATCH_MIPS_EHB 0x00301013 +#define MASK_MIPS_EHB 0xffffffff +#define MATCH_MIPS_IHB 0x00101013 +#define MASK_MIPS_IHB 0xffffffff +#define MATCH_MIPS_PAUSE 0x00501013 +#define MASK_MIPS_PAUSE 0xffffffff +#define MATCH_MIPS_PREF 0x0000000b +#define MASK_MIPS_PREF 0xe000707f /* Unprivileged Counter/Timers CSR addresses. */ #define CSR_CYCLE 0xc00 #define CSR_TIME 0xc01 @@ -3895,6 +3914,7 @@ #define CSR_MTVEC 0x305 #define CSR_MCOUNTEREN 0x306 #define CSR_MSTATUSH 0x310 +#define CSR_MEDELEGH 0x312 #define CSR_MSCRATCH 0x340 #define CSR_MEPC 0x341 #define CSR_MCAUSE 0x342 @@ -4085,6 +4105,7 @@ #define CSR_HIE 0x604 #define CSR_HCOUNTEREN 0x606 #define CSR_HGEIE 0x607 +#define CSR_HEDELEGH 0x612 #define CSR_HTVAL 0x643 #define CSR_HIP 0x644 #define CSR_HVIP 0x645 @@ -4945,6 +4966,16 @@ DECLARE_INSN(ssamoswap_w, MATCH_SSAMOSWAP_W, MASK_SSAMOSWAP_W) DECLARE_INSN(ssamoswap_d, MATCH_SSAMOSWAP_D, MASK_SSAMOSWAP_D) /* Zicfilp instructions. */ DECLARE_INSN(lpad, MATCH_LPAD, MASK_LPAD) +/* MIPS custom instructions. */ +DECLARE_INSN(mips_ccmov, MATCH_MIPS_CCMOV, MASK_MIPS_CCMOV) +DECLARE_INSN(mips_lwp, MATCH_MIPS_LWP, MASK_MIPS_LWP) +DECLARE_INSN(mips_ldp, MATCH_MIPS_LDP, MASK_MIPS_LDP) +DECLARE_INSN(mips_swp, MATCH_MIPS_SWP, MASK_MIPS_SWP) +DECLARE_INSN(mips_sdp, MATCH_MIPS_SDP, MASK_MIPS_SDP) +DECLARE_INSN(mips_ehb, MATCH_MIPS_EHB, MASK_MIPS_EHB) +DECLARE_INSN(mips_ihb, MATCH_MIPS_IHB, MASK_MIPS_IHB) +DECLARE_INSN(mips_pause, MATCH_MIPS_PAUSE, MASK_MIPS_PAUSE) +DECLARE_INSN(mips_pref, MATCH_MIPS_PREF, MASK_MIPS_PREF) #endif /* DECLARE_INSN */ #ifdef DECLARE_CSR /* Unprivileged Counter/Timers CSRs. */ @@ -5033,6 +5064,7 @@ DECLARE_CSR(mconfigptr, CSR_MCONFIGPTR, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_ DECLARE_CSR(mstatus, CSR_MSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) DECLARE_CSR(misa, CSR_MISA, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) DECLARE_CSR(medeleg, CSR_MEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(medelegh, CSR_MEDELEGH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P13, PRIV_SPEC_CLASS_DRAFT) DECLARE_CSR(mideleg, CSR_MIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) DECLARE_CSR(mie, CSR_MIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) DECLARE_CSR(mtvec, CSR_MTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) @@ -5224,6 +5256,7 @@ DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRI /* Privileged Hypervisor CSRs. */ DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hedelegh, CSR_HEDELEGH, CSR_CLASS_H_32, PRIV_SPEC_CLASS_1P13, PRIV_SPEC_CLASS_DRAFT) DECLARE_CSR(hideleg, CSR_HIDELEG, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(hie, CSR_HIE, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(hcounteren, CSR_HCOUNTEREN, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index d76bcdb..c5dd546 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -132,6 +132,15 @@ static inline unsigned int riscv_insn_length (insn_t insn) ((RV_X(x, 25, 1)) | (RV_X(x, 20, 5) << 1) | (RV_IMM_SIGN_N(x, 20, 5) << 5)) #define EXTRACT_CV_SIMD_UIMM6(x) \ ((RV_X(x, 25, 1)) | (RV_X(x, 20, 5) << 1)) +/* Vendor-specific (MIPS) extract macros. */ +#define EXTRACT_MIPS_LWP_IMM(x) \ + (RV_X(x, 22, 5) << 2) +#define EXTRACT_MIPS_LDP_IMM(x) \ + (RV_X(x, 23, 4) << 3) +#define EXTRACT_MIPS_SWP_IMM(x) \ + ((RV_X(x, 25, 2) << 5) | (RV_X(x, 9, 3) << 2)) +#define EXTRACT_MIPS_SDP_IMM(x) \ + ((RV_X(x, 25, 2) << 5) | (RV_X(x, 10, 2) << 3)) #define ENCODE_ITYPE_IMM(x) \ (RV_X(x, 0, 12) << 20) @@ -200,6 +209,15 @@ static inline unsigned int riscv_insn_length (insn_t insn) ((RV_X(x, 0, 1) << 25) | (RV_X(x, 1, 5) << 20)) #define ENCODE_CV_SIMD_UIMM6(x) \ ((RV_X(x, 0, 1) << 25) | (RV_X(x, 1, 5) << 20)) +/* Vendor-specific (MIPS) encode macros. */ +#define ENCODE_MIPS_LWP_IMM(x) \ + (RV_X(x, 2, 5) << 22) +#define ENCODE_MIPS_LDP_IMM(x) \ + (RV_X(x, 3, 4) << 23) +#define ENCODE_MIPS_SWP_IMM(x) \ + ((RV_X(x, 5, 2) << 25) | (RV_X(x, 2, 3) << 9)) +#define ENCODE_MIPS_SDP_IMM(x) \ + ((RV_X(x, 5, 2) << 25) | (RV_X(x, 3, 2) << 10)) #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x)) #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x)) @@ -383,6 +401,24 @@ static inline unsigned int riscv_insn_length (insn_t insn) #define OP_MASK_XSO1 0x1 #define OP_SH_XSO1 26 +/* MIPS fields. */ +#define OP_MASK_MIPS_IMM9 0x1ff +#define OP_SH_MIPS_IMM9 20 +#define OP_MASK_MIPS_HINT 0x1f +#define OP_SH_MIPS_HINT 7 +#define OP_MASK_MIPS_LWP_OFFSET 0x1f +#define OP_SH_MIPS_LWP_OFFSET 22 +#define OP_MASK_MIPS_LDP_OFFSET 0xf +#define OP_SH_MIPS_LDP_OFFSET 23 +#define OP_MASK_MIPS_SWP_OFFSET9 0x7 +#define OP_SH_MIPS_SWP_OFFSET9 9 +#define OP_MASK_MIPS_SWP_OFFSET25 0x3 +#define OP_SH_MIPS_SWP_OFFSET25 25 +#define OP_MASK_MIPS_SDP_OFFSET10 0x3 +#define OP_SH_MIPS_SDP_OFFSET10 10 +#define OP_MASK_MIPS_SDP_OFFSET25 0x3 +#define OP_SH_MIPS_SDP_OFFSET25 25 + /* ABI names for selected x-registers. */ #define X_RA 1 @@ -563,6 +599,10 @@ enum riscv_insn_class INSN_CLASS_XSFVQMACCQOQ, INSN_CLASS_XSFVQMACCDOD, INSN_CLASS_XSFVFNRCLIPXFQF, + INSN_CLASS_XMIPSCBOP, + INSN_CLASS_XMIPSCMOV, + INSN_CLASS_XMIPSEXECTL, + INSN_CLASS_XMIPSLSP, }; /* This structure holds information for a particular instruction. */ |