diff options
Diffstat (limited to 'include/opcode/riscv-opc.h')
| -rw-r--r-- | include/opcode/riscv-opc.h | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index fea4948..c20cb20 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -3804,6 +3804,25 @@ #define MASK_SFVFNRCLIPXUFQF 0xfe00707f #define MATCH_SFVFNRCLIPXFQF 0x8e00505b #define MASK_SFVFNRCLIPXFQF 0xfe00707f +/* MIPS custom instruction. */ +#define MATCH_MIPS_CCMOV 0x600300b +#define MASK_MIPS_CCMOV 0x600707f +#define MATCH_MIPS_LWP 0x0010400b +#define MASK_MIPS_LWP 0x0030707f +#define MATCH_MIPS_LDP 0x0000400b +#define MASK_MIPS_LDP 0x0070707f +#define MATCH_MIPS_SWP 0x0000508b +#define MASK_MIPS_SWP 0x000071ff +#define MATCH_MIPS_SDP 0x0000500b +#define MASK_MIPS_SDP 0x000073ff +#define MATCH_MIPS_EHB 0x00301013 +#define MASK_MIPS_EHB 0xffffffff +#define MATCH_MIPS_IHB 0x00101013 +#define MASK_MIPS_IHB 0xffffffff +#define MATCH_MIPS_PAUSE 0x00501013 +#define MASK_MIPS_PAUSE 0xffffffff +#define MATCH_MIPS_PREF 0x0000000b +#define MASK_MIPS_PREF 0xe000707f /* Unprivileged Counter/Timers CSR addresses. */ #define CSR_CYCLE 0xc00 #define CSR_TIME 0xc01 @@ -3895,6 +3914,7 @@ #define CSR_MTVEC 0x305 #define CSR_MCOUNTEREN 0x306 #define CSR_MSTATUSH 0x310 +#define CSR_MEDELEGH 0x312 #define CSR_MSCRATCH 0x340 #define CSR_MEPC 0x341 #define CSR_MCAUSE 0x342 @@ -4085,6 +4105,7 @@ #define CSR_HIE 0x604 #define CSR_HCOUNTEREN 0x606 #define CSR_HGEIE 0x607 +#define CSR_HEDELEGH 0x612 #define CSR_HTVAL 0x643 #define CSR_HIP 0x644 #define CSR_HVIP 0x645 @@ -4945,6 +4966,16 @@ DECLARE_INSN(ssamoswap_w, MATCH_SSAMOSWAP_W, MASK_SSAMOSWAP_W) DECLARE_INSN(ssamoswap_d, MATCH_SSAMOSWAP_D, MASK_SSAMOSWAP_D) /* Zicfilp instructions. */ DECLARE_INSN(lpad, MATCH_LPAD, MASK_LPAD) +/* MIPS custom instructions. */ +DECLARE_INSN(mips_ccmov, MATCH_MIPS_CCMOV, MASK_MIPS_CCMOV) +DECLARE_INSN(mips_lwp, MATCH_MIPS_LWP, MASK_MIPS_LWP) +DECLARE_INSN(mips_ldp, MATCH_MIPS_LDP, MASK_MIPS_LDP) +DECLARE_INSN(mips_swp, MATCH_MIPS_SWP, MASK_MIPS_SWP) +DECLARE_INSN(mips_sdp, MATCH_MIPS_SDP, MASK_MIPS_SDP) +DECLARE_INSN(mips_ehb, MATCH_MIPS_EHB, MASK_MIPS_EHB) +DECLARE_INSN(mips_ihb, MATCH_MIPS_IHB, MASK_MIPS_IHB) +DECLARE_INSN(mips_pause, MATCH_MIPS_PAUSE, MASK_MIPS_PAUSE) +DECLARE_INSN(mips_pref, MATCH_MIPS_PREF, MASK_MIPS_PREF) #endif /* DECLARE_INSN */ #ifdef DECLARE_CSR /* Unprivileged Counter/Timers CSRs. */ @@ -5033,6 +5064,7 @@ DECLARE_CSR(mconfigptr, CSR_MCONFIGPTR, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_ DECLARE_CSR(mstatus, CSR_MSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) DECLARE_CSR(misa, CSR_MISA, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) DECLARE_CSR(medeleg, CSR_MEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(medelegh, CSR_MEDELEGH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P13, PRIV_SPEC_CLASS_DRAFT) DECLARE_CSR(mideleg, CSR_MIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) DECLARE_CSR(mie, CSR_MIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) DECLARE_CSR(mtvec, CSR_MTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) @@ -5224,6 +5256,7 @@ DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRI /* Privileged Hypervisor CSRs. */ DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hedelegh, CSR_HEDELEGH, CSR_CLASS_H_32, PRIV_SPEC_CLASS_1P13, PRIV_SPEC_CLASS_DRAFT) DECLARE_CSR(hideleg, CSR_HIDELEG, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(hie, CSR_HIE, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(hcounteren, CSR_HCOUNTEREN, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) |