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| author | Maciej W. Rozycki <macro@orcam.me.uk> | 2021-05-29 03:26:32 +0200 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@orcam.me.uk> | 2021-05-29 03:26:32 +0200 |
| commit | cccc84faff88135ea118250d1b19cfb7aac7e8c1 (patch) | |
| tree | 1f4022bf2b69b21b17daa41f06df559fd7200a91 /include | |
| parent | c9de3168a9568c6fb8038b9b83a912a9a391152b (diff) | |
| download | gdb-cccc84faff88135ea118250d1b19cfb7aac7e8c1.zip gdb-cccc84faff88135ea118250d1b19cfb7aac7e8c1.tar.gz gdb-cccc84faff88135ea118250d1b19cfb7aac7e8c1.tar.bz2 | |
MIPS/opcodes: Free up redundant `g' operand code
In the operand handling rewrite made for the MIPS disassembler with
commit ab90248154ba ("Add structures to describe MIPS operands"),
<https://sourceware.org/ml/binutils/2013-07/msg00135.html>, the `g'
operand code has become redundant for the regular MIPS instruction set
by duplicating the OP_REG_COPRO semantics of the `G' operand code.
Later commit 351cdf24d223 ("Implement O32 FPXX, FP64 and FP64A ABI
extensions") converted the CTTC1 instruction from the `g' to the `G'
operand code, but still left a few instructions behind.
Convert the three remaining instructions still using the `g' code then,
namely: CTTC2, MTTC2 and MTTHC2, and remove all traces of the operand
code, freeing it up for other use.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
and "mtthc2" to using the `G' rather than `g' operand code for
the coprocessor control register referred.
include/
* opcode/mips.h: Complement change made to opcodes and remove
references to the `g' regular MIPS ISA operand code.
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 5 | ||||
| -rw-r--r-- | include/opcode/mips.h | 3 |
2 files changed, 6 insertions, 2 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index 19dc8e3..b97775e 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,8 @@ +2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk> + + * opcode/mips.h: Complement change made to opcodes and remove + references to the `g' regular MIPS ISA operand code. + 2021-05-28 H.J. Lu <hongjiu.lu@intel.com> PR ld/27905 diff --git a/include/opcode/mips.h b/include/opcode/mips.h index f72c5db..9fa9fcb 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -899,7 +899,6 @@ mips_opcode_32bit_p (const struct mips_opcode *mo) "$" 1 bit load high flag (OP_*_MT_H) "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T) "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) - "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD) "+t" 5 bit coprocessor 0 destination register (OP_*_RT) MCU ASE usage: @@ -1001,7 +1000,7 @@ mips_opcode_32bit_p (const struct mips_opcode *mo) "1234567890" "%[]<>(),+-:'@!#$*&\~" "ABCDEFGHIJKLMNOPQRSTUVWXYZ" - "abcdefghijklopqrstuvwxz" + "abcdef hijkl opqrstuvwx z" Extension character sequences used so far ("+" followed by the following), for quick reference when adding more: |