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| author | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2024-01-15 09:35:55 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2024-01-15 11:45:41 +0000 |
| commit | 88601c2d941b004b443dc4bfdf3b93ea1983d136 (patch) | |
| tree | d2ed31930c0f82a30e5090f3a1b70e3a8f3ca681 /include | |
| parent | 89e06ec1521898892e27615714f51d30703d5139 (diff) | |
| download | gdb-88601c2d941b004b443dc4bfdf3b93ea1983d136.zip gdb-88601c2d941b004b443dc4bfdf3b93ea1983d136.tar.gz gdb-88601c2d941b004b443dc4bfdf3b93ea1983d136.tar.bz2 | |
aarch64: Add support for FEAT_SVE2p1.
Hi,
This patch add support for FEAT_SVE2p1 (SVE2.1 Extension) feature
along with +sve2p1 optional flag to enabe this feature.
Also support for following SVE2p1 instructions is added
addqv, andqv, smaxqv, sminqv, umaxqv, uminqv and uminqv.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/aarch64.h | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 648e25f..1af49c4 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -226,6 +226,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_B16B16, /* SME2.1 instructions. */ AARCH64_FEATURE_SME2p1, + /* SVE2.1 instructions. */ + AARCH64_FEATURE_SVE2p1, AARCH64_NUM_FEATURES }; @@ -1000,6 +1002,7 @@ enum aarch64_insn_class cssc, gcs, the, + sve2_urqvs }; /* Opcode enumerators. */ @@ -1272,7 +1275,9 @@ extern const aarch64_opcode aarch64_opcode_table[]; allow. This impacts the constraintts on assembly but yelds no impact on disassembly. */ #define F_OPD_NARROW (1ULL << 33) -/* Next bit is 34. */ +/* For the instruction with size[22:23] field. */ +#define F_OPD_SIZE (1ULL << 34) +/* Next bit is 35. */ /* Instruction constraints. */ /* This instruction has a predication constraint on the instruction at PC+4. */ @@ -1339,7 +1344,8 @@ static inline bool opcode_has_special_coder (const aarch64_opcode *opcode) { return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T - | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) != 0; + | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND + | F_OPD_SIZE)) != 0; } struct aarch64_name_value_pair |