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| author | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2024-01-15 09:34:41 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2024-01-15 11:45:41 +0000 |
| commit | 89e06ec1521898892e27615714f51d30703d5139 (patch) | |
| tree | 2f51b8db85375d158020794c4a4fcbb63033fcd9 /include | |
| parent | 7e8d2d875701971c77224079056a0c8272d63109 (diff) | |
| download | gdb-89e06ec1521898892e27615714f51d30703d5139.zip gdb-89e06ec1521898892e27615714f51d30703d5139.tar.gz gdb-89e06ec1521898892e27615714f51d30703d5139.tar.bz2 | |
aarch64: Add support for FEAT_SME2p1 instructions.
Hi,
This patch add support for FEAT_SME2p1 and "movaz" instructions
along with the optional flag +sme2p1.
Following "movaz" instructions are add:
Move and zero two ZA tile slices to vector registers.
Move and zero four ZA tile slices to vector registers.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/aarch64.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index e2ca923..648e25f 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -224,6 +224,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_SEBEP, /* SVE2.1 and SME2.1 non-widening BFloat16 instructions. */ AARCH64_FEATURE_B16B16, + /* SME2.1 instructions. */ + AARCH64_FEATURE_SME2p1, AARCH64_NUM_FEATURES }; @@ -705,6 +707,14 @@ enum aarch64_opnd AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */ AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */ AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */ + AARCH64_OPND_SME_ZA_array_vrsb_1, /* Tile to vector, two registers (B). */ + AARCH64_OPND_SME_ZA_array_vrsh_1, /* Tile to vector, two registers (H). */ + AARCH64_OPND_SME_ZA_array_vrss_1, /* Tile to vector, two registers (S). */ + AARCH64_OPND_SME_ZA_array_vrsd_1, /* Tile to vector, two registers (D). */ + AARCH64_OPND_SME_ZA_array_vrsb_2, /* Tile to vector, four registers (B). */ + AARCH64_OPND_SME_ZA_array_vrsh_2, /* Tile to vector, four registers (H). */ + AARCH64_OPND_SME_ZA_array_vrss_2, /* Tile to vector, four registers (S). */ + AARCH64_OPND_SME_ZA_array_vrsd_2, /* Tile to vector, four registers (D). */ AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */ AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */ AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */ @@ -962,6 +972,7 @@ enum aarch64_insn_class sme_start, sme_stop, sme2_mov, + sme2_movaz, sve_cpy, sve_index, sve_limm, |