RISC-V: Add support for XCvBitmanip extension in CV32E40P

Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html

Contributors:
  Mary Bennett <mary.bennett682@gmail.com>
  Nandni Jamnadas <nandni.jamnadas@embecosm.com>
  Pietra Ferreira <pietra.ferreira@embecosm.com>
  Charlie Keaney
  Jessica Mills
  Craig Blackmore <craig.blackmore@embecosm.com>
  Simon Cook <simon.cook@embecosm.com>
  Jeremy Bennett <jeremy.bennett@embecosm.com>
  Helene Chelin <helene.chelin@embecosm.com>

bfd/ChangeLog:
	* elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvbitmanip`
	instruction class.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:
	* config/tc-riscv.c (validate_riscv_insn): Add custom operands `Xc6` and `Xc7`.
	(riscv_ip): Likewise.
	* doc/c-riscv.texi: Note XCVbitmanip as an additional ISA extension
	for CORE-V.
	* testsuite/gas/riscv/march-help.l: Add xcvbitmanip.
	* testsuite/gas/riscv/x-cv-bitmanip-fail.d: New Test.
	* testsuite/gas/riscv/x-cv-bitmanip-fail.l: New Test.
	* testsuite/gas/riscv/x-cv-bitmanip-fail.s: New Test.
	* testsuite/gas/riscv/x-cv-bitmanip.d: New Test.
	* testsuite/gas/riscv/x-cv-bitmanip.s: New Test.

include/opcode/ChangeLog:
	* riscv-opc.h: Add corresponding MATCH and MASK macros for
	XCVbitmanip.
	* riscv.h: Add corresponding EXTRACT and ENCODE macros for
	XCVbitmanip.
	(enum riscv_insn_class): Add the XCVbitmanip instruction class.

opcodes/ChangeLog:
	* riscv-dis.c (print_insn_args): Add custom operands `Xc6` and `Xc7`.
	* riscv-opc.c: Add XCvBitmanip instructions.

2 files changed, 44 insertions, 2 deletions

diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 22e63ba..f5d720f 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2650,6 +2650,39 @@
 #define MATCH_CV_SHRR      0x2a00302b
 #define MASK_CV_SWRR       0xfe00707f
 #define MATCH_CV_SWRR      0x2c00302b
+/* Vendor-specific (CORE-V) Xcvbitmanip instructions.  */
+#define MATCH_CV_EXTRACTR     0x3000302b
+#define MATCH_CV_EXTRACTUR    0x3200302b
+#define MATCH_CV_INSERTR      0x3400302b
+#define MATCH_CV_BCLRR        0x3800302b
+#define MATCH_CV_BSETR        0x3a00302b
+#define MATCH_CV_ROR          0x4000302b
+#define MATCH_CV_FF1          0x4200302b
+#define MATCH_CV_FL1          0x4400302b
+#define MATCH_CV_CLB          0x4600302b
+#define MATCH_CV_CNT          0x4800302b
+#define MATCH_CV_EXTRACT      0x5b
+#define MATCH_CV_EXTRACTU     0x4000005b
+#define MATCH_CV_INSERT       0x8000005b
+#define MATCH_CV_BCLR         0x105b
+#define MATCH_CV_BSET         0x4000105b
+#define MATCH_CV_BITREV       0xc000105b
+#define MASK_CV_EXTRACTR      0xfe00707f
+#define MASK_CV_EXTRACTUR     0xfe00707f
+#define MASK_CV_INSERTR       0xfe00707f
+#define MASK_CV_BCLRR         0xfe00707f
+#define MASK_CV_BSETR         0xfe00707f
+#define MASK_CV_ROR           0xfe00707f
+#define MASK_CV_FF1           0xfff0707f
+#define MASK_CV_FL1           0xfff0707f
+#define MASK_CV_CLB           0xfff0707f
+#define MASK_CV_CNT           0xfff0707f
+#define MASK_CV_EXTRACT       0xc000707f
+#define MASK_CV_EXTRACTU      0xc000707f
+#define MASK_CV_INSERT        0xc000707f
+#define MASK_CV_BCLR          0xc000707f
+#define MASK_CV_BSET          0xc000707f
+#define MASK_CV_BITREV        0xf800707f
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 #define MATCH_TH_ADDSL 0x0000100b
 #define MASK_TH_ADDSL 0xf800707f
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 9ccf0ec..cccd21b 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -122,6 +122,10 @@ static inline unsigned int riscv_insn_length (insn_t insn)
   (RV_X(x, 25, 5))
 #define EXTRACT_CV_BI_IMM5(x) \
   (RV_X(x, 20, 5) | (RV_IMM_SIGN_N(x, 20, 5) << 5))
+#define EXTRACT_CV_BITMANIP_UIMM5(x) \
+  (RV_X(x, 25, 5))
+#define EXTRACT_CV_BITMANIP_UIMM2(x) \
+  (RV_X(x, 25, 2))
 
 #define ENCODE_ITYPE_IMM(x) \
   (RV_X(x, 0, 12) << 20)
@@ -180,6 +184,10 @@ static inline unsigned int riscv_insn_length (insn_t insn)
   (RV_X(x, 0, 5) << 20)
 #define ENCODE_CV_IS3_UIMM5(x) \
   (RV_X(x, 0, 5) << 25)
+#define ENCODE_CV_BITMANIP_UIMM5(x) \
+  (RV_X(x, 0, 5) << 25)
+#define ENCODE_CV_BITMANIP_UIMM2(x) \
+  (RV_X(x, 0, 2) << 25)
 
 #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
 #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
@@ -497,10 +505,11 @@ enum riscv_insn_class
   INSN_CLASS_ZACAS,
   INSN_CLASS_ZABHA_AND_ZACAS,
   INSN_CLASS_H,
-  INSN_CLASS_XCVMAC,
   INSN_CLASS_XCVALU,
-  INSN_CLASS_XCVELW,
   INSN_CLASS_XCVBI,
+  INSN_CLASS_XCVBITMANIP,
+  INSN_CLASS_XCVELW,
+  INSN_CLASS_XCVMAC,
   INSN_CLASS_XCVMEM,
   INSN_CLASS_XTHEADBA,
   INSN_CLASS_XTHEADBB,