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-rw-r--r--bfd/elfxx-riscv.c25
-rw-r--r--gas/NEWS2
-rw-r--r--gas/config/tc-riscv.c26
-rw-r--r--gas/doc/c-riscv.texi17
-rw-r--r--gas/testsuite/gas/riscv/march-help.l5
-rw-r--r--gas/testsuite/gas/riscv/x-cv-bitmanip-fail.d3
-rw-r--r--gas/testsuite/gas/riscv/x-cv-bitmanip-fail.l57
-rw-r--r--gas/testsuite/gas/riscv/x-cv-bitmanip-fail.s56
-rw-r--r--gas/testsuite/gas/riscv/x-cv-bitmanip.d119
-rw-r--r--gas/testsuite/gas/riscv/x-cv-bitmanip.s108
-rw-r--r--include/opcode/riscv-opc.h33
-rw-r--r--include/opcode/riscv.h13
-rw-r--r--opcodes/riscv-dis.c8
-rw-r--r--opcodes/riscv-opc.c19
14 files changed, 471 insertions, 20 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index eee8114..d517b2e 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1466,10 +1466,11 @@ static struct riscv_supported_ext riscv_supported_std_zxm_ext[] =
static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
{
- {"xcvmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xcvalu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
- {"xcvelw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xcvbi", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"xcvbitmanip", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"xcvelw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"xcvmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xcvmem", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2721,14 +2722,16 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "svinval");
case INSN_CLASS_H:
return riscv_subset_supports (rps, "h");
- case INSN_CLASS_XCVMAC:
- return riscv_subset_supports (rps, "xcvmac");
case INSN_CLASS_XCVALU:
return riscv_subset_supports (rps, "xcvalu");
- case INSN_CLASS_XCVELW:
- return riscv_subset_supports (rps, "xcvelw");
case INSN_CLASS_XCVBI:
return riscv_subset_supports (rps, "xcvbi");
+ case INSN_CLASS_XCVBITMANIP:
+ return riscv_subset_supports (rps, "xcvbitmanip");
+ case INSN_CLASS_XCVELW:
+ return riscv_subset_supports (rps, "xcvelw");
+ case INSN_CLASS_XCVMAC:
+ return riscv_subset_supports (rps, "xcvmac");
case INSN_CLASS_XCVMEM:
return riscv_subset_supports (rps, "xcvmem");
case INSN_CLASS_XTHEADBA:
@@ -2999,14 +3002,16 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return "svinval";
case INSN_CLASS_H:
return _("h");
- case INSN_CLASS_XCVMAC:
- return "xcvmac";
case INSN_CLASS_XCVALU:
return "xcvalu";
- case INSN_CLASS_XCVELW:
- return "xcvelw";
case INSN_CLASS_XCVBI:
return "xcvbi";
+ case INSN_CLASS_XCVBITMANIP:
+ return "xcvbitmanip";
+ case INSN_CLASS_XCVELW:
+ return "xcvelw";
+ case INSN_CLASS_XCVMAC:
+ return "xcvmac";
case INSN_CLASS_XCVMEM:
return "xcvmem";
case INSN_CLASS_XTHEADBA:
diff --git a/gas/NEWS b/gas/NEWS
index e0484bc..7d634a5 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -2,6 +2,8 @@
* Add support for RISC-V Zimop, Zcmop extensions with version 1.0.
+* Add support for RISC-V CORE-V extension (XCvBitmanip) with version 1.0.
+
Changes in 2.43:
* Add support for LoongArch .option for fine-grained control of assembly
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index c09bd42..779e0b8 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1688,6 +1688,12 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
case '3':
used_bits |= ENCODE_CV_IS3_UIMM5 (-1U);
break;
+ case '6':
+ used_bits |= ENCODE_CV_BITMANIP_UIMM5(-1U);
+ break;
+ case '7':
+ used_bits |= ENCODE_CV_BITMANIP_UIMM2(-1U);
+ break;
default:
goto unknown_validate_operand;
}
@@ -3996,6 +4002,26 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
ip->insn_opcode
|= ENCODE_CV_IS2_UIMM5 (imm_expr->X_add_number);
continue;
+ case '6':
+ my_getExpression (imm_expr, asarg);
+ check_absolute_expr (ip, imm_expr, FALSE);
+ asarg = expr_parse_end;
+ if (imm_expr->X_add_number < 0
+ || imm_expr->X_add_number > 31)
+ break;
+ ip->insn_opcode
+ |= ENCODE_CV_BITMANIP_UIMM5 (imm_expr->X_add_number);
+ continue;
+ case '7':
+ my_getExpression (imm_expr, asarg);
+ check_absolute_expr (ip, imm_expr, FALSE);
+ asarg = expr_parse_end;
+ if (imm_expr->X_add_number < 0
+ || imm_expr->X_add_number > 3)
+ break;
+ ip->insn_opcode
+ |= ENCODE_CV_BITMANIP_UIMM2 (imm_expr->X_add_number);
+ continue;
default:
goto unknown_riscv_ip_operand;
}
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index d396669..cec7457 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -740,13 +740,18 @@ extensions supported and provides the location of their
publicly-released documentation:
@table @r
-@item XCvMac
-The XCvMac extension provides instructions for multiply-accumulate operations.
+@item XCvAlu
+The XCvAlu extension provides instructions for general ALU operations.
It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
-@item XCvAlu
-The XCvAlu extension provides instructions for general ALU operations.
+@item XCvBi
+The XCvBi extension provides instructions for branch immediate operations.
+
+It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
+
+@item XCvBitmanip
+The XCvBitmanip extension provides instructions for bitmanip operations.
It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
@@ -755,8 +760,8 @@ The XCvElw extension provides instructions for event load word operations.
It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
-@item XCvBi
-The XCvBi extension provides instructions for branch immediate operations.
+@item XCvMac
+The XCvMac extension provides instructions for multiply-accumulate operations.
It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index 054c2e9..0d9b4c9 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -131,10 +131,11 @@ All available -march extensions for RISC-V:
svinval 1.0
svnapot 1.0
svpbmt 1.0
- xcvmac 1.0
xcvalu 1.0
- xcvelw 1.0
xcvbi 1.0
+ xcvbitmanip 1.0
+ xcvelw 1.0
+ xcvmac 1.0
xcvmem 1.0
xtheadba 1.0
xtheadbb 1.0
diff --git a/gas/testsuite/gas/riscv/x-cv-bitmanip-fail.d b/gas/testsuite/gas/riscv/x-cv-bitmanip-fail.d
new file mode 100644
index 0000000..a1611e7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-cv-bitmanip-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvbitmanip
+#source: x-cv-bitmanip-fail.s
+#error_output: x-cv-bitmanip-fail.l
diff --git a/gas/testsuite/gas/riscv/x-cv-bitmanip-fail.l b/gas/testsuite/gas/riscv/x-cv-bitmanip-fail.l
new file mode 100644
index 0000000..67bb7d3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-cv-bitmanip-fail.l
@@ -0,0 +1,57 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.bclr x32,x32,20,20'
+.*: Error: illegal operands `cv.bclr x33,x33,20,20'
+.*: Error: illegal operands `cv.bclr x6,x7,0,32'
+.*: Error: illegal operands `cv.bclr x6,x7,32,0'
+.*: Error: illegal operands `cv.bclr x6,x7,0,-1'
+.*: Error: illegal operands `cv.bclr x6,x7,-1,0'
+.*: Error: illegal operands `cv.bclrr x32,x32,x32'
+.*: Error: illegal operands `cv.bclrr x33,x33,x33'
+.*: Error: illegal operands `cv.bitrev x32,x32,2,20'
+.*: Error: illegal operands `cv.bitrev x33,x33,2,20'
+.*: Error: illegal operands `cv.bitrev x6,x7,-1,0'
+.*: Error: illegal operands `cv.bitrev x6,x7,0,-1'
+.*: Error: illegal operands `cv.bitrev x6,x7,0,32'
+.*: Error: illegal operands `cv.bitrev x6,x7,4,0'
+.*: Error: illegal operands `cv.bset x32,x32,20,20'
+.*: Error: illegal operands `cv.bset x33,x33,20,20'
+.*: Error: illegal operands `cv.bset x6,x7,0,32'
+.*: Error: illegal operands `cv.bset x6,x7,32,0'
+.*: Error: illegal operands `cv.bset x6,x7,0,-1'
+.*: Error: illegal operands `cv.bset x6,x7,-1,0'
+.*: Error: illegal operands `cv.bsetr x32,x32,x32'
+.*: Error: illegal operands `cv.bsetr x33,x33,x33'
+.*: Error: illegal operands `cv.clb x32,x32'
+.*: Error: illegal operands `cv.clb x33,x33'
+.*: Error: illegal operands `cv.cnt x32,x32'
+.*: Error: illegal operands `cv.cnt x33,x33'
+.*: Error: illegal operands `cv.extract x32,x32,20,20'
+.*: Error: illegal operands `cv.extract x33,x33,20,20'
+.*: Error: illegal operands `cv.extract x6,x7,0,32'
+.*: Error: illegal operands `cv.extract x6,x7,32,0'
+.*: Error: illegal operands `cv.extract x6,x7,0,-1'
+.*: Error: illegal operands `cv.extract x6,x7,-1,0'
+.*: Error: illegal operands `cv.extractr x32,x32,x32'
+.*: Error: illegal operands `cv.extractr x33,x33,x33'
+.*: Error: illegal operands `cv.extractu x32,x32,20,20'
+.*: Error: illegal operands `cv.extractu x33,x33,20,20'
+.*: Error: illegal operands `cv.extractu x6,x7,0,32'
+.*: Error: illegal operands `cv.extractu x6,x7,32,0'
+.*: Error: illegal operands `cv.extractu x6,x7,0,-1'
+.*: Error: illegal operands `cv.extractu x6,x7,-1,0'
+.*: Error: illegal operands `cv.extractur x32,x32,x32'
+.*: Error: illegal operands `cv.extractur x33,x33,x33'
+.*: Error: illegal operands `cv.ff1 x32,x32'
+.*: Error: illegal operands `cv.ff1 x33,x33'
+.*: Error: illegal operands `cv.fl1 x32,x32'
+.*: Error: illegal operands `cv.fl1 x33,x33'
+.*: Error: illegal operands `cv.insert x32,x32,20,20'
+.*: Error: illegal operands `cv.insert x33,x33,20,20'
+.*: Error: illegal operands `cv.insert x6,x7,0,32'
+.*: Error: illegal operands `cv.insert x6,x7,32,0'
+.*: Error: illegal operands `cv.insert x6,x7,0,-1'
+.*: Error: illegal operands `cv.insert x6,x7,-1,0'
+.*: Error: illegal operands `cv.insertr x32,x32,x32'
+.*: Error: illegal operands `cv.insertr x33,x33,x33'
+.*: Error: illegal operands `cv.ror x32,x32,x32'
+.*: Error: illegal operands `cv.ror x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/x-cv-bitmanip-fail.s b/gas/testsuite/gas/riscv/x-cv-bitmanip-fail.s
new file mode 100644
index 0000000..031ba52
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-cv-bitmanip-fail.s
@@ -0,0 +1,56 @@
+ cv.bclr x32, x32, 20, 20
+ cv.bclr x33, x33, 20, 20
+ cv.bclr x6, x7, 0, 32
+ cv.bclr x6, x7, 32, 0
+ cv.bclr x6, x7, 0, -1
+ cv.bclr x6, x7, -1, 0
+ cv.bclrr x32, x32, x32
+ cv.bclrr x33, x33, x33
+ cv.bitrev x32, x32, 2, 20
+ cv.bitrev x33, x33, 2, 20
+ cv.bitrev x6, x7, -1, 0
+ cv.bitrev x6, x7, 0, -1
+ cv.bitrev x6, x7, 0, 32
+ cv.bitrev x6, x7, 4, 0
+ cv.bset x32, x32, 20, 20
+ cv.bset x33, x33, 20, 20
+ cv.bset x6, x7, 0, 32
+ cv.bset x6, x7, 32, 0
+ cv.bset x6, x7, 0, -1
+ cv.bset x6, x7, -1, 0
+ cv.bsetr x32, x32, x32
+ cv.bsetr x33, x33, x33
+ cv.clb x32, x32
+ cv.clb x33, x33
+ cv.cnt x32, x32
+ cv.cnt x33, x33
+ cv.extract x32, x32, 20, 20
+ cv.extract x33, x33, 20, 20
+ cv.extract x6, x7, 0, 32
+ cv.extract x6, x7, 32, 0
+ cv.extract x6, x7, 0, -1
+ cv.extract x6, x7, -1, 0
+ cv.extractr x32, x32, x32
+ cv.extractr x33, x33, x33
+ cv.extractu x32, x32, 20, 20
+ cv.extractu x33, x33, 20, 20
+ cv.extractu x6, x7, 0, 32
+ cv.extractu x6, x7, 32, 0
+ cv.extractu x6, x7, 0, -1
+ cv.extractu x6, x7, -1, 0
+ cv.extractur x32, x32, x32
+ cv.extractur x33, x33, x33
+ cv.ff1 x32, x32
+ cv.ff1 x33, x33
+ cv.fl1 x32, x32
+ cv.fl1 x33, x33
+ cv.insert x32, x32, 20, 20
+ cv.insert x33, x33, 20, 20
+ cv.insert x6, x7, 0, 32
+ cv.insert x6, x7, 32, 0
+ cv.insert x6, x7, 0, -1
+ cv.insert x6, x7, -1, 0
+ cv.insertr x32, x32, x32
+ cv.insertr x33, x33, x33
+ cv.ror x32, x32, x32
+ cv.ror x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/x-cv-bitmanip.d b/gas/testsuite/gas/riscv/x-cv-bitmanip.d
new file mode 100644
index 0000000..ba891af
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-cv-bitmanip.d
@@ -0,0 +1,119 @@
+#as: -march=rv32i_xcvbitmanip
+#source: x-cv-bitmanip.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+
+ 0: 2940105b cv.bclr zero,zero,20,20
+ 4: 294090db cv.bclr ra,ra,20,20
+ 8: 2941115b cv.bclr sp,sp,20,20
+ c: 2944145b cv.bclr s0,s0,20,20
+ 10: 294a1a5b cv.bclr s4,s4,20,20
+ 14: 294f9fdb cv.bclr t6,t6,20,20
+ 18: 0003935b cv.bclr t1,t2,0,0
+ 1c: 3ff3935b cv.bclr t1,t2,31,31
+ 20: 3800302b cv.bclrr zero,zero,zero
+ 24: 3810b0ab cv.bclrr ra,ra,ra
+ 28: 3821312b cv.bclrr sp,sp,sp
+ 2c: 3884342b cv.bclrr s0,s0,s0
+ 30: 394a3a2b cv.bclrr s4,s4,s4
+ 34: 39ffbfab cv.bclrr t6,t6,t6
+ 38: c540105b cv.bitrev zero,zero,2,20
+ 3c: c54090db cv.bitrev ra,ra,2,20
+ 40: c541115b cv.bitrev sp,sp,2,20
+ 44: c544145b cv.bitrev s0,s0,2,20
+ 48: c54a1a5b cv.bitrev s4,s4,2,20
+ 4c: c54f9fdb cv.bitrev t6,t6,2,20
+ 50: c003935b cv.bitrev t1,t2,0,0
+ 54: c7f3935b cv.bitrev t1,t2,3,31
+ 58: 6940105b cv.bset zero,zero,20,20
+ 5c: 694090db cv.bset ra,ra,20,20
+ 60: 6941115b cv.bset sp,sp,20,20
+ 64: 6944145b cv.bset s0,s0,20,20
+ 68: 694a1a5b cv.bset s4,s4,20,20
+ 6c: 694f9fdb cv.bset t6,t6,20,20
+ 70: 4003935b cv.bset t1,t2,0,0
+ 74: 7ff3935b cv.bset t1,t2,31,31
+ 78: 3a00302b cv.bsetr zero,zero,zero
+ 7c: 3a10b0ab cv.bsetr ra,ra,ra
+ 80: 3a21312b cv.bsetr sp,sp,sp
+ 84: 3a84342b cv.bsetr s0,s0,s0
+ 88: 3b4a3a2b cv.bsetr s4,s4,s4
+ 8c: 3bffbfab cv.bsetr t6,t6,t6
+ 90: 4600302b cv.clb zero,zero
+ 94: 4600b0ab cv.clb ra,ra
+ 98: 4601312b cv.clb sp,sp
+ 9c: 4604342b cv.clb s0,s0
+ a0: 460a3a2b cv.clb s4,s4
+ a4: 460fbfab cv.clb t6,t6
+ a8: 4800302b cv.cnt zero,zero
+ ac: 4800b0ab cv.cnt ra,ra
+ b0: 4801312b cv.cnt sp,sp
+ b4: 4804342b cv.cnt s0,s0
+ b8: 480a3a2b cv.cnt s4,s4
+ bc: 480fbfab cv.cnt t6,t6
+ c0: 2940005b cv.extract zero,zero,20,20
+ c4: 294080db cv.extract ra,ra,20,20
+ c8: 2941015b cv.extract sp,sp,20,20
+ cc: 2944045b cv.extract s0,s0,20,20
+ d0: 294a0a5b cv.extract s4,s4,20,20
+ d4: 294f8fdb cv.extract t6,t6,20,20
+ d8: 0003835b cv.extract t1,t2,0,0
+ dc: 3ff3835b cv.extract t1,t2,31,31
+ e0: 3000302b cv.extractr zero,zero,zero
+ e4: 3010b0ab cv.extractr ra,ra,ra
+ e8: 3021312b cv.extractr sp,sp,sp
+ ec: 3084342b cv.extractr s0,s0,s0
+ f0: 314a3a2b cv.extractr s4,s4,s4
+ f4: 31ffbfab cv.extractr t6,t6,t6
+ f8: 6940005b cv.extractu zero,zero,20,20
+ fc: 694080db cv.extractu ra,ra,20,20
+ 100: 6941015b cv.extractu sp,sp,20,20
+ 104: 6944045b cv.extractu s0,s0,20,20
+ 108: 694a0a5b cv.extractu s4,s4,20,20
+ 10c: 694f8fdb cv.extractu t6,t6,20,20
+ 110: 4003835b cv.extractu t1,t2,0,0
+ 114: 7ff3835b cv.extractu t1,t2,31,31
+ 118: 3200302b cv.extractur zero,zero,zero
+ 11c: 3210b0ab cv.extractur ra,ra,ra
+ 120: 3221312b cv.extractur sp,sp,sp
+ 124: 3284342b cv.extractur s0,s0,s0
+ 128: 334a3a2b cv.extractur s4,s4,s4
+ 12c: 33ffbfab cv.extractur t6,t6,t6
+ 130: 4200302b cv.ff1 zero,zero
+ 134: 4200b0ab cv.ff1 ra,ra
+ 138: 4201312b cv.ff1 sp,sp
+ 13c: 4204342b cv.ff1 s0,s0
+ 140: 420a3a2b cv.ff1 s4,s4
+ 144: 420fbfab cv.ff1 t6,t6
+ 148: 4400302b cv.fl1 zero,zero
+ 14c: 4400b0ab cv.fl1 ra,ra
+ 150: 4401312b cv.fl1 sp,sp
+ 154: 4404342b cv.fl1 s0,s0
+ 158: 440a3a2b cv.fl1 s4,s4
+ 15c: 440fbfab cv.fl1 t6,t6
+ 160: a940005b cv.insert zero,zero,20,20
+ 164: a94080db cv.insert ra,ra,20,20
+ 168: a941015b cv.insert sp,sp,20,20
+ 16c: a944045b cv.insert s0,s0,20,20
+ 170: a94a0a5b cv.insert s4,s4,20,20
+ 174: a94f8fdb cv.insert t6,t6,20,20
+ 178: 8003835b cv.insert t1,t2,0,0
+ 17c: bff3835b cv.insert t1,t2,31,31
+ 180: 3400302b cv.insertr zero,zero,zero
+ 184: 3410b0ab cv.insertr ra,ra,ra
+ 188: 3421312b cv.insertr sp,sp,sp
+ 18c: 3484342b cv.insertr s0,s0,s0
+ 190: 354a3a2b cv.insertr s4,s4,s4
+ 194: 35ffbfab cv.insertr t6,t6,t6
+ 198: 4000302b cv.ror zero,zero,zero
+ 19c: 4010b0ab cv.ror ra,ra,ra
+ 1a0: 4021312b cv.ror sp,sp,sp
+ 1a4: 4084342b cv.ror s0,s0,s0
+ 1a8: 414a3a2b cv.ror s4,s4,s4
+ 1ac: 41ffbfab cv.ror t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/x-cv-bitmanip.s b/gas/testsuite/gas/riscv/x-cv-bitmanip.s
new file mode 100644
index 0000000..d83bec0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-cv-bitmanip.s
@@ -0,0 +1,108 @@
+ cv.bclr x0, x0, 20, 20
+ cv.bclr x1, x1, 20, 20
+ cv.bclr x2, x2, 20, 20
+ cv.bclr x8, x8, 20, 20
+ cv.bclr x20, x20, 20, 20
+ cv.bclr x31, x31, 20, 20
+ cv.bclr x6, x7, 0, 0
+ cv.bclr x6, x7, 31, 31
+ cv.bclrr x0, x0, x0
+ cv.bclrr x1, x1, x1
+ cv.bclrr x2, x2, x2
+ cv.bclrr x8, x8, x8
+ cv.bclrr x20, x20, x20
+ cv.bclrr x31, x31, x31
+ cv.bitrev x0, x0, 2, 20
+ cv.bitrev x1, x1, 2, 20
+ cv.bitrev x2, x2, 2, 20
+ cv.bitrev x8, x8, 2, 20
+ cv.bitrev x20, x20, 2, 20
+ cv.bitrev x31, x31, 2, 20
+ cv.bitrev x6, x7, 0, 0
+ cv.bitrev x6, x7, 3, 31
+ cv.bset x0, x0, 20, 20
+ cv.bset x1, x1, 20, 20
+ cv.bset x2, x2, 20, 20
+ cv.bset x8, x8, 20, 20
+ cv.bset x20, x20, 20, 20
+ cv.bset x31, x31, 20, 20
+ cv.bset x6, x7, 0, 0
+ cv.bset x6, x7, 31, 31
+ cv.bsetr x0, x0, x0
+ cv.bsetr x1, x1, x1
+ cv.bsetr x2, x2, x2
+ cv.bsetr x8, x8, x8
+ cv.bsetr x20, x20, x20
+ cv.bsetr x31, x31, x31
+ cv.clb x0, x0
+ cv.clb x1, x1
+ cv.clb x2, x2
+ cv.clb x8, x8
+ cv.clb x20, x20
+ cv.clb x31, x31
+ cv.cnt x0, x0
+ cv.cnt x1, x1
+ cv.cnt x2, x2
+ cv.cnt x8, x8
+ cv.cnt x20, x20
+ cv.cnt x31, x31
+ cv.extract x0, x0, 20, 20
+ cv.extract x1, x1, 20, 20
+ cv.extract x2, x2, 20, 20
+ cv.extract x8, x8, 20, 20
+ cv.extract x20, x20, 20, 20
+ cv.extract x31, x31, 20, 20
+ cv.extract x6, x7, 0, 0
+ cv.extract x6, x7, 31, 31
+ cv.extractr x0, x0, x0
+ cv.extractr x1, x1, x1
+ cv.extractr x2, x2, x2
+ cv.extractr x8, x8, x8
+ cv.extractr x20, x20, x20
+ cv.extractr x31, x31, x31
+ cv.extractu x0, x0, 20, 20
+ cv.extractu x1, x1, 20, 20
+ cv.extractu x2, x2, 20, 20
+ cv.extractu x8, x8, 20, 20
+ cv.extractu x20, x20, 20, 20
+ cv.extractu x31, x31, 20, 20
+ cv.extractu x6, x7, 0, 0
+ cv.extractu x6, x7, 31, 31
+ cv.extractur x0, x0, x0
+ cv.extractur x1, x1, x1
+ cv.extractur x2, x2, x2
+ cv.extractur x8, x8, x8
+ cv.extractur x20, x20, x20
+ cv.extractur x31, x31, x31
+ cv.ff1 x0, x0
+ cv.ff1 x1, x1
+ cv.ff1 x2, x2
+ cv.ff1 x8, x8
+ cv.ff1 x20, x20
+ cv.ff1 x31, x31
+ cv.fl1 x0, x0
+ cv.fl1 x1, x1
+ cv.fl1 x2, x2
+ cv.fl1 x8, x8
+ cv.fl1 x20, x20
+ cv.fl1 x31, x31
+ cv.insert x0, x0, 20, 20
+ cv.insert x1, x1, 20, 20
+ cv.insert x2, x2, 20, 20
+ cv.insert x8, x8, 20, 20
+ cv.insert x20, x20, 20, 20
+ cv.insert x31, x31, 20, 20
+ cv.insert x6, x7, 0, 0
+ cv.insert x6, x7, 31, 31
+ cv.insertr x0, x0, x0
+ cv.insertr x1, x1, x1
+ cv.insertr x2, x2, x2
+ cv.insertr x8, x8, x8
+ cv.insertr x20, x20, x20
+ cv.insertr x31, x31, x31
+ cv.ror x0, x0, x0
+ cv.ror x1, x1, x1
+ cv.ror x2, x2, x2
+ cv.ror x8, x8, x8
+ cv.ror x20, x20, x20
+ cv.ror x31, x31, x31
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 22e63ba..f5d720f 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2650,6 +2650,39 @@
#define MATCH_CV_SHRR 0x2a00302b
#define MASK_CV_SWRR 0xfe00707f
#define MATCH_CV_SWRR 0x2c00302b
+/* Vendor-specific (CORE-V) Xcvbitmanip instructions. */
+#define MATCH_CV_EXTRACTR 0x3000302b
+#define MATCH_CV_EXTRACTUR 0x3200302b
+#define MATCH_CV_INSERTR 0x3400302b
+#define MATCH_CV_BCLRR 0x3800302b
+#define MATCH_CV_BSETR 0x3a00302b
+#define MATCH_CV_ROR 0x4000302b
+#define MATCH_CV_FF1 0x4200302b
+#define MATCH_CV_FL1 0x4400302b
+#define MATCH_CV_CLB 0x4600302b
+#define MATCH_CV_CNT 0x4800302b
+#define MATCH_CV_EXTRACT 0x5b
+#define MATCH_CV_EXTRACTU 0x4000005b
+#define MATCH_CV_INSERT 0x8000005b
+#define MATCH_CV_BCLR 0x105b
+#define MATCH_CV_BSET 0x4000105b
+#define MATCH_CV_BITREV 0xc000105b
+#define MASK_CV_EXTRACTR 0xfe00707f
+#define MASK_CV_EXTRACTUR 0xfe00707f
+#define MASK_CV_INSERTR 0xfe00707f
+#define MASK_CV_BCLRR 0xfe00707f
+#define MASK_CV_BSETR 0xfe00707f
+#define MASK_CV_ROR 0xfe00707f
+#define MASK_CV_FF1 0xfff0707f
+#define MASK_CV_FL1 0xfff0707f
+#define MASK_CV_CLB 0xfff0707f
+#define MASK_CV_CNT 0xfff0707f
+#define MASK_CV_EXTRACT 0xc000707f
+#define MASK_CV_EXTRACTU 0xc000707f
+#define MASK_CV_INSERT 0xc000707f
+#define MASK_CV_BCLR 0xc000707f
+#define MASK_CV_BSET 0xc000707f
+#define MASK_CV_BITREV 0xf800707f
/* Vendor-specific (T-Head) XTheadBa instructions. */
#define MATCH_TH_ADDSL 0x0000100b
#define MASK_TH_ADDSL 0xf800707f
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 9ccf0ec..cccd21b 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -122,6 +122,10 @@ static inline unsigned int riscv_insn_length (insn_t insn)
(RV_X(x, 25, 5))
#define EXTRACT_CV_BI_IMM5(x) \
(RV_X(x, 20, 5) | (RV_IMM_SIGN_N(x, 20, 5) << 5))
+#define EXTRACT_CV_BITMANIP_UIMM5(x) \
+ (RV_X(x, 25, 5))
+#define EXTRACT_CV_BITMANIP_UIMM2(x) \
+ (RV_X(x, 25, 2))
#define ENCODE_ITYPE_IMM(x) \
(RV_X(x, 0, 12) << 20)
@@ -180,6 +184,10 @@ static inline unsigned int riscv_insn_length (insn_t insn)
(RV_X(x, 0, 5) << 20)
#define ENCODE_CV_IS3_UIMM5(x) \
(RV_X(x, 0, 5) << 25)
+#define ENCODE_CV_BITMANIP_UIMM5(x) \
+ (RV_X(x, 0, 5) << 25)
+#define ENCODE_CV_BITMANIP_UIMM2(x) \
+ (RV_X(x, 0, 2) << 25)
#define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
#define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
@@ -497,10 +505,11 @@ enum riscv_insn_class
INSN_CLASS_ZACAS,
INSN_CLASS_ZABHA_AND_ZACAS,
INSN_CLASS_H,
- INSN_CLASS_XCVMAC,
INSN_CLASS_XCVALU,
- INSN_CLASS_XCVELW,
INSN_CLASS_XCVBI,
+ INSN_CLASS_XCVBITMANIP,
+ INSN_CLASS_XCVELW,
+ INSN_CLASS_XCVMAC,
INSN_CLASS_XCVMEM,
INSN_CLASS_XTHEADBA,
INSN_CLASS_XTHEADBB,
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 9c5e6ce..f292fc7 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -803,6 +803,14 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
print (info->stream, dis_style_immediate, "%d",
((int) EXTRACT_CV_BI_IMM5 (l)));
break;
+ case '6':
+ print (info->stream, dis_style_immediate, "%d",
+ ((int) EXTRACT_CV_BITMANIP_UIMM5 (l)));
+ break;
+ case '7':
+ print (info->stream, dis_style_immediate, "%d",
+ ((int) EXTRACT_CV_BITMANIP_UIMM2 (l)));
+ break;
default:
goto undefined_modifier;
}
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index e6831bd..8addcd0 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2339,6 +2339,25 @@ const struct riscv_opcode riscv_opcodes[] =
{"cv.sw", 0, INSN_CLASS_XCVMEM, "t,d(s)", MATCH_CV_SWRR, MASK_CV_SWRR, match_opcode, 0},
{"cv.sw", 0, INSN_CLASS_XCVMEM, "t,(s),d", MATCH_CV_SWRRPOST, MASK_CV_SWRRPOST, match_opcode, 0},
+/* Vendor-specific (CORE-V) Xcvbitmanip instructions. */
+{"cv.extractr", 0, INSN_CLASS_XCVBITMANIP, "d,s,t", MATCH_CV_EXTRACTR, MASK_CV_EXTRACTR, match_opcode, 0},
+{"cv.extractur", 0, INSN_CLASS_XCVBITMANIP, "d,s,t", MATCH_CV_EXTRACTUR, MASK_CV_EXTRACTUR, match_opcode, 0},
+{"cv.insertr", 0, INSN_CLASS_XCVBITMANIP, "d,s,t", MATCH_CV_INSERTR, MASK_CV_INSERTR, match_opcode, 0},
+{"cv.bclrr", 0, INSN_CLASS_XCVBITMANIP, "d,s,t", MATCH_CV_BCLRR, MASK_CV_BCLRR, match_opcode, 0},
+{"cv.bsetr", 0, INSN_CLASS_XCVBITMANIP, "d,s,t", MATCH_CV_BSETR, MASK_CV_BSETR, match_opcode, 0},
+{"cv.ror", 0, INSN_CLASS_XCVBITMANIP, "d,s,t", MATCH_CV_ROR, MASK_CV_ROR, match_opcode, 0},
+{"cv.ff1", 0, INSN_CLASS_XCVBITMANIP, "d,s", MATCH_CV_FF1, MASK_CV_FF1, match_opcode, 0},
+{"cv.fl1", 0, INSN_CLASS_XCVBITMANIP, "d,s", MATCH_CV_FL1, MASK_CV_FL1, match_opcode, 0},
+{"cv.clb", 0, INSN_CLASS_XCVBITMANIP, "d,s", MATCH_CV_CLB, MASK_CV_CLB, match_opcode, 0},
+{"cv.cnt", 0, INSN_CLASS_XCVBITMANIP, "d,s", MATCH_CV_CNT, MASK_CV_CNT, match_opcode, 0},
+
+{"cv.extract", 0, INSN_CLASS_XCVBITMANIP, "d,s,Xc6,Xc2", MATCH_CV_EXTRACT, MASK_CV_EXTRACT, match_opcode, 0},
+{"cv.extractu", 0, INSN_CLASS_XCVBITMANIP, "d,s,Xc6,Xc2", MATCH_CV_EXTRACTU, MASK_CV_EXTRACTU, match_opcode, 0},
+{"cv.insert", 0, INSN_CLASS_XCVBITMANIP, "d,s,Xc6,Xc2", MATCH_CV_INSERT, MASK_CV_INSERT, match_opcode, 0},
+{"cv.bclr", 0, INSN_CLASS_XCVBITMANIP, "d,s,Xc6,Xc2", MATCH_CV_BCLR, MASK_CV_BCLR, match_opcode, 0},
+{"cv.bset", 0, INSN_CLASS_XCVBITMANIP, "d,s,Xc6,Xc2", MATCH_CV_BSET, MASK_CV_BSET, match_opcode, 0},
+{"cv.bitrev", 0, INSN_CLASS_XCVBITMANIP, "d,s,Xc7,Xc2", MATCH_CV_BITREV, MASK_CV_BITREV, match_opcode, 0},
+
/* Vendor-specific (T-Head) XTheadBa instructions. */
{"th.addsl", 0, INSN_CLASS_XTHEADBA, "d,s,t,Xtu2@25", MATCH_TH_ADDSL, MASK_TH_ADDSL, match_opcode, 0},
generated by cgit v1.1 at 2024-11-18 11:01:59 +0000