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2024-07-02gcc: docs: Fix documentation of two hooksMatthew Malcomson1-10/+8
2024-06-25Replace {FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE with new hook mode_for_floating_typeKewen Lin1-0/+9
2024-06-13[APX CCMP] Add targetm.have_ccmp hook [PR115370]Hongyu Wang1-0/+10
2024-06-07enable adjustment of return_pc debug attrsAlexandre Oliva1-0/+9
2024-05-10c++, mingw: Fix up types of dtor hooks to __cxa_{,thread_}atexit/__cxa_throw ...Jakub Jelinek1-1/+12
2024-01-03Update copyright years.Jakub Jelinek1-1/+1
2023-12-16Add support for target_version attributeAndrew Carlotti1-0/+17
2023-12-15bitint: Introduce abi_limb_modeJakub Jelinek1-2/+2
2023-12-07strub: enable conditional supportAlexandre Oliva1-0/+8
2023-12-05Restore build with GCC 4.8 to GCC 5Richard Sandiford1-1/+1
2023-12-05Allow targets to add USEs to asmsRichard Sandiford1-2/+3
2023-12-05Add a new target hook: TARGET_START_CALL_ARGSRichard Sandiford1-12/+47
2023-12-05Add a target hook for sibcall epiloguesRichard Sandiford1-0/+9
2023-12-05Allow prologues and epilogues to be inserted laterRichard Sandiford1-0/+21
2023-12-02Allow target attributes in non-gnu namespacesRichard Sandiford1-7/+28
2023-11-23gcc: Introduce -fhardenedMarek Polacek1-0/+7
2023-11-18Add TARGET_HAVE_LIBATOMICSebastian Huber1-0/+8
2023-11-18gcov: Remove TARGET_GCOV_TYPE_SIZE target hookSebastian Huber1-12/+0
2023-11-11mode-switching: Add a backprop hookRichard Sandiford1-0/+29
2023-11-11mode-switching: Add a target-configurable confluence operatorRichard Sandiford1-0/+17
2023-11-11mode-switching: Pass the set of live registers to the after hookRichard Sandiford1-1/+3
2023-11-11mode-switching: Pass set of live registers to the needed hookRichard Sandiford1-2/+3
2023-11-11mode-switching: Allow targets to set the mode for EH handlersRichard Sandiford1-0/+7
2023-11-11mode-switching: Tweak the macro/hook documentationRichard Sandiford1-16/+27
2023-09-06Middle-end _BitInt support [PR102989]Jakub Jelinek1-0/+19
2023-08-23rtl: use rtx_code for gen_ccmp_first and gen_ccmp_nextRichard Earnshaw1-2/+2
2023-08-09targhooks: Extend legitimate_address_p with code_helper [PR110248]Kewen Lin1-5/+13
2023-05-30stor-layout, aarch64: Express SRA intrinsics with RTL codesKyrylo Tkachov1-1/+15
2023-04-28Add targetm.libm_function_max_errorJakub Jelinek1-0/+17
2023-04-01aarch64, builtins: Include PR registers in FUNCTION_ARG_REGNO_P etc. [PR109254]Jakub Jelinek1-2/+4
2023-03-23Remove TARGET_GEN_MEMSET_SCRATCH_RTX since it's not used anymore.liuhongt1-9/+0
2023-03-12middle-end: Implement preferred_div_as_shifts_over_mult [PR108583]Tamar Christina1-0/+12
2023-03-12middle-end: Revert can_special_div_by_const changes [PR108583]Tamar Christina1-19/+0
2023-03-03c++, v3: Emit fundamental tinfos for _Float16/decltype(0.0bf16) types on ia32...Jakub Jelinek1-0/+13
2023-01-03Revert "Compute a table of DWARF register sizes at compile"Florian Weimer1-4/+4
2023-01-02Compute a table of DWARF register sizes at compileFlorian Weimer1-4/+4
2023-01-02Update copyright years.Jakub Jelinek1-1/+1
2022-11-25OpenMP: Generate SIMD clones for functions with "declare target"Sandra Loosemore1-1/+1
2022-11-14middle-end: Fix can_special_div_by_const doc.Tamar Christina1-1/+1
2022-11-14middle-end: Support not decomposing specific divisions during vectorization.Tamar Christina1-0/+19
2022-11-14Revert "sphinx: port .def files to RST"Martin Liska1-1657/+1648
2022-11-14Revert "sphinx: use proper lexers for target macros"Martin Liska1-6/+6
2022-11-09sphinx: use proper lexers for target macrosMartin Liska1-6/+6
2022-11-09sphinx: port .def files to RSTMartin Liska1-1648/+1657
2022-10-28c: tree: target: C2x (...) function prototypes and va_start relaxationJoseph Myers1-1/+3
2022-09-30Document -fexcess-precision=16 in target.defH.J. Lu1-1/+1
2022-08-30omp-simd-clone: Allow fixed-lane vectorsAndrew Stubbs1-0/+3
2022-05-25Add new parameter to vec_perm_const hook for specifying operand mode.Prathamesh Kulkarni1-7/+11
2022-04-01Add an assertion: the zeroed_hardregs set is a subset of all call used regs.Qing Zhao1-0/+7
2022-02-21aarch64: Add compiler support for Shadow Call StackDan Li1-0/+8